forked from OSchip/llvm-project
[AMDGPU] Fix pointer info for pseudo source for r600
The pointer info for pseudo source for r600 is not correct when alloca addr space is not 0, which causes invalid SDNode for r600---amdgiz. This patch fixes that. Differential Revision: https://reviews.llvm.org/D39670 llvm-svn: 317861
This commit is contained in:
Yaxun Liu
parent
9278019eb3
commit
920cc2f813
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@ -1493,3 +1493,21 @@ void R600InstrInfo::clearFlag(MachineInstr &MI, unsigned Operand,
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FlagOp.setImm(InstFlags);
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}
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}
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unsigned R600InstrInfo::getAddressSpaceForPseudoSourceKind(
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PseudoSourceValue::PSVKind Kind) const {
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switch (Kind) {
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case PseudoSourceValue::Stack:
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case PseudoSourceValue::FixedStack:
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return AMDGPUASI.PRIVATE_ADDRESS;
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case PseudoSourceValue::ConstantPool:
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case PseudoSourceValue::GOT:
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case PseudoSourceValue::JumpTable:
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case PseudoSourceValue::GlobalValueCallEntry:
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case PseudoSourceValue::ExternalSymbolCallEntry:
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case PseudoSourceValue::TargetCustom:
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return AMDGPUASI.CONSTANT_ADDRESS;
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}
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llvm_unreachable("Invalid pseudo source kind");
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return AMDGPUASI.PRIVATE_ADDRESS;
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}
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@ -318,6 +318,9 @@ public:
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bool isRegisterLoad(const MachineInstr &MI) const {
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return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_LOAD;
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}
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unsigned getAddressSpaceForPseudoSourceKind(
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PseudoSourceValue::PSVKind Kind) const override;
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};
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namespace AMDGPU {
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@ -1,6 +1,6 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}constant_load_i1:
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; GCN: buffer_load_ubyte
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@ -1,6 +1,6 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}global_load_i1:
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; GCN: buffer_load_ubyte
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@ -1,6 +1,6 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}local_load_i1:
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; GCN: ds_read_u8
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@ -1,9 +1,10 @@
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; RUN: llc -march=amdgcn -mcpu=verde -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=verde -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG -check-prefix=FUNC %s
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; RUN: opt -S -mtriple=amdgcn-- -amdgpu-promote-alloca -sroa -instcombine < %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck --check-prefix=EG -check-prefix=FUNC %s
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; RUN: opt -S -mtriple=amdgcn---amdgiz -amdgpu-promote-alloca -sroa -instcombine < %s | FileCheck -check-prefix=OPT %s
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target datalayout = "A5"
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; OPT-LABEL: @vector_read(
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; OPT: %0 = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
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@ -17,17 +18,17 @@
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; EG: MOVA_INT
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define amdgpu_kernel void @vector_read(i32 addrspace(1)* %out, i32 %index) {
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entry:
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%tmp = alloca [4 x i32]
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%x = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0
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%y = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 3
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store i32 0, i32* %x
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store i32 1, i32* %y
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store i32 2, i32* %z
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store i32 3, i32* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 %index
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%tmp2 = load i32, i32* %tmp1
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%tmp = alloca [4 x i32], addrspace(5)
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%x = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 0
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%y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
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store i32 0, i32 addrspace(5)* %x
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store i32 1, i32 addrspace(5)* %y
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store i32 2, i32 addrspace(5)* %z
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store i32 3, i32 addrspace(5)* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %index
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%tmp2 = load i32, i32 addrspace(5)* %tmp1
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store i32 %tmp2, i32 addrspace(1)* %out
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ret void
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}
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@ -46,19 +47,19 @@ entry:
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; EG: MOVA_INT
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define amdgpu_kernel void @vector_write(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) {
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entry:
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%tmp = alloca [4 x i32]
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%x = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0
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%y = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 3
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store i32 0, i32* %x
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store i32 0, i32* %y
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store i32 0, i32* %z
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store i32 0, i32* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 %w_index
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store i32 1, i32* %tmp1
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%tmp2 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 %r_index
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%tmp3 = load i32, i32* %tmp2
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%tmp = alloca [4 x i32], addrspace(5)
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%x = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 0
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%y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
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store i32 0, i32 addrspace(5)* %x
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store i32 0, i32 addrspace(5)* %y
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store i32 0, i32 addrspace(5)* %z
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store i32 0, i32 addrspace(5)* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %w_index
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store i32 1, i32 addrspace(5)* %tmp1
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%tmp2 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %r_index
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%tmp3 = load i32, i32 addrspace(5)* %tmp2
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store i32 %tmp3, i32 addrspace(1)* %out
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ret void
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}
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@ -73,19 +74,19 @@ entry:
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; EG: STORE_RAW
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define amdgpu_kernel void @bitcast_gep(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) {
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entry:
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%tmp = alloca [4 x i32]
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%x = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0
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%y = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 3
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store i32 0, i32* %x
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store i32 0, i32* %y
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store i32 0, i32* %z
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store i32 0, i32* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 1
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%tmp2 = bitcast i32* %tmp1 to [4 x i32]*
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%tmp3 = getelementptr [4 x i32], [4 x i32]* %tmp2, i32 0, i32 0
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%tmp4 = load i32, i32* %tmp3
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%tmp = alloca [4 x i32], addrspace(5)
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%x = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 0
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%y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
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store i32 0, i32 addrspace(5)* %x
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store i32 0, i32 addrspace(5)* %y
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store i32 0, i32 addrspace(5)* %z
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store i32 0, i32 addrspace(5)* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%tmp2 = bitcast i32 addrspace(5)* %tmp1 to [4 x i32] addrspace(5)*
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%tmp3 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp2, i32 0, i32 0
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%tmp4 = load i32, i32 addrspace(5)* %tmp3
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store i32 %tmp4, i32 addrspace(1)* %out
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ret void
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}
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@ -95,18 +96,18 @@ entry:
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; OPT: store i32 %0, i32 addrspace(1)* %out, align 4
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define amdgpu_kernel void @vector_read_bitcast_gep(i32 addrspace(1)* %out, i32 %index) {
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entry:
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%tmp = alloca [4 x i32]
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%x = getelementptr inbounds [4 x i32], [4 x i32]* %tmp, i32 0, i32 0
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%y = getelementptr inbounds [4 x i32], [4 x i32]* %tmp, i32 0, i32 1
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%z = getelementptr inbounds [4 x i32], [4 x i32]* %tmp, i32 0, i32 2
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%w = getelementptr inbounds [4 x i32], [4 x i32]* %tmp, i32 0, i32 3
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%bc = bitcast i32* %x to float*
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store float 1.0, float* %bc
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store i32 1, i32* %y
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store i32 2, i32* %z
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store i32 3, i32* %w
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%tmp1 = getelementptr inbounds [4 x i32], [4 x i32]* %tmp, i32 0, i32 %index
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%tmp2 = load i32, i32* %tmp1
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%tmp = alloca [4 x i32], addrspace(5)
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%x = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 0
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%y = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%z = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
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%w = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
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%bc = bitcast i32 addrspace(5)* %x to float addrspace(5)*
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store float 1.0, float addrspace(5)* %bc
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store i32 1, i32 addrspace(5)* %y
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store i32 2, i32 addrspace(5)* %z
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store i32 3, i32 addrspace(5)* %w
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%tmp1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %index
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%tmp2 = load i32, i32 addrspace(5)* %tmp1
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store i32 %tmp2, i32 addrspace(1)* %out
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ret void
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}
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@ -123,18 +124,18 @@ entry:
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; OPT: load float
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define amdgpu_kernel void @vector_read_bitcast_alloca(float addrspace(1)* %out, i32 %index) {
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entry:
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%tmp = alloca [4 x i32]
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%tmp.bc = bitcast [4 x i32]* %tmp to [4 x float]*
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%x = getelementptr inbounds [4 x float], [4 x float]* %tmp.bc, i32 0, i32 0
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%y = getelementptr inbounds [4 x float], [4 x float]* %tmp.bc, i32 0, i32 1
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%z = getelementptr inbounds [4 x float], [4 x float]* %tmp.bc, i32 0, i32 2
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%w = getelementptr inbounds [4 x float], [4 x float]* %tmp.bc, i32 0, i32 3
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store float 0.0, float* %x
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store float 1.0, float* %y
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store float 2.0, float* %z
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store float 4.0, float* %w
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%tmp1 = getelementptr inbounds [4 x float], [4 x float]* %tmp.bc, i32 0, i32 %index
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%tmp2 = load float, float* %tmp1
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%tmp = alloca [4 x i32], addrspace(5)
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%tmp.bc = bitcast [4 x i32] addrspace(5)* %tmp to [4 x float] addrspace(5)*
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%x = getelementptr inbounds [4 x float], [4 x float] addrspace(5)* %tmp.bc, i32 0, i32 0
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%y = getelementptr inbounds [4 x float], [4 x float] addrspace(5)* %tmp.bc, i32 0, i32 1
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%z = getelementptr inbounds [4 x float], [4 x float] addrspace(5)* %tmp.bc, i32 0, i32 2
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%w = getelementptr inbounds [4 x float], [4 x float] addrspace(5)* %tmp.bc, i32 0, i32 3
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store float 0.0, float addrspace(5)* %x
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store float 1.0, float addrspace(5)* %y
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store float 2.0, float addrspace(5)* %z
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store float 4.0, float addrspace(5)* %w
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%tmp1 = getelementptr inbounds [4 x float], [4 x float] addrspace(5)* %tmp.bc, i32 0, i32 %index
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%tmp2 = load float, float addrspace(5)* %tmp1
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store float %tmp2, float addrspace(1)* %out
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ret void
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}
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@ -146,17 +147,17 @@ entry:
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; OPT: store i32 %0, i32 addrspace(1)* %out, align 4
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define amdgpu_kernel void @vector_read_with_local_arg(i32 addrspace(3)* %stopper, i32 addrspace(1)* %out, i32 %index) {
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entry:
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%tmp = alloca [4 x i32]
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%x = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0
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%y = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 3
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store i32 0, i32* %x
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store i32 1, i32* %y
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store i32 2, i32* %z
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store i32 3, i32* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 %index
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%tmp2 = load i32, i32* %tmp1
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%tmp = alloca [4 x i32], addrspace(5)
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%x = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 0
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%y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
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store i32 0, i32 addrspace(5)* %x
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store i32 1, i32 addrspace(5)* %y
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store i32 2, i32 addrspace(5)* %z
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store i32 3, i32 addrspace(5)* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %index
|
||||
%tmp2 = load i32, i32 addrspace(5)* %tmp1
|
||||
store i32 %tmp2, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue