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[X86] Remove some intel syntax aliases on (v)cvtpd2(u)dq, (v)cvtpd2ps, (v)cvt(u)qq2ps. Add 'x' and'y' suffix aliases to masked version of the same in att syntax. 

The 128/256 bit version of these instructions require an 'x' or 'y' suffix to
disambiguate the memory form in att syntax.

We were allowing the same suffix in intel syntax, but it appears gas does not
do that.

gas does allow the 'x' and 'y' suffix on register and broadcast forms even
though its not needed. We were allowing it on unmasked register form, but not on
masked versions or on masked or unmasked broadcast form.

While there fix some test coverage holes so they can be extended with the 'x'
and 'y' suffix tests.

llvm-svn: 359418
This commit is contained in:
Craig Topper 2019-04-29 06:13:41 +00:00
parent 2d5e7de526
commit 9202d5f8f1
6 changed files with 3085 additions and 202 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

178
llvm/lib/Target/X86/X86InstrAVX512.td
View File

@ -7728,13 +7728,44 @@ multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr, X86SchedWriteWidths sc
}
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>;
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z128rm") VR128X:$dst, f128mem:$src), 0, "intel">;
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
(!cast<Instruction>(NAME # "Z128rrk") VR128X:$dst,
VK2WM:$mask, VR128X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}} {z}|"
"$dst {${mask}} {z}, $src}",
(!cast<Instruction>(NAME # "Z128rrkz") VR128X:$dst,
VK2WM:$mask, VR128X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst|$dst, ${src}{1to2}}",
(!cast<Instruction>(NAME # "Z128rmb") VR128X:$dst, f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}}|"
"$dst {${mask}}, ${src}{1to2}}",
(!cast<Instruction>(NAME # "Z128rmbk") VR128X:$dst,
VK2WM:$mask, f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}} {z}|"
"$dst {${mask}} {z}, ${src}{1to2}}",
(!cast<Instruction>(NAME # "Z128rmbkz") VR128X:$dst,
VK2WM:$mask, f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>;
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z256rm") VR128X:$dst, f256mem:$src), 0, "intel">;
(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
(!cast<Instruction>(NAME # "Z256rrk") VR128X:$dst,
VK4WM:$mask, VR256X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}} {z}|"
"$dst {${mask}} {z}, $src}",
(!cast<Instruction>(NAME # "Z256rrkz") VR128X:$dst,
VK4WM:$mask, VR256X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst|$dst, ${src}{1to4}}",
(!cast<Instruction>(NAME # "Z256rmb") VR128X:$dst, f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}}|"
"$dst {${mask}}, ${src}{1to4}}",
(!cast<Instruction>(NAME # "Z256rmbk") VR128X:$dst,
VK4WM:$mask, f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}} {z}|"
"$dst {${mask}} {z}, ${src}{1to4}}",
(!cast<Instruction>(NAME # "Z256rmbkz") VR128X:$dst,
VK4WM:$mask, f64mem:$src), 0, "att">;
}
defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps", SchedWriteCvtPD2PS>,
@ -7930,13 +7961,46 @@ multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
}
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>;
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z128rm") VR128X:$dst, i128mem:$src), 0, "intel">;
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst,
VR128X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
(!cast<Instruction>(NAME # "Z128rrk") VR128X:$dst,
VK2WM:$mask, VR128X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
(!cast<Instruction>(NAME # "Z128rrkz") VR128X:$dst,
VK2WM:$mask, VR128X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst|$dst, ${src}{1to2}}",
(!cast<Instruction>(NAME # "Z128rmb") VR128X:$dst,
f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}}|"
"$dst {${mask}}, ${src}{1to2}}",
(!cast<Instruction>(NAME # "Z128rmbk") VR128X:$dst,
VK2WM:$mask, f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}} {z}|"
"$dst {${mask}} {z}, ${src}{1to2}}",
(!cast<Instruction>(NAME # "Z128rmbkz") VR128X:$dst,
VK2WM:$mask, f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>;
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z256rm") VR128X:$dst, i256mem:$src), 0, "intel">;
(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst,
VR256X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
(!cast<Instruction>(NAME # "Z256rrk") VR128X:$dst,
VK4WM:$mask, VR256X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
(!cast<Instruction>(NAME # "Z256rrkz") VR128X:$dst,
VK4WM:$mask, VR256X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst|$dst, ${src}{1to4}}",
(!cast<Instruction>(NAME # "Z256rmb") VR128X:$dst,
f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}}|"
"$dst {${mask}}, ${src}{1to4}}",
(!cast<Instruction>(NAME # "Z256rmbk") VR128X:$dst,
VK4WM:$mask, f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}} {z}|"
"$dst {${mask}} {z}, ${src}{1to4}}",
(!cast<Instruction>(NAME # "Z256rmbkz") VR128X:$dst,
VK4WM:$mask, f64mem:$src), 0, "att">;
}
// Convert Double to Signed/Unsigned Doubleword
@ -7961,13 +8025,44 @@ multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
}
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>;
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z128rm") VR128X:$dst, f128mem:$src), 0, "intel">;
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
(!cast<Instruction>(NAME # "Z128rrk") VR128X:$dst,
VK2WM:$mask, VR128X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
(!cast<Instruction>(NAME # "Z128rrkz") VR128X:$dst,
VK2WM:$mask, VR128X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst|$dst, ${src}{1to2}}",
(!cast<Instruction>(NAME # "Z128rmb") VR128X:$dst,
f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}}|"
"$dst {${mask}}, ${src}{1to2}}",
(!cast<Instruction>(NAME # "Z128rmbk") VR128X:$dst,
VK2WM:$mask, f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}} {z}|"
"$dst {${mask}} {z}, ${src}{1to2}}",
(!cast<Instruction>(NAME # "Z128rmbkz") VR128X:$dst,
VK2WM:$mask, f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>;
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z256rm") VR128X:$dst, f256mem:$src), 0, "intel">;
(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
(!cast<Instruction>(NAME # "Z256rrk") VR128X:$dst,
VK4WM:$mask, VR256X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
(!cast<Instruction>(NAME # "Z256rrkz") VR128X:$dst,
VK4WM:$mask, VR256X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst|$dst, ${src}{1to4}}",
(!cast<Instruction>(NAME # "Z256rmb") VR128X:$dst,
f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}}|"
"$dst {${mask}}, ${src}{1to4}}",
(!cast<Instruction>(NAME # "Z256rmbk") VR128X:$dst,
VK4WM:$mask, f64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}} {z}|"
"$dst {${mask}} {z}, ${src}{1to4}}",
(!cast<Instruction>(NAME # "Z256rmbkz") VR128X:$dst,
VK4WM:$mask, f64mem:$src), 0, "att">;
}
// Convert Double to Signed/Unsigned Quardword
@ -8081,13 +8176,48 @@ multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
}
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>;
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z128rm") VR128X:$dst, i128mem:$src), 0, "intel">;
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst,
VR128X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
(!cast<Instruction>(NAME # "Z128rrk") VR128X:$dst,
VK2WM:$mask, VR128X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
(!cast<Instruction>(NAME # "Z128rrkz") VR128X:$dst,
VK2WM:$mask, VR128X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst|$dst, ${src}{1to2}}",
(!cast<Instruction>(NAME # "Z128rmb") VR128X:$dst,
i64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}}|"
"$dst {${mask}}, ${src}{1to2}}",
(!cast<Instruction>(NAME # "Z128rmbk") VR128X:$dst,
VK2WM:$mask, i64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}} {z}|"
"$dst {${mask}} {z}, ${src}{1to2}}",
(!cast<Instruction>(NAME # "Z128rmbkz") VR128X:$dst,
VK2WM:$mask, i64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>;
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "Z256rm") VR128X:$dst, i256mem:$src), 0, "intel">;
(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst,
VR256X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}}|"
"$dst {${mask}}, $src}",
(!cast<Instruction>(NAME # "Z256rrk") VR128X:$dst,
VK4WM:$mask, VR256X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}} {z}|"
"$dst {${mask}} {z}, $src}",
(!cast<Instruction>(NAME # "Z256rrkz") VR128X:$dst,
VK4WM:$mask, VR256X:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst|$dst, ${src}{1to4}}",
(!cast<Instruction>(NAME # "Z256rmb") VR128X:$dst,
i64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}}|"
"$dst {${mask}}, ${src}{1to4}}",
(!cast<Instruction>(NAME # "Z256rmbk") VR128X:$dst,
VK4WM:$mask, i64mem:$src), 0, "att">;
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}} {z}|"
"$dst {${mask}} {z}, ${src}{1to4}}",
(!cast<Instruction>(NAME # "Z256rmbkz") VR128X:$dst,
VK4WM:$mask, i64mem:$src), 0, "att">;
}
defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86VSintToFP,

24
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -1475,13 +1475,9 @@ def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
}
def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
(VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
(VCVTPD2DQrm VR128:$dst, f128mem:$src), 0, "intel">;
(VCVTPD2DQrr VR128:$dst, VR128:$src), 0, "att">;
def : InstAlias<"vcvtpd2dqy\t{$src, $dst|$dst, $src}",
(VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
def : InstAlias<"vcvtpd2dqy\t{$src, $dst|$dst, $src}",
(VCVTPD2DQYrm VR128:$dst, f256mem:$src), 0, "intel">;
(VCVTPD2DQYrr VR128:$dst, VR256:$src), 0, "att">;
def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"cvtpd2dq\t{$src, $dst|$dst, $src}",
@ -1579,13 +1575,9 @@ def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
} // Predicates = [HasAVX, NoVLX]
def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
(VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
(VCVTTPD2DQrm VR128:$dst, f128mem:$src), 0, "intel">;
(VCVTTPD2DQrr VR128:$dst, VR128:$src), 0, "att">;
def : InstAlias<"vcvttpd2dqy\t{$src, $dst|$dst, $src}",
(VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
def : InstAlias<"vcvttpd2dqy\t{$src, $dst|$dst, $src}",
(VCVTTPD2DQYrm VR128:$dst, f256mem:$src), 0, "intel">;
(VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0, "att">;
let Predicates = [HasAVX, NoVLX] in {
def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
@ -1717,13 +1709,9 @@ def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
} // Predicates = [HasAVX, NoVLX]
def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
(VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
(VCVTPD2PSrm VR128:$dst, f128mem:$src), 0, "intel">;
(VCVTPD2PSrr VR128:$dst, VR128:$src), 0, "att">;
def : InstAlias<"vcvtpd2psy\t{$src, $dst|$dst, $src}",
(VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
def : InstAlias<"vcvtpd2psy\t{$src, $dst|$dst, $src}",
(VCVTPD2PSYrm VR128:$dst, f256mem:$src), 0, "intel">;
(VCVTPD2PSYrr VR128:$dst, VR256:$src), 0, "att">;
def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"cvtpd2ps\t{$src, $dst|$dst, $src}",

48
llvm/test/MC/X86/intel-syntax-x86-64-avx.s
View File

@ -68,98 +68,50 @@
// CHECK: encoding: [0xc4,0xc1,0x79,0x5a,0xc7]
vcvtpd2ps xmm0, xmm15
// CHECK: vcvtpd2ps xmm0, xmm15
// CHECK: encoding: [0xc4,0xc1,0x79,0x5a,0xc7]
vcvtpd2psx xmm0, xmm15
// CHECK: vcvtpd2ps xmm0, xmmword ptr [rax]
// CHECK: encoding: [0xc5,0xf9,0x5a,0x00]
vcvtpd2ps xmm0, xmmword ptr [rax]
// CHECK: vcvtpd2ps xmm0, xmmword ptr [rax]
// CHECK: encoding: [0xc5,0xf9,0x5a,0x00]
vcvtpd2psx xmm0, xmmword ptr [rax]
// CHECK: vcvtpd2ps xmm0, ymm15
// CHECK: encoding: [0xc4,0xc1,0x7d,0x5a,0xc7]
vcvtpd2ps xmm0, ymm15
// CHECK: vcvtpd2ps xmm0, ymm15
// CHECK: encoding: [0xc4,0xc1,0x7d,0x5a,0xc7]
vcvtpd2psy xmm0, ymm15
// CHECK: vcvtpd2ps xmm0, ymmword ptr [rax]
// CHECK: encoding: [0xc5,0xfd,0x5a,0x00]
vcvtpd2ps xmm0, ymmword ptr [rax]
// CHECK: vcvtpd2ps xmm0, ymmword ptr [rax]
// CHECK: encoding: [0xc5,0xfd,0x5a,0x00]
vcvtpd2psy xmm0, ymmword ptr [rax]
// CHECK: vcvtpd2dq xmm0, xmm15
// CHECK: encoding: [0xc4,0xc1,0x7b,0xe6,0xc7]
vcvtpd2dq xmm0, xmm15
// CHECK: vcvtpd2dq xmm0, xmm15
// CHECK: encoding: [0xc4,0xc1,0x7b,0xe6,0xc7]
vcvtpd2dqx xmm0, xmm15
// CHECK: vcvtpd2dq xmm0, xmmword ptr [rax]
// CHECK: encoding: [0xc5,0xfb,0xe6,0x00]
vcvtpd2dq xmm0, xmmword ptr [rax]
// CHECK: vcvtpd2dq xmm0, xmmword ptr [rax]
// CHECK: encoding: [0xc5,0xfb,0xe6,0x00]
vcvtpd2dqx xmm0, xmmword ptr [rax]
// CHECK: vcvtpd2dq xmm0, ymm15
// CHECK: encoding: [0xc4,0xc1,0x7f,0xe6,0xc7]
vcvtpd2dq xmm0, ymm15
// CHECK: vcvtpd2dq xmm0, ymm15
// CHECK: encoding: [0xc4,0xc1,0x7f,0xe6,0xc7]
vcvtpd2dqy xmm0, ymm15
// CHECK: vcvtpd2dq xmm0, ymmword ptr [rax]
// CHECK: encoding: [0xc5,0xff,0xe6,0x00]
vcvtpd2dq xmm0, ymmword ptr [rax]
// CHECK: vcvtpd2dq xmm0, ymmword ptr [rax]
// CHECK: encoding: [0xc5,0xff,0xe6,0x00]
vcvtpd2dqy xmm0, ymmword ptr [rax]
// CHECK: vcvttpd2dq xmm0, xmm15
// CHECK: encoding: [0xc4,0xc1,0x79,0xe6,0xc7]
vcvttpd2dq xmm0, xmm15
// CHECK: vcvttpd2dq xmm0, xmm15
// CHECK: encoding: [0xc4,0xc1,0x79,0xe6,0xc7]
vcvttpd2dqx xmm0, xmm15
// CHECK: vcvttpd2dq xmm0, xmmword ptr [rax]
// CHECK: encoding: [0xc5,0xf9,0xe6,0x00]
vcvttpd2dq xmm0, xmmword ptr [rax]
// CHECK: vcvttpd2dq xmm0, xmmword ptr [rax]
// CHECK: encoding: [0xc5,0xf9,0xe6,0x00]
vcvttpd2dqx xmm0, xmmword ptr [rax]
// CHECK: vcvttpd2dq xmm0, ymm15
// CHECK: encoding: [0xc4,0xc1,0x7d,0xe6,0xc7]
vcvttpd2dq xmm0, ymm15
// CHECK: vcvttpd2dq xmm0, ymm15
// CHECK: encoding: [0xc4,0xc1,0x7d,0xe6,0xc7]
vcvttpd2dqy xmm0, ymm15
// CHECK: vcvttpd2dq xmm0, ymmword ptr [rax]
// CHECK: encoding: [0xc5,0xfd,0xe6,0x00]
vcvttpd2dq xmm0, ymmword ptr [rax]
// CHECK: vcvttpd2dq xmm0, ymmword ptr [rax]
// CHECK: encoding: [0xc5,0xfd,0xe6,0x00]
vcvttpd2dqy xmm0, ymmword ptr [rax]
// CHECK: vpmaddwd xmm1, xmm2, xmm3
// CHECK: encoding: [0xc5,0xe9,0xf5,0xcb]
vpmaddwd xmm1, xmm2, xmm3

112
llvm/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s
View File

@ -1124,226 +1124,114 @@
// CHECK: encoding: [0x62,0xb1,0xfd,0x08,0x5a,0xc7]
vcvtpd2ps xmm0, xmm23
// CHECK: vcvtpd2ps xmm0, xmm23
// CHECK: encoding: [0x62,0xb1,0xfd,0x08,0x5a,0xc7]
vcvtpd2psx xmm0, xmm23
// CHECK: vcvtpd2ps xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0x5a,0x00]
vcvtpd2ps xmm16, xmmword ptr [rax]
// CHECK: vcvtpd2ps xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0x5a,0x00]
vcvtpd2psx xmm16, xmmword ptr [rax]
// CHECK: vcvtpd2ps xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xfd,0x28,0x5a,0xc7]
vcvtpd2ps xmm0, ymm23
// CHECK: vcvtpd2ps xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xfd,0x28,0x5a,0xc7]
vcvtpd2psy xmm0, ymm23
// CHECK: vcvtpd2ps xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x5a,0x00]
vcvtpd2ps xmm16, ymmword ptr [rax]
// CHECK: vcvtpd2ps xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x5a,0x00]
vcvtpd2psy xmm16, ymmword ptr [rax]
// CHECK: vcvtpd2dq xmm0, xmm23
// CHECK: encoding: [0x62,0xb1,0xff,0x08,0xe6,0xc7]
vcvtpd2dq xmm0, xmm23
// CHECK: vcvtpd2dq xmm0, xmm23
// CHECK: encoding: [0x62,0xb1,0xff,0x08,0xe6,0xc7]
vcvtpd2dqx xmm0, xmm23
// CHECK: vcvtpd2dq xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0xe6,0x00]
vcvtpd2dq xmm16, xmmword ptr [rax]
// CHECK: vcvtpd2dq xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0xe6,0x00]
vcvtpd2dqx xmm16, xmmword ptr [rax]
// CHECK: vcvtpd2dq xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xff,0x28,0xe6,0xc7]
vcvtpd2dq xmm0, ymm23
// CHECK: vcvtpd2dq xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xff,0x28,0xe6,0xc7]
vcvtpd2dqy xmm0, ymm23
// CHECK: vcvtpd2dq xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xff,0x28,0xe6,0x00]
vcvtpd2dq xmm16, ymmword ptr [rax]
// CHECK: vcvtpd2dq xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xff,0x28,0xe6,0x00]
vcvtpd2dqy xmm16, ymmword ptr [rax]
// CHECK: vcvtpd2udq xmm0, xmm23
// CHECK: encoding: [0x62,0xb1,0xfc,0x08,0x79,0xc7]
vcvtpd2udq xmm0, xmm23
// CHECK: vcvtpd2udq xmm0, xmm23
// CHECK: encoding: [0x62,0xb1,0xfc,0x08,0x79,0xc7]
vcvtpd2udqx xmm0, xmm23
// CHECK: vcvtpd2udq xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfc,0x08,0x79,0x00]
vcvtpd2udq xmm16, xmmword ptr [rax]
// CHECK: vcvtpd2udq xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfc,0x08,0x79,0x00]
vcvtpd2udqx xmm16, xmmword ptr [rax]
// CHECK: vcvtpd2udq xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xfc,0x28,0x79,0xc7]
vcvtpd2udq xmm0, ymm23
// CHECK: vcvtpd2udq xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xfc,0x28,0x79,0xc7]
vcvtpd2udqy xmm0, ymm23
// CHECK: vcvtpd2udq xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfc,0x28,0x79,0x00]
vcvtpd2udq xmm16, ymmword ptr [rax]
// CHECK: vcvtpd2udq xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfc,0x28,0x79,0x00]
vcvtpd2udqy xmm16, ymmword ptr [rax]
// CHECK: vcvttpd2dq xmm0, xmm23
// CHECK: encoding: [0x62,0xb1,0xfd,0x08,0xe6,0xc7]
vcvttpd2dq xmm0, xmm23
// CHECK: vcvttpd2dq xmm0, xmm23
// CHECK: encoding: [0x62,0xb1,0xfd,0x08,0xe6,0xc7]
vcvttpd2dqx xmm0, xmm23
// CHECK: vcvttpd2dq xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0xe6,0x00]
vcvttpd2dq xmm16, xmmword ptr [rax]
// CHECK: vcvttpd2dq xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0xe6,0x00]
vcvttpd2dqx xmm16, xmmword ptr [rax]
// CHECK: vcvttpd2dq xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xfd,0x28,0xe6,0xc7]
vcvttpd2dq xmm0, ymm23
// CHECK: vcvttpd2dq xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xfd,0x28,0xe6,0xc7]
vcvttpd2dqy xmm0, ymm23
// CHECK: vcvttpd2dq xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0xe6,0x00]
vcvttpd2dq xmm16, ymmword ptr [rax]
// CHECK: vcvttpd2dq xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0xe6,0x00]
vcvttpd2dqy xmm16, ymmword ptr [rax]
// CHECK: vcvttpd2udq xmm0, xmm23
// CHECK: encoding: [0x62,0xb1,0xfc,0x08,0x78,0xc7]
vcvttpd2udq xmm0, xmm23
// CHECK: vcvttpd2udq xmm0, xmm23
// CHECK: encoding: [0x62,0xb1,0xfc,0x08,0x78,0xc7]
vcvttpd2udqx xmm0, xmm23
// CHECK: vcvttpd2udq xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfc,0x08,0x78,0x00]
vcvttpd2udq xmm16, xmmword ptr [rax]
// CHECK: vcvttpd2udq xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfc,0x08,0x78,0x00]
vcvttpd2udqx xmm16, xmmword ptr [rax]
// CHECK: vcvttpd2udq xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xfc,0x28,0x78,0xc7]
vcvttpd2udq xmm0, ymm23
// CHECK: vcvttpd2udq xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xfc,0x28,0x78,0xc7]
vcvttpd2udqy xmm0, ymm23
// CHECK: vcvttpd2udq xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfc,0x28,0x78,0x00]
vcvttpd2udq xmm16, ymmword ptr [rax]
// CHECK: vcvttpd2udq xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfc,0x28,0x78,0x00]
vcvttpd2udqy xmm16, ymmword ptr [rax]
// CHECK: vcvtqq2ps xmm0, xmm23
// CHECK: encoding: [0x62,0xb1,0xfc,0x08,0x5b,0xc7]
vcvtqq2ps xmm0, xmm23
// CHECK: vcvtqq2ps xmm0, xmm23
// CHECK: encoding: [0x62,0xb1,0xfc,0x08,0x5b,0xc7]
vcvtqq2psx xmm0, xmm23
// CHECK: vcvtqq2ps xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfc,0x08,0x5b,0x00]
vcvtqq2ps xmm16, xmmword ptr [rax]
// CHECK: vcvtqq2ps xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfc,0x08,0x5b,0x00]
vcvtqq2psx xmm16, xmmword ptr [rax]
// CHECK: vcvtqq2ps xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xfc,0x28,0x5b,0xc7]
vcvtqq2ps xmm0, ymm23
// CHECK: vcvtqq2ps xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xfc,0x28,0x5b,0xc7]
vcvtqq2psy xmm0, ymm23
// CHECK: vcvtqq2ps xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfc,0x28,0x5b,0x00]
vcvtqq2ps xmm16, ymmword ptr [rax]
// CHECK: vcvtqq2ps xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xfc,0x28,0x5b,0x00]
vcvtqq2psy xmm16, ymmword ptr [rax]
// CHECK: vcvtuqq2ps xmm0, xmm23
// CHECK: encoding: [0x62,0xb1,0xff,0x08,0x7a,0xc7]
vcvtuqq2ps xmm0, xmm23
// CHECK: vcvtuqq2ps xmm0, xmm23
// CHECK: encoding: [0x62,0xb1,0xff,0x08,0x7a,0xc7]
vcvtuqq2psx xmm0, xmm23
// CHECK: vcvtuqq2ps xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7a,0x00]
vcvtuqq2ps xmm16, xmmword ptr [rax]
// CHECK: vcvtuqq2ps xmm16, xmmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7a,0x00]
vcvtuqq2psx xmm16, xmmword ptr [rax]
// CHECK: vcvtuqq2ps xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xff,0x28,0x7a,0xc7]
vcvtuqq2ps xmm0, ymm23
// CHECK: vcvtuqq2ps xmm0, ymm23
// CHECK: encoding: [0x62,0xb1,0xff,0x28,0x7a,0xc7]
vcvtuqq2psy xmm0, ymm23
// CHECK: vcvtuqq2ps xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xff,0x28,0x7a,0x00]
vcvtuqq2ps xmm16, ymmword ptr [rax]
// CHECK: vcvtuqq2ps xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xff,0x28,0x7a,0x00]
vcvtuqq2psy xmm16, ymmword ptr [rax]
// CHECK: vcvtps2pd xmm1 {k2} {z}, qword ptr [rcx + 128]
// CHECK: encoding: [0x62,0xf1,0x7c,0x8a,0x5a,0x49,0x10]
vcvtps2pd xmm1 {k2} {z}, qword ptr [rcx+0x80]

1268
llvm/test/MC/X86/x86-64-avx512dq_vl.s
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1657
llvm/test/MC/X86/x86-64-avx512f_vl.s
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File diff suppressed because it is too large Load Diff