From 9201fb9ce7a4138831a27502a396e6b89d68be88 Mon Sep 17 00:00:00 2001 From: Michael Kuperstein Date: Wed, 26 Feb 2014 12:06:36 +0000 Subject: [PATCH] Ensure bitcode encoding of instructions and their operands stays stable. This includes instructions with aggregate operands (insert/extract), instructions with vector operands (insert/extract/shuffle), binary arithmetic and bitwise instructions, conversion instructions and terminators. Work was done by lama.saba@intel.com. llvm-svn: 202262 --- .../test/Bitcode/aggregateInstructions.3.2.ll | 33 ++++ .../Bitcode/aggregateInstructions.3.2.ll.bc | Bin 0 -> 452 bytes .../Bitcode/binaryFloatInstructions.3.2.ll | 120 ++++++++++++ .../Bitcode/binaryFloatInstructions.3.2.ll.bc | Bin 0 -> 992 bytes .../test/Bitcode/binaryIntInstructions.3.2.ll | 177 ++++++++++++++++++ .../Bitcode/binaryIntInstructions.3.2.ll.bc | Bin 0 -> 1324 bytes llvm/test/Bitcode/bitwiseInstructions.3.2.ll | 68 +++++++ .../Bitcode/bitwiseInstructions.3.2.ll.bc | Bin 0 -> 612 bytes .../Bitcode/conversionInstructions.3.2.ll | 104 ++++++++++ .../Bitcode/conversionInstructions.3.2.ll.bc | Bin 0 -> 996 bytes .../Bitcode/terminatorInstructions.3.2.ll | 47 +++++ .../Bitcode/terminatorInstructions.3.2.ll.bc | Bin 0 -> 568 bytes llvm/test/Bitcode/vectorInstructions.3.2.ll | 34 ++++ .../test/Bitcode/vectorInstructions.3.2.ll.bc | Bin 0 -> 500 bytes 14 files changed, 583 insertions(+) create mode 100644 llvm/test/Bitcode/aggregateInstructions.3.2.ll create mode 100644 llvm/test/Bitcode/aggregateInstructions.3.2.ll.bc create mode 100644 llvm/test/Bitcode/binaryFloatInstructions.3.2.ll create mode 100644 llvm/test/Bitcode/binaryFloatInstructions.3.2.ll.bc create mode 100644 llvm/test/Bitcode/binaryIntInstructions.3.2.ll create mode 100644 llvm/test/Bitcode/binaryIntInstructions.3.2.ll.bc create mode 100644 llvm/test/Bitcode/bitwiseInstructions.3.2.ll create mode 100644 llvm/test/Bitcode/bitwiseInstructions.3.2.ll.bc create mode 100644 llvm/test/Bitcode/conversionInstructions.3.2.ll create mode 100644 llvm/test/Bitcode/conversionInstructions.3.2.ll.bc create mode 100644 llvm/test/Bitcode/terminatorInstructions.3.2.ll create mode 100644 llvm/test/Bitcode/terminatorInstructions.3.2.ll.bc create mode 100644 llvm/test/Bitcode/vectorInstructions.3.2.ll create mode 100644 llvm/test/Bitcode/vectorInstructions.3.2.ll.bc diff --git a/llvm/test/Bitcode/aggregateInstructions.3.2.ll b/llvm/test/Bitcode/aggregateInstructions.3.2.ll new file mode 100644 index 000000000000..9352390b131b --- /dev/null +++ b/llvm/test/Bitcode/aggregateInstructions.3.2.ll @@ -0,0 +1,33 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; aggregateOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not misread instructions with aggregate operands +; in older bitcode files. + +define void @extractvalue([4 x i8] %x1, [4 x [4 x i8]] %x2, {{i32, float}} %x3){ +entry: +; CHECK: %res1 = extractvalue [4 x i8] %x1, 0 + %res1 = extractvalue [4 x i8] %x1, 0 + +; CHECK-NEXT: %res2 = extractvalue [4 x [4 x i8]] %x2, 1 + %res2 = extractvalue [4 x [4 x i8 ]] %x2, 1 + +; CHECK-NEXT: %res3 = extractvalue [4 x [4 x i8]] %x2, 0, 1 + %res3 = extractvalue [4 x [4 x i8 ]] %x2, 0, 1 + +; CHECK-NEXT: %res4 = extractvalue { { i32, float } } %x3, 0, 1 + %res4 = extractvalue {{i32, float}} %x3, 0, 1 + + ret void +} + +define void @insertvalue([4 x [4 x i8 ]] %x1){ +entry: +; CHECK: %res1 = insertvalue [4 x [4 x i8]] %x1, i8 0, 0, 0 + %res1 = insertvalue [4 x [4 x i8 ]] %x1, i8 0, 0, 0 + +; CHECK-NEXT: %res2 = insertvalue [4 x [4 x i8]] undef, i8 0, 0, 0 + %res2 = insertvalue [4 x [4 x i8 ]] undef, i8 0, 0, 0 + + ret void +} \ No newline at end of file diff --git a/llvm/test/Bitcode/aggregateInstructions.3.2.ll.bc b/llvm/test/Bitcode/aggregateInstructions.3.2.ll.bc new file mode 100644 index 0000000000000000000000000000000000000000..053f85fda645b366ad102f2d4c119dc9569651a7 GIT binary patch literal 452 zcmZ>AK5$Qwhk+rFfq{X$Nr8b0NDBcmd!zD1#}h1`Yyw7>lNeigR9QJB}F$U~Vl5k}h%XN#7@Jx&eml@;v8GYWa0 zG4Q_?;QP|RXUyXycj%z(xrH)m2CQIZ&C+L>ZBIDc_AuK5%_vl0U;vpXwn3rS#U+?k zM9&`6j5d{ lF$U6`1)D*{A)sgZK)wdK3t_e>(4?zrK$B7+CIKaZ002vmVrc*X literal 0 HcmV?d00001 diff --git a/llvm/test/Bitcode/binaryFloatInstructions.3.2.ll b/llvm/test/Bitcode/binaryFloatInstructions.3.2.ll new file mode 100644 index 000000000000..f94d82d23c9f --- /dev/null +++ b/llvm/test/Bitcode/binaryFloatInstructions.3.2.ll @@ -0,0 +1,120 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; BinaryFloatOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not misread binary float instructions from +; older bitcode files. + +define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){ +entry: +; CHECK: %res1 = fadd float %x1, %x1 + %res1 = fadd float %x1, %x1 + +; CHECK-NEXT: %res2 = fadd double %x2, %x2 + %res2 = fadd double %x2, %x2 + +; CHECK-NEXT: %res3 = fadd half %x3, %x3 + %res3 = fadd half %x3, %x3 + +; CHECK-NEXT: %res4 = fadd fp128 %x4, %x4 + %res4 = fadd fp128 %x4, %x4 + +; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5 + %res5 = fadd x86_fp80 %x5, %x5 + +; CHECK-NEXT: %res6 = fadd ppc_fp128 %x6, %x6 + %res6 = fadd ppc_fp128 %x6, %x6 + + ret void +} + +define void @faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x float> %x5){ +entry: +; CHECK: %res1 = fadd <2 x float> %x1, %x1 + %res1 = fadd <2 x float> %x1, %x1 + +; CHECK-NEXT: %res2 = fadd <3 x float> %x2, %x2 + %res2 = fadd <3 x float> %x2, %x2 + +; CHECK-NEXT: %res3 = fadd <4 x float> %x3, %x3 + %res3 = fadd <4 x float> %x3, %x3 + +; CHECK-NEXT: %res4 = fadd <8 x float> %x4, %x4 + %res4 = fadd <8 x float> %x4, %x4 + +; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5 + %res5 = fadd <16 x float> %x5, %x5 + + ret void +} + +define void @faddDoubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, <16 x double> %x5){ +entry: +; CHECK: %res1 = fadd <2 x double> %x1, %x1 + %res1 = fadd <2 x double> %x1, %x1 + +; CHECK-NEXT: %res2 = fadd <3 x double> %x2, %x2 + %res2 = fadd <3 x double> %x2, %x2 + +; CHECK-NEXT: %res3 = fadd <4 x double> %x3, %x3 + %res3 = fadd <4 x double> %x3, %x3 + +; CHECK-NEXT: %res4 = fadd <8 x double> %x4, %x4 + %res4 = fadd <8 x double> %x4, %x4 + +; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5 + %res5 = fadd <16 x double> %x5, %x5 + + ret void +} + +define void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half> %x5){ +entry: +; CHECK: %res1 = fadd <2 x half> %x1, %x1 + %res1 = fadd <2 x half> %x1, %x1 + +; CHECK-NEXT: %res2 = fadd <3 x half> %x2, %x2 + %res2 = fadd <3 x half> %x2, %x2 + +; CHECK-NEXT: %res3 = fadd <4 x half> %x3, %x3 + %res3 = fadd <4 x half> %x3, %x3 + +; CHECK-NEXT: %res4 = fadd <8 x half> %x4, %x4 + %res4 = fadd <8 x half> %x4, %x4 + +; CHECK-NEXT: %res5 = fadd <16 x half> %x5, %x5 + %res5 = fadd <16 x half> %x5, %x5 + + ret void +} + +define void @fsub(float %x1){ +entry: +; CHECK: %res1 = fsub float %x1, %x1 + %res1 = fsub float %x1, %x1 + + ret void +} + +define void @fmul(float %x1){ +entry: +; CHECK: %res1 = fmul float %x1, %x1 + %res1 = fmul float %x1, %x1 + + ret void +} + +define void @fdiv(float %x1){ +entry: +; CHECK: %res1 = fdiv float %x1, %x1 + %res1 = fdiv float %x1, %x1 + + ret void +} + +define void @frem(float %x1){ +entry: +; CHECK: %res1 = frem float %x1, %x1 + %res1 = frem float %x1, %x1 + + ret void +} diff --git a/llvm/test/Bitcode/binaryFloatInstructions.3.2.ll.bc b/llvm/test/Bitcode/binaryFloatInstructions.3.2.ll.bc new file mode 100644 index 0000000000000000000000000000000000000000..8dbb4e456a044584f292a4067d90cbf88dcddd5a GIT binary patch literal 992 zcmZ>AK5$Qwhk@ZM0|NthlL7-1kQM@B_D1E2jwe_=*#wL%Co#70sIqcM%CU4OHAuKJ zIZfhrIwD{sV!FMEaIpQPGaFF8w&jEo08V4*6m>jTiuxxOU=s2_> zS;CQ{O|UINq7g_S9zmb;#rik21$0gF^~D$^wTBn3Q;w9h?jqG$yHatx9A` zlyH-1OJqrsaB~1s85(Q_i8HqehO;Or@H04zumD{G1QLsEAdCY7M?oG2f;J6V2*beT zCxp?Uc#0ju;t8~aFcLaGf&2snl@dTg5QvRA8f1<D)WBX@!CpM0 zkmnf#|62jRFAaRgJWg_l4$7WeD3fNu3Rc!EeTLcggtKiAvn|k!LInl}0U+(>AR;6h z!4S-F_=7H=!QPexR+obT-JB+@20U|}S-C$7HSy{I*@_!P^c80?2J(2MvbzWh_Am+n z1%cWb5*2`61Jc4Qj*@Is5*^?KLmM;5-5@*699>$LNH-N+ou&}8O_Sq#F885U>E?o` z*A!xYF^aetyUwr_5LCSS&B3K5MVduW@KUazi;Kq&PoUsapms1wRA68b0kVMhh_Z$R zIzWj83!nwOKyi@f5|C!0ItJE@K7wf=BX%lsgy(V|N}b(QaCe(R%nn12@H}3i_*Rg8 zH-Wk!?jLIAasb^83 %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){ +entry: +; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1 + %res1 = add nuw nsw <2 x i8> %x1, %x1 + +; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x2 + %res2 = add nuw nsw <3 x i8> %x2, %x2 + +; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3 + %res3 = add nuw nsw <4 x i8> %x3, %x3 + +; CHECK-NEXT: %res4 = add nuw nsw <8 x i8> %x4, %x4 + %res4 = add nuw nsw <8 x i8> %x4, %x4 + +; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5 + %res5 = add nuw nsw <16 x i8> %x5, %x5 + + ret void +} + +define void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> %x5){ +entry: +; CHECK: %res1 = add nuw nsw <2 x i16> %x1, %x1 + %res1 = add nuw nsw <2 x i16> %x1, %x1 + +; CHECK-NEXT: %res2 = add nuw nsw <3 x i16> %x2, %x2 + %res2 = add nuw nsw <3 x i16> %x2, %x2 + +; CHECK-NEXT: %res3 = add nuw nsw <4 x i16> %x3, %x3 + %res3 = add nuw nsw <4 x i16> %x3, %x3 + +; CHECK-NEXT: %res4 = add nuw nsw <8 x i16> %x4, %x4 + %res4 = add nuw nsw <8 x i16> %x4, %x4 + +; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5 + %res5 = add nuw nsw <16 x i16> %x5, %x5 + + ret void +} + +define void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> %x5){ +entry: +; CHECK: %res1 = add nuw nsw <2 x i32> %x1, %x1 + %res1 = add nuw nsw <2 x i32> %x1, %x1 + +; CHECK-NEXT: %res2 = add nuw nsw <3 x i32> %x2, %x2 + %res2 = add nuw nsw <3 x i32> %x2, %x2 + +; CHECK-NEXT: %res3 = add nuw nsw <4 x i32> %x3, %x3 + %res3 = add nuw nsw <4 x i32> %x3, %x3 + +; CHECK-NEXT: %res4 = add nuw nsw <8 x i32> %x4, %x4 + %res4 = add nuw nsw <8 x i32> %x4, %x4 + +; CHECK-NEXT: %res5 = add nuw nsw <16 x i32> %x5, %x5 + %res5 = add nuw nsw <16 x i32> %x5, %x5 + + ret void +} + +define void @addvec64NuwNsw(<2 x i64> %x1, <3 x i64> %x2 ,<4 x i64> %x3, <8 x i64> %x4, <16 x i64> %x5){ +entry: +; CHECK: %res1 = add nuw nsw <2 x i64> %x1, %x1 + %res1 = add nuw nsw <2 x i64> %x1, %x1 + +; CHECK-NEXT: %res2 = add nuw nsw <3 x i64> %x2, %x2 + %res2 = add nuw nsw <3 x i64> %x2, %x2 + +; CHECK-NEXT: %res3 = add nuw nsw <4 x i64> %x3, %x3 + %res3 = add nuw nsw <4 x i64> %x3, %x3 + +; CHECK-NEXT: %res4 = add nuw nsw <8 x i64> %x4, %x4 + %res4 = add nuw nsw <8 x i64> %x4, %x4 + +; CHECK-NEXT: %res5 = add nuw nsw <16 x i64> %x5, %x5 + %res5 = add nuw nsw <16 x i64> %x5, %x5 + + ret void +} + +define void @sub(i8 %x1){ +entry: +; CHECK: %res1 = sub i8 %x1, %x1 + %res1 = sub i8 %x1, %x1 + +; CHECK: %res2 = sub nuw i8 %x1, %x1 + %res2 = sub nuw i8 %x1, %x1 + +; CHECK: %res3 = sub nsw i8 %x1, %x1 + %res3 = sub nsw i8 %x1, %x1 + +; CHECK: %res4 = sub nuw nsw i8 %x1, %x1 + %res4 = sub nuw nsw i8 %x1, %x1 + + ret void +} + +define void @mul(i8 %x1){ +entry: +; CHECK: %res1 = mul i8 %x1, %x1 + %res1 = mul i8 %x1, %x1 + + ret void +} + +define void @udiv(i8 %x1){ +entry: +; CHECK: %res1 = udiv i8 %x1, %x1 + %res1 = udiv i8 %x1, %x1 + +; CHECK-NEXT: %res2 = udiv exact i8 %x1, %x1 + %res2 = udiv exact i8 %x1, %x1 + + ret void +} + +define void @sdiv(i8 %x1){ +entry: +; CHECK: %res1 = sdiv i8 %x1, %x1 + %res1 = sdiv i8 %x1, %x1 + +; CHECK-NEXT: %res2 = sdiv exact i8 %x1, %x1 + %res2 = sdiv exact i8 %x1, %x1 + + ret void +} + +define void @urem(i32 %x1){ +entry: +; CHECK: %res1 = urem i32 %x1, %x1 + %res1 = urem i32 %x1, %x1 + + ret void +} + +define void @srem(i32 %x1){ +entry: +; CHECK: %res1 = srem i32 %x1, %x1 + %res1 = srem i32 %x1, %x1 + + ret void +} diff --git a/llvm/test/Bitcode/binaryIntInstructions.3.2.ll.bc b/llvm/test/Bitcode/binaryIntInstructions.3.2.ll.bc new file mode 100644 index 0000000000000000000000000000000000000000..749e0c34dc844ad7342be90298794bf0147c2f65 GIT binary patch literal 1324 zcmeHG&rcIk5Pt3M(zRV-7h2t7C0mPFVobJ$Lpjv+$5M*vp)^D=a_A!92?C-9FJ=o% zv&J5fAOVT75R4r3-~pqFhb=|Y1CVGUiSb7?B-~6)G@hMp7dT*ue}FI9H(%y`^UZrR zJE5@p#YrI)H6Uae<&Y5}R0*Fc<+>Lv;H_n}w`tNKQ>O{iUW4E5me^)vXwni|rM*@k z$+nukLT%JM;dHGgB+Bl*R%;SGM2 zr(9H?H+m=+2d2@Ajbx(_l#U@bC@cAZ1|`&%4B!S*a;$!H^jQslCG3;)nUG|{DrVTgZV*Yh(qWY*t)MMA7?_(9!=f2FikY7e7md`G2_#4 zcKb~4!^vJ!ZshLQ(+PpU8Hi&EyNakW8&zrRGzOdTD_A*C*_@w#w_bYEGn-T67SI(z zzZz^69<&kdZ2^6oSqP}p1ir@e>L91Rd!OuHf z*GoUyaT^hDV@w|nr_0SW zQ&B#J&`~(s57afa@K*;j4(#XBq>FF)uf13Qy_!@2g8mZ08BS2sPCP<;psNUx;5WtT z4XgNq>st0e&)#nZ1i5DpgEse9fKX{vM4hW?q>?@wKNts|QvJ1mO5^2bxR};ZZHoSu gL!Yx^&vs)Bvt0aNW3;;$-y|M>pIu(+5FSXOKas0GoB#j- literal 0 HcmV?d00001 diff --git a/llvm/test/Bitcode/bitwiseInstructions.3.2.ll b/llvm/test/Bitcode/bitwiseInstructions.3.2.ll new file mode 100644 index 000000000000..6225a08f2064 --- /dev/null +++ b/llvm/test/Bitcode/bitwiseInstructions.3.2.ll @@ -0,0 +1,68 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; bitwiseOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not misread bitwise instructions from +; older bitcode files. + +define void @shl(i8 %x1){ +entry: +; CHECK: %res1 = shl i8 %x1, %x1 + %res1 = shl i8 %x1, %x1 + +; CHECK: %res2 = shl nuw i8 %x1, %x1 + %res2 = shl nuw i8 %x1, %x1 + +; CHECK: %res3 = shl nsw i8 %x1, %x1 + %res3 = shl nsw i8 %x1, %x1 + +; CHECK: %res4 = shl nuw nsw i8 %x1, %x1 + %res4 = shl nuw nsw i8 %x1, %x1 + + ret void +} + +define void @lshr(i8 %x1){ +entry: +; CHECK: %res1 = lshr i8 %x1, %x1 + %res1 = lshr i8 %x1, %x1 + +; CHECK: %res2 = lshr exact i8 %x1, %x1 + %res2 = lshr exact i8 %x1, %x1 + + ret void +} + +define void @ashr(i8 %x1){ +entry: +; CHECK: %res1 = ashr i8 %x1, %x1 + %res1 = ashr i8 %x1, %x1 + +; CHECK-NEXT: %res2 = ashr exact i8 %x1, %x1 + %res2 = ashr exact i8 %x1, %x1 + + ret void +} + +define void @and(i8 %x1){ +entry: +; CHECK: %res1 = and i8 %x1, %x1 + %res1 = and i8 %x1, %x1 + + ret void +} + +define void @or(i8 %x1){ +entry: +; CHECK: %res1 = or i8 %x1, %x1 + %res1 = or i8 %x1, %x1 + + ret void +} + +define void @xor(i8 %x1){ +entry: +; CHECK: %res1 = xor i8 %x1, %x1 + %res1 = xor i8 %x1, %x1 + + ret void +} \ No newline at end of file diff --git a/llvm/test/Bitcode/bitwiseInstructions.3.2.ll.bc b/llvm/test/Bitcode/bitwiseInstructions.3.2.ll.bc new file mode 100644 index 0000000000000000000000000000000000000000..136a7c9a0a2db4cd9ac9ff97b0cbfc2f3a2ab536 GIT binary patch literal 612 zcmZ>AK5$Qwhk;=l0|NthlL7-1kQM@B_D1E2jwe_=*#wL%Co#70sIqcM%CU4OHSoAH zIZfhrN)a#;vEY#K)3syKB`@je^r&ED}feT0* zDV^X@NNHu6thl5FNIY&?I6*|nr>%#(CB;WTK$)SK#Y0d4XtDDYkS-vQSOjzx2pkYd zg)kV}G?*bQ0~bjMqe1Z$RPIS41A`!tZOqXibL62+nh2w9hqFb?;U1?3_R0$O;u(cJ z&lvdM3h;et;4|iNk~?%z_S{05Gy_(!vS#Ts%(f?-ZF`t)fo2pcFfeccX*UIniM%`x z#u5hN z4-hyjl9;9tvsG3=Q1NP;gG))hQo~vY(PFX uy-?qS?S<)aoTZRLtR9e?K=w2ySqQLT+5r@SxCf^0Ad%`AlX05|G7|tTcYd${ literal 0 HcmV?d00001 diff --git a/llvm/test/Bitcode/conversionInstructions.3.2.ll b/llvm/test/Bitcode/conversionInstructions.3.2.ll new file mode 100644 index 000000000000..4b3f27386eff --- /dev/null +++ b/llvm/test/Bitcode/conversionInstructions.3.2.ll @@ -0,0 +1,104 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; conversionOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not misread conversion instructions from +; older bitcode files. + +define void @trunc(i32 %src){ +entry: +; CHECK: %res1 = trunc i32 %src to i8 + %res1 = trunc i32 %src to i8 + + ret void +} + +define void @zext(i32 %src){ +entry: +; CHECK: %res1 = zext i32 %src to i64 + %res1 = zext i32 %src to i64 + + ret void +} + +define void @sext(i32 %src){ +entry: +; CHECK: %res1 = sext i32 %src to i64 + %res1 = sext i32 %src to i64 + + ret void +} + +define void @fptrunc(double %src){ +entry: +; CHECK: %res1 = fptrunc double %src to float + %res1 = fptrunc double %src to float + + ret void +} + +define void @fpext(float %src){ +entry: +; CHECK: %res1 = fpext float %src to double + %res1 = fpext float %src to double + + ret void +} + +define void @fptoui(float %src){ +entry: +; CHECK: %res1 = fptoui float %src to i32 + %res1 = fptoui float %src to i32 + + ret void +} + +define void @fptosi(float %src){ +entry: +; CHECK: %res1 = fptosi float %src to i32 + %res1 = fptosi float %src to i32 + + ret void +} + +define void @uitofp(i32 %src){ +entry: +; CHECK: %res1 = uitofp i32 %src to float + %res1 = uitofp i32 %src to float + + ret void +} + +define void @sitofp(i32 %src){ +entry: +; CHECK: %res1 = sitofp i32 %src to float + %res1 = sitofp i32 %src to float + + ret void +} + +define void @ptrtoint(i32* %src){ +entry: +; CHECK: %res1 = ptrtoint i32* %src to i8 + %res1 = ptrtoint i32* %src to i8 + + ret void +} + +define void @inttoptr(i32 %src){ +entry: +; CHECK: %res1 = inttoptr i32 %src to i32* + %res1 = inttoptr i32 %src to i32* + + ret void +} + +define void @bitcast(i32 %src1, i32* %src2){ +entry: +; CHECK: %res1 = bitcast i32 %src1 to i32 + %res1 = bitcast i32 %src1 to i32 + +; CHECK: %res2 = bitcast i32* %src2 to i64* + %res2 = bitcast i32* %src2 to i64* + + ret void +} \ No newline at end of file diff --git a/llvm/test/Bitcode/conversionInstructions.3.2.ll.bc b/llvm/test/Bitcode/conversionInstructions.3.2.ll.bc new file mode 100644 index 0000000000000000000000000000000000000000..fabf7dab6fb876c375e394b5a54ca7ec09bffddd GIT binary patch literal 996 zcmZ>AK5$Qwhk@Z60|NthlL7-1kQM@B_D1E2jwe_=*#wL%Co#70sIqcM%CU4OHHf$} zIZfhrS|VU1V!55c4r3syKB`@je^r&ED}K@dnA zDS2=zq_nb3R$9^mBp$acoFF3P)78V>vcyNgLz$tNB_V)Cz=MZTgi%1tn8B5yU7%Ho z!F4r{f<{&`%Ly4q4FMMCDIgPpKw=Tl#UOA%AQi%3XwzVWunb&0A&dq^FOX+|fF}^- zBOplVFoG}`kc={b2q7EA2N9ak&Ioq9F-L>Uk%uyAB8;{j&K50)dz>2BD=XNGXB6^0 zW8i-)!1twr&zQ$a?$ANma|>nC3|PU+nx)S$+n#W??P0bB8ds>mz#s~w%?d=$iv;#2 zaB*Dnnf%#jBBy{*p>JA($oVH89f}e{MwUmDSzJE~Tu)(j`{={hdZW=%adNPYm_y1D zQ%MIy*AV3!hXfTSGk8o^RX8u=%Xi5KXl5eNY)&98%yN*G-#~_g706}}5I8H6c+9|K zVgj#=i-##t2n-Sx5NZubP#Zvk+UF#wWice)y@@24+em`ixgj!Id s2gWgHqJKyCLkD0S1NqQ+cJP=O5Y4RU+LX%&jP0$q0)mP+fwB+)0A%#TEC2ui literal 0 HcmV?d00001 diff --git a/llvm/test/Bitcode/terminatorInstructions.3.2.ll b/llvm/test/Bitcode/terminatorInstructions.3.2.ll new file mode 100644 index 000000000000..31e78967ee0c --- /dev/null +++ b/llvm/test/Bitcode/terminatorInstructions.3.2.ll @@ -0,0 +1,47 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; TerminatorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not misread terminator instructions from +; older bitcode files. + +define i32 @condbr(i1 %cond){ +entry: +; CHECK: br i1 %cond, label %TrueLabel, label %FalseLabel + br i1 %cond, label %TrueLabel, label %FalseLabel + + TrueLabel: + ret i32 1 + + FalseLabel: + ret i32 0 +} + +define i32 @uncondbr(){ +entry: +; CHECK: br label %uncondLabel + br label %uncondLabel + + uncondLabel: + ret i32 1 +} + +define i32 @indirectbr(i8* %Addr){ +entry: +; CHECK: indirectbr i8* %Addr, [label %bb1, label %bb2] + indirectbr i8* %Addr, [ label %bb1, label %bb2 ] + + bb1: + ret i32 1 + + bb2: + ret i32 0 +} + +define void @unreachable(){ +entry: +; CHECK: unreachable + unreachable + + ret void +} + diff --git a/llvm/test/Bitcode/terminatorInstructions.3.2.ll.bc b/llvm/test/Bitcode/terminatorInstructions.3.2.ll.bc new file mode 100644 index 0000000000000000000000000000000000000000..9d92ead8ad182880152b0ff57ee8bea15365020a GIT binary patch literal 568 zcmZ>AK5$Qwhk>D+fq{X$Nr8b0NDBcmd!zD1#}h1`Yyw7>lNeigR9QJB;VF2MH1Z{IQ)#~G<;(0b^!^3bTBX^ zDljnc0%>6uC$M=SZ?dQY&0=w6d+5Nx016O@cJU2hCvdVH0b2$XPgG!F0NI7jEuRIC z3vg(r2=K8mFt7pDK+P~7P#T&ka1W58l+%zKx%|pnvy_{2bm914`e_A08q7Y A?*IS* literal 0 HcmV?d00001 diff --git a/llvm/test/Bitcode/vectorInstructions.3.2.ll b/llvm/test/Bitcode/vectorInstructions.3.2.ll new file mode 100644 index 000000000000..b24ef75ef081 --- /dev/null +++ b/llvm/test/Bitcode/vectorInstructions.3.2.ll @@ -0,0 +1,34 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; vectorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not misread vector operations of +; older bitcode files. + +define void @extractelement(<2 x i8> %x1){ +entry: +; CHECK: %res1 = extractelement <2 x i8> %x1, i32 0 + %res1 = extractelement <2 x i8> %x1, i32 0 + + ret void +} + +define void @insertelement(<2 x i8> %x1){ +entry: +; CHECK: %res1 = insertelement <2 x i8> %x1, i8 0, i32 0 + %res1 = insertelement <2 x i8> %x1, i8 0, i32 0 + + ret void +} + +define void @shufflevector(<2 x i8> %x1){ +entry: +; CHECK: %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> + %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> + +; CHECK-NEXT: %res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> + %res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> + + ret void +} + + diff --git a/llvm/test/Bitcode/vectorInstructions.3.2.ll.bc b/llvm/test/Bitcode/vectorInstructions.3.2.ll.bc new file mode 100644 index 0000000000000000000000000000000000000000..b1727031701b1ad272b300209e52568860c5b3d8 GIT binary patch literal 500 zcmZ>AK5$Qwhk>Drfq{X$Nr8b0NDBcmd!zD1#}h1`Yyw7>lNeigR9QJBAfVK!kD8S;2;b22BA#Eey^g zAlCqa#3BI*DCQXFVw!_(?<#3Nv1AAo!d-04yo@WgF zZw2_iH1HYoILRG4D0^<9Oqu~JSXs058D`rP&bB?wwm>rq6&M(}fVA2L5B5+I?m)pq zPh8j@2wWFoJmjLo;%qXR)x<+t@FJKk3{;m0R1XX?24NOQ9gxF7{=5QoOfrX4!$SuK z1{NTnJwV{BNTQiS%vMnWLB*>;5r{reSitmwd^bgq;S~pvF6L<#NU#t<(<_Oh7i1T* o-X)R@pCXt97@Bzw3-A~TG=nT>1FAvT4c1@g;L?)93>1d}0M=G(>i_@% literal 0 HcmV?d00001