forked from OSchip/llvm-project
[AMDGPU] gfx1030 RT support
Differential Revision: https://reviews.llvm.org/D87782
This commit is contained in:
Stanislav Mekhanoshin
parent
56069b5c71
commit
91f503c3af
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@ -1698,6 +1698,14 @@ class AMDGPUGlobalAtomicRtn<LLVMType vt> : Intrinsic <
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def int_amdgcn_global_atomic_csub : AMDGPUGlobalAtomicRtn<llvm_i32_ty>;
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// uint4 llvm.amdgcn.image.bvh.intersect.ray <node_ptr>, <ray_extent>, <ray_origin>,
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// <ray_dir>, ray_inv_dir>, <texture_descr>
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def int_amdgcn_image_bvh_intersect_ray :
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Intrinsic<[llvm_v4i32_ty],
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[llvm_anyint_ty, llvm_float_ty, llvm_v4f32_ty, llvm_anyvector_ty,
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LLVMMatchType<1>, llvm_v4i32_ty],
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[IntrReadMem]>;
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//===----------------------------------------------------------------------===//
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// Deep learning intrinsics.
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//===----------------------------------------------------------------------===//
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@ -1444,6 +1444,7 @@ public:
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void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
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bool IsAtomic = false);
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void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
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void cvtIntersectRay(MCInst &Inst, const OperandVector &Operands);
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OperandMatchResultTy parseDim(OperandVector &Operands);
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OperandMatchResultTy parseDPP8(OperandVector &Operands);
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@ -3109,8 +3110,9 @@ bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst) {
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int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe);
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assert(VDataIdx != -1);
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assert(DMaskIdx != -1);
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assert(TFEIdx != -1);
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if (DMaskIdx == -1 || TFEIdx == -1) // intersect_ray
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return true;
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unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx);
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unsigned TFESize = Inst.getOperand(TFEIdx).getImm()? 1 : 0;
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@ -3137,6 +3139,7 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst) {
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return true;
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const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);
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const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
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AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
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int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
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@ -3145,9 +3148,11 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst) {
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assert(VAddr0Idx != -1);
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assert(SrsrcIdx != -1);
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assert(DimIdx != -1);
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assert(SrsrcIdx > VAddr0Idx);
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if (DimIdx == -1)
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return true; // intersect_ray
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unsigned Dim = Inst.getOperand(DimIdx).getImm();
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const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
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bool IsNSA = SrsrcIdx - VAddr0Idx > 1;
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@ -6466,6 +6471,17 @@ void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands)
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cvtMIMG(Inst, Operands, true);
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}
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void AMDGPUAsmParser::cvtIntersectRay(MCInst &Inst,
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const OperandVector &Operands) {
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for (unsigned I = 1; I < Operands.size(); ++I) {
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auto &Operand = (AMDGPUOperand &)*Operands[I];
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if (Operand.isReg())
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Operand.addRegOperands(Inst, 1);
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}
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Inst.addOperand(MCOperand::createImm(1)); // a16
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}
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//===----------------------------------------------------------------------===//
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// smrd
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//===----------------------------------------------------------------------===//
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@ -139,6 +139,8 @@ DECODE_OPERAND_REG(VS_128)
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DECODE_OPERAND_REG(VReg_64)
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DECODE_OPERAND_REG(VReg_96)
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DECODE_OPERAND_REG(VReg_128)
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DECODE_OPERAND_REG(VReg_256)
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DECODE_OPERAND_REG(VReg_512)
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DECODE_OPERAND_REG(SReg_32)
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DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
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@ -499,8 +501,16 @@ DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
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AMDGPU::OpName::d16);
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assert(VDataIdx != -1);
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assert(DMaskIdx != -1);
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assert(TFEIdx != -1);
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if (DMaskIdx == -1 || TFEIdx == -1) {// intersect_ray
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if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) {
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assert(MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa ||
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MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa ||
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MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa ||
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MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa);
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addOperand(MI, MCOperand::createImm(1));
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}
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return MCDisassembler::Success;
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}
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const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
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bool IsAtomic = (VDstIdx != -1);
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@ -708,6 +708,55 @@ multiclass MIMG_Gather <bits<8> op, AMDGPUSampleVariant sample, bit wqm = 0,
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multiclass MIMG_Gather_WQM <bits<8> op, AMDGPUSampleVariant sample>
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: MIMG_Gather<op, sample, 1>;
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class MIMG_IntersectRay_gfx10<int op, string opcode, RegisterClass AddrRC, bit A16>
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: MIMG_gfx10<op, (outs VReg_128:$vdata), "AMDGPU"> {
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let InOperandList = !con((ins AddrRC:$vaddr0, SReg_128:$srsrc),
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!if(!eq(A16,1), (ins GFX10A16:$a16), (ins)));
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let AsmString = opcode#" $vdata, $vaddr0, $srsrc"#!if(!eq(A16,1), "$a16", "");
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let nsa = 0;
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}
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class MIMG_IntersectRay_nsa_gfx10<int op, string opcode, int num_addrs, bit A16>
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: MIMG_nsa_gfx10<op, (outs VReg_128:$vdata), num_addrs, "AMDGPU"> {
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let InOperandList = !con(nsah.AddrIns,
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(ins SReg_128:$srsrc),
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!if(!eq(A16,1), (ins GFX10A16:$a16), (ins)));
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let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc"#!if(!eq(A16,1), "$a16", "");
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}
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multiclass MIMG_IntersectRay<int op, string opcode, int num_addrs, bit A16> {
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def "" : MIMGBaseOpcode;
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let SubtargetPredicate = HasGFX10_BEncoding,
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AssemblerPredicate = HasGFX10_BEncoding,
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AsmMatchConverter = !if(!eq(A16,1), "cvtIntersectRay", ""),
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dmask = 0xf,
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unorm = 1,
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d16 = 0,
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glc = 0,
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slc = 0,
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dlc = 0,
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tfe = 0,
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lwe = 0,
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r128 = 1,
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ssamp = 0,
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dim = {0, 0, 0},
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a16 = A16,
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d16 = 0,
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BaseOpcode = !cast<MIMGBaseOpcode>(NAME),
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VDataDwords = 4 in {
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// TODO: MIMGAddrSize will choose VReg_512 which is a 16 register tuple,
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// when we only need 9, 11 or 12 depending on A16 field and ptr size.
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def "_sa" : MIMG_IntersectRay_gfx10<op, opcode, MIMGAddrSize<num_addrs, 0>.RegClass, A16> {
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let VAddrDwords = !srl(MIMGAddrSize<num_addrs, 0>.RegClass.Size, 5);
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}
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def _nsa : MIMG_IntersectRay_nsa_gfx10<op, opcode, num_addrs, A16> {
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let VAddrDwords = num_addrs;
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// MIMG Instructions
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//===----------------------------------------------------------------------===//
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@ -832,6 +881,11 @@ defm IMAGE_SAMPLE_C_CD_CL_O_G16 : MIMG_Sampler <0x000000ef, AMDGPUSample_c_cd_cl
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let SubtargetPredicate = HasGFX10_BEncoding in
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defm IMAGE_MSAA_LOAD : MIMG_NoSampler <0x00000080, "image_msaa_load", 1>;
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defm IMAGE_BVH_INTERSECT_RAY : MIMG_IntersectRay<0xe6, "image_bvh_intersect_ray", 11, 0>;
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defm IMAGE_BVH_INTERSECT_RAY_a16 : MIMG_IntersectRay<0xe6, "image_bvh_intersect_ray", 8, 1>;
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defm IMAGE_BVH64_INTERSECT_RAY : MIMG_IntersectRay<0xe7, "image_bvh64_intersect_ray", 12, 0>;
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defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay<0xe7, "image_bvh64_intersect_ray", 9, 1>;
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/********** ========================================= **********/
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/********** Table of dimension-aware image intrinsics **********/
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/********** ========================================= **********/
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@ -80,9 +80,8 @@ bool SIAddIMGInit::runOnMachineFunction(MachineFunction &MF) {
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MachineOperand *LWE = TII->getNamedOperand(MI, AMDGPU::OpName::lwe);
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MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16);
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// Check for instructions that don't have tfe or lwe fields
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// There shouldn't be any at this point.
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assert( (TFE && LWE) && "Expected tfe and lwe operands in instruction");
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if (!TFE && !LWE) // intersect_ray
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continue;
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unsigned TFEVal = TFE->getImm();
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unsigned LWEVal = LWE->getImm();
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@ -1194,6 +1194,17 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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MachineMemOperand::MOVolatile;
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return true;
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}
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case Intrinsic::amdgcn_image_bvh_intersect_ray: {
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SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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Info.opc = ISD::INTRINSIC_W_CHAIN;
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Info.memVT = MVT::getVT(CI.getType()); // XXX: what is correct VT?
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Info.ptrVal = MFI->getImagePSV(
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*MF.getSubtarget<GCNSubtarget>().getInstrInfo(), CI.getArgOperand(5));
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Info.align.reset();
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Info.flags = MachineMemOperand::MOLoad |
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MachineMemOperand::MODereferenceable;
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return true;
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}
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case Intrinsic::amdgcn_ds_gws_init:
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case Intrinsic::amdgcn_ds_gws_barrier:
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case Intrinsic::amdgcn_ds_gws_sema_v:
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@ -7318,6 +7329,76 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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DAG.getVTList(VT, MVT::Other), Ops,
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M->getMemOperand());
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}
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case Intrinsic::amdgcn_image_bvh_intersect_ray: {
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SDLoc DL(Op);
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MemSDNode *M = cast<MemSDNode>(Op);
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SDValue NodePtr = M->getOperand(2);
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SDValue RayExtent = M->getOperand(3);
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SDValue RayOrigin = M->getOperand(4);
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SDValue RayDir = M->getOperand(5);
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SDValue RayInvDir = M->getOperand(6);
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SDValue TDescr = M->getOperand(7);
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assert(NodePtr.getValueType() == MVT::i32 ||
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NodePtr.getValueType() == MVT::i64);
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assert(RayDir.getValueType() == MVT::v4f16 ||
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RayDir.getValueType() == MVT::v4f32);
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bool IsA16 = RayDir.getValueType().getVectorElementType() == MVT::f16;
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bool Is64 = NodePtr.getValueType() == MVT::i64;
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unsigned Opcode = IsA16 ? Is64 ? AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa
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: AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa
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: Is64 ? AMDGPU::IMAGE_BVH64_INTERSECT_RAY_nsa
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: AMDGPU::IMAGE_BVH_INTERSECT_RAY_nsa;
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SmallVector<SDValue, 16> Ops;
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auto packLanes = [&DAG, &Ops, &DL] (SDValue Op, bool IsAligned) {
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SmallVector<SDValue, 3> Lanes;
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DAG.ExtractVectorElements(Op, Lanes, 0, 3);
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if (Lanes[0].getValueSizeInBits() == 32) {
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for (unsigned I = 0; I < 3; ++I)
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Ops.push_back(DAG.getBitcast(MVT::i32, Lanes[I]));
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} else {
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if (IsAligned) {
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Ops.push_back(
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DAG.getBitcast(MVT::i32,
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DAG.getBuildVector(MVT::v2f16, DL,
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{ Lanes[0], Lanes[1] })));
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Ops.push_back(Lanes[2]);
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} else {
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SDValue Elt0 = Ops.pop_back_val();
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Ops.push_back(
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DAG.getBitcast(MVT::i32,
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DAG.getBuildVector(MVT::v2f16, DL,
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{ Elt0, Lanes[0] })));
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Ops.push_back(
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DAG.getBitcast(MVT::i32,
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DAG.getBuildVector(MVT::v2f16, DL,
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{ Lanes[1], Lanes[2] })));
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}
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}
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};
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if (Is64)
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DAG.ExtractVectorElements(DAG.getBitcast(MVT::v2i32, NodePtr), Ops, 0, 2);
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else
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Ops.push_back(NodePtr);
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Ops.push_back(DAG.getBitcast(MVT::i32, RayExtent));
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packLanes(RayOrigin, true);
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packLanes(RayDir, true);
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packLanes(RayInvDir, false);
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Ops.push_back(TDescr);
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if (IsA16)
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Ops.push_back(DAG.getTargetConstant(1, DL, MVT::i1));
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Ops.push_back(M->getChain());
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auto *NewNode = DAG.getMachineNode(Opcode, DL, M->getVTList(), Ops);
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MachineMemOperand *MemRef = M->getMemOperand();
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DAG.setNodeMemRefs(NewNode, {MemRef});
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return SDValue(NewNode, 0);
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}
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default:
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if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
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AMDGPU::getImageDimIntrinsicInfo(IntrID))
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@ -10963,7 +11044,8 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
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unsigned Opcode = Node->getMachineOpcode();
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if (TII->isMIMG(Opcode) && !TII->get(Opcode).mayStore() &&
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!TII->isGather4(Opcode)) {
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!TII->isGather4(Opcode) &&
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AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::dmask) != -1) {
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return adjustWritemask(Node, DAG);
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}
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@ -393,6 +393,15 @@ static InstClassEnum getInstClass(unsigned Opc, const SIInstrInfo &TII) {
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case AMDGPU::DS_WRITE_B64:
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case AMDGPU::DS_WRITE_B64_gfx9:
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return DS_WRITE;
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case AMDGPU::IMAGE_BVH_INTERSECT_RAY_sa:
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case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_sa:
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case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa:
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case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa:
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case AMDGPU::IMAGE_BVH_INTERSECT_RAY_nsa:
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case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_nsa:
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case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa:
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case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa:
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return UNKNOWN;
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}
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}
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@ -272,8 +272,8 @@ void SIShrinkInstructions::shrinkMIMG(MachineInstr &MI) {
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// enabled
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int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe);
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int LWEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::lwe);
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unsigned TFEVal = MI.getOperand(TFEIdx).getImm();
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unsigned LWEVal = MI.getOperand(LWEIdx).getImm();
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unsigned TFEVal = (TFEIdx == -1) ? 0 : MI.getOperand(TFEIdx).getImm();
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unsigned LWEVal = (LWEIdx == -1) ? 0 : MI.getOperand(LWEIdx).getImm();
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int ToUntie = -1;
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if (TFEVal || LWEVal) {
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// TFE/LWE is enabled so we need to deal with an implicit tied operand
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@ -0,0 +1,162 @@
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; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(uint node_ptr, float ray_extent, float4 ray_origin, float4 ray_dir, float4 ray_inv_dir, uint4 texture_descr)
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; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(uint node_ptr, float ray_extent, float4 ray_origin, half4 ray_dir, half4 ray_inv_dir, uint4 texture_descr)
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; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(ulong node_ptr, float ray_extent, float4 ray_origin, float4 ray_dir, float4 ray_inv_dir, uint4 texture_descr)
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; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(ulong node_ptr, float ray_extent, float4 ray_origin, half4 ray_dir, half4 ray_inv_dir, uint4 texture_descr)
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declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32, float, <4 x float>, <4 x float>, <4 x float>, <4 x i32>)
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declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32, float, <4 x float>, <4 x half>, <4 x half>, <4 x i32>)
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declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64, float, <4 x float>, <4 x float>, <4 x float>, <4 x i32>)
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declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64, float, <4 x float>, <4 x half>, <4 x half>, <4 x i32>)
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; GCN-LABEL: {{^}}image_bvh_intersect_ray:
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; GCN: image_bvh_intersect_ray v[0:3], v[0:15], s[0:3]{{$}}
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; Arguments are flattened to represent the actual VGPR_A layout, so we have no
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; extra moves in the generated kernel.
|
||||
define amdgpu_ps <4 x float> @image_bvh_intersect_ray(i32 %node_ptr, float %ray_extent, float %ray_origin_x, float %ray_origin_y, float %ray_origin_z, float %ray_dir_x, float %ray_dir_y, float %ray_dir_z, float %ray_inv_dir_x, float %ray_inv_dir_y, float %ray_inv_dir_z, <4 x i32> inreg %tdescr) {
|
||||
main_body:
|
||||
%ray_origin0 = insertelement <4 x float> undef, float %ray_origin_x, i32 0
|
||||
%ray_origin1 = insertelement <4 x float> %ray_origin0, float %ray_origin_y, i32 1
|
||||
%ray_origin = insertelement <4 x float> %ray_origin1, float %ray_origin_z, i32 2
|
||||
%ray_dir0 = insertelement <4 x float> undef, float %ray_dir_x, i32 0
|
||||
%ray_dir1 = insertelement <4 x float> %ray_dir0, float %ray_dir_y, i32 1
|
||||
%ray_dir = insertelement <4 x float> %ray_dir1, float %ray_dir_z, i32 2
|
||||
%ray_inv_dir0 = insertelement <4 x float> undef, float %ray_inv_dir_x, i32 0
|
||||
%ray_inv_dir1 = insertelement <4 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
|
||||
%ray_inv_dir = insertelement <4 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
|
||||
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <4 x float> %ray_origin, <4 x float> %ray_dir, <4 x float> %ray_inv_dir, <4 x i32> %tdescr)
|
||||
%r = bitcast <4 x i32> %v to <4 x float>
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}image_bvh_intersect_ray_a16:
|
||||
; GCN: image_bvh_intersect_ray v[0:3], v[{{[0-9:]+}}], s[{{[0-9:]+}}] a16{{$}}
|
||||
define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, float inreg %ray_extent, <4 x float> inreg %ray_origin, <4 x half> inreg %ray_dir, <4 x half> inreg %ray_inv_dir, <4 x i32> inreg %tdescr) {
|
||||
main_body:
|
||||
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <4 x float> %ray_origin, <4 x half> %ray_dir, <4 x half> %ray_inv_dir, <4 x i32> %tdescr)
|
||||
%r = bitcast <4 x i32> %v to <4 x float>
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}image_bvh64_intersect_ray:
|
||||
; GCN: image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3]{{$}}
|
||||
; Arguments are flattened to represent the actual VGPR_A layout, so we have no
|
||||
; extra moves in the generated kernel.
|
||||
define amdgpu_ps <4 x float> @image_bvh64_intersect_ray(<2 x i32> %node_ptr_vec, float %ray_extent, float %ray_origin_x, float %ray_origin_y, float %ray_origin_z, float %ray_dir_x, float %ray_dir_y, float %ray_dir_z, float %ray_inv_dir_x, float %ray_inv_dir_y, float %ray_inv_dir_z, <4 x i32> inreg %tdescr) {
|
||||
main_body:
|
||||
%node_ptr = bitcast <2 x i32> %node_ptr_vec to i64
|
||||
%ray_origin0 = insertelement <4 x float> undef, float %ray_origin_x, i32 0
|
||||
%ray_origin1 = insertelement <4 x float> %ray_origin0, float %ray_origin_y, i32 1
|
||||
%ray_origin = insertelement <4 x float> %ray_origin1, float %ray_origin_z, i32 2
|
||||
%ray_dir0 = insertelement <4 x float> undef, float %ray_dir_x, i32 0
|
||||
%ray_dir1 = insertelement <4 x float> %ray_dir0, float %ray_dir_y, i32 1
|
||||
%ray_dir = insertelement <4 x float> %ray_dir1, float %ray_dir_z, i32 2
|
||||
%ray_inv_dir0 = insertelement <4 x float> undef, float %ray_inv_dir_x, i32 0
|
||||
%ray_inv_dir1 = insertelement <4 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
|
||||
%ray_inv_dir = insertelement <4 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
|
||||
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <4 x float> %ray_origin, <4 x float> %ray_dir, <4 x float> %ray_inv_dir, <4 x i32> %tdescr)
|
||||
%r = bitcast <4 x i32> %v to <4 x float>
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}image_bvh64_intersect_ray_a16:
|
||||
; GCN: image_bvh64_intersect_ray v[0:3], v[{{[0-9:]+}}], s[{{[0-9:]+}}] a16{{$}}
|
||||
define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr, float inreg %ray_extent, <4 x float> inreg %ray_origin, <4 x half> inreg %ray_dir, <4 x half> inreg %ray_inv_dir, <4 x i32> inreg %tdescr) {
|
||||
main_body:
|
||||
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 %node_ptr, float %ray_extent, <4 x float> %ray_origin, <4 x half> %ray_dir, <4 x half> %ray_inv_dir, <4 x i32> %tdescr)
|
||||
%r = bitcast <4 x i32> %v to <4 x float>
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; TODO: NSA reassign is very limited and cannot work with VGPR tuples and subregs.
|
||||
|
||||
; GCN-LABEL: {{^}}image_bvh_intersect_ray_nsa_reassign:
|
||||
; GCN: image_bvh_intersect_ray v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
|
||||
define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(i32* %p_node_ptr, float* %p_ray, <4 x i32> inreg %tdescr) {
|
||||
main_body:
|
||||
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep_node_ptr = getelementptr inbounds i32, i32* %p_node_ptr, i32 %lid
|
||||
%node_ptr = load i32, i32* %gep_node_ptr, align 4
|
||||
%gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
|
||||
%ray_extent = load float, float* %gep_ray, align 4
|
||||
%ray_origin0 = insertelement <4 x float> undef, float 0.0, i32 0
|
||||
%ray_origin1 = insertelement <4 x float> %ray_origin0, float 1.0, i32 1
|
||||
%ray_origin = insertelement <4 x float> %ray_origin1, float 2.0, i32 2
|
||||
%ray_dir0 = insertelement <4 x float> undef, float 3.0, i32 0
|
||||
%ray_dir1 = insertelement <4 x float> %ray_dir0, float 4.0, i32 1
|
||||
%ray_dir = insertelement <4 x float> %ray_dir1, float 5.0, i32 2
|
||||
%ray_inv_dir0 = insertelement <4 x float> undef, float 6.0, i32 0
|
||||
%ray_inv_dir1 = insertelement <4 x float> %ray_inv_dir0, float 7.0, i32 1
|
||||
%ray_inv_dir = insertelement <4 x float> %ray_inv_dir1, float 8.0, i32 2
|
||||
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <4 x float> %ray_origin, <4 x float> %ray_dir, <4 x float> %ray_inv_dir, <4 x i32> %tdescr)
|
||||
store <4 x i32> %v, <4 x i32>* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}image_bvh_intersect_ray_a16_nsa_reassign:
|
||||
; GCN: image_bvh_intersect_ray v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}] a16{{$}}
|
||||
define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(i32* %p_node_ptr, float* %p_ray, <4 x i32> inreg %tdescr) {
|
||||
main_body:
|
||||
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep_node_ptr = getelementptr inbounds i32, i32* %p_node_ptr, i32 %lid
|
||||
%node_ptr = load i32, i32* %gep_node_ptr, align 4
|
||||
%gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
|
||||
%ray_extent = load float, float* %gep_ray, align 4
|
||||
%ray_origin0 = insertelement <4 x float> undef, float 0.0, i32 0
|
||||
%ray_origin1 = insertelement <4 x float> %ray_origin0, float 1.0, i32 1
|
||||
%ray_origin = insertelement <4 x float> %ray_origin1, float 2.0, i32 2
|
||||
%ray_dir0 = insertelement <4 x half> undef, half 3.0, i32 0
|
||||
%ray_dir1 = insertelement <4 x half> %ray_dir0, half 4.0, i32 1
|
||||
%ray_dir = insertelement <4 x half> %ray_dir1, half 5.0, i32 2
|
||||
%ray_inv_dir0 = insertelement <4 x half> undef, half 6.0, i32 0
|
||||
%ray_inv_dir1 = insertelement <4 x half> %ray_inv_dir0, half 7.0, i32 1
|
||||
%ray_inv_dir = insertelement <4 x half> %ray_inv_dir1, half 8.0, i32 2
|
||||
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <4 x float> %ray_origin, <4 x half> %ray_dir, <4 x half> %ray_inv_dir, <4 x i32> %tdescr)
|
||||
store <4 x i32> %v, <4 x i32>* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}image_bvh64_intersect_ray_nsa_reassign:
|
||||
; GCN: image_bvh64_intersect_ray v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
|
||||
define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(float* %p_ray, <4 x i32> inreg %tdescr) {
|
||||
main_body:
|
||||
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
|
||||
%ray_extent = load float, float* %gep_ray, align 4
|
||||
%ray_origin0 = insertelement <4 x float> undef, float 0.0, i32 0
|
||||
%ray_origin1 = insertelement <4 x float> %ray_origin0, float 1.0, i32 1
|
||||
%ray_origin = insertelement <4 x float> %ray_origin1, float 2.0, i32 2
|
||||
%ray_dir0 = insertelement <4 x float> undef, float 3.0, i32 0
|
||||
%ray_dir1 = insertelement <4 x float> %ray_dir0, float 4.0, i32 1
|
||||
%ray_dir = insertelement <4 x float> %ray_dir1, float 5.0, i32 2
|
||||
%ray_inv_dir0 = insertelement <4 x float> undef, float 6.0, i32 0
|
||||
%ray_inv_dir1 = insertelement <4 x float> %ray_inv_dir0, float 7.0, i32 1
|
||||
%ray_inv_dir = insertelement <4 x float> %ray_inv_dir1, float 8.0, i32 2
|
||||
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <4 x float> %ray_origin, <4 x float> %ray_dir, <4 x float> %ray_inv_dir, <4 x i32> %tdescr)
|
||||
store <4 x i32> %v, <4 x i32>* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}image_bvh64_intersect_ray_a16_nsa_reassign:
|
||||
; GCN: image_bvh64_intersect_ray v[{{[0-9:]+}}], v[{{[0-9:]+}}], s[{{[0-9:]+}}] a16{{$}}
|
||||
define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(float* %p_ray, <4 x i32> inreg %tdescr) {
|
||||
main_body:
|
||||
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
|
||||
%ray_extent = load float, float* %gep_ray, align 4
|
||||
%ray_origin0 = insertelement <4 x float> undef, float 0.0, i32 0
|
||||
%ray_origin1 = insertelement <4 x float> %ray_origin0, float 1.0, i32 1
|
||||
%ray_origin = insertelement <4 x float> %ray_origin1, float 2.0, i32 2
|
||||
%ray_dir0 = insertelement <4 x half> undef, half 3.0, i32 0
|
||||
%ray_dir1 = insertelement <4 x half> %ray_dir0, half 4.0, i32 1
|
||||
%ray_dir = insertelement <4 x half> %ray_dir1, half 5.0, i32 2
|
||||
%ray_inv_dir0 = insertelement <4 x half> undef, half 6.0, i32 0
|
||||
%ray_inv_dir1 = insertelement <4 x half> %ray_inv_dir0, half 7.0, i32 1
|
||||
%ray_inv_dir = insertelement <4 x half> %ray_inv_dir1, half 8.0, i32 2
|
||||
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <4 x float> %ray_origin, <4 x half> %ray_dir, <4 x half> %ray_inv_dir, <4 x i32> %tdescr)
|
||||
store <4 x i32> %v, <4 x i32>* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x()
|
||||
|
|
@ -23,16 +23,16 @@ v_fma_legacy_f32 v0, v1, v2, v3
|
|||
// GFX10: error: instruction not supported on this GPU
|
||||
|
||||
image_bvh_intersect_ray v[4:7], v[9:24], s[4:7]
|
||||
// GFX10: error: invalid instruction
|
||||
// GFX10: error: instruction not supported on this GPU
|
||||
|
||||
image_bvh_intersect_ray v[4:7], v[9:16], s[4:7] a16
|
||||
// GFX10: error: invalid instruction
|
||||
// GFX10: error: invalid operand
|
||||
|
||||
image_bvh64_intersect_ray v[4:7], v[9:24], s[4:7]
|
||||
// GFX10: error: invalid instruction
|
||||
// GFX10: error: instruction not supported on this GPU
|
||||
|
||||
image_bvh64_intersect_ray v[4:7], v[9:24], s[4:7] a16
|
||||
// GFX10: error: invalid instruction
|
||||
// GFX10: error: invalid operand
|
||||
|
||||
image_msaa_load v[1:4], v5, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
// GFX10: error: not a valid operand.
|
||||
|
|
|
|||
|
|
@ -61,6 +61,30 @@ v_fma_legacy_f32 v0, v1, |v2|, -v3
|
|||
v_fma_legacy_f32 v0, s1, 2.0, -v3
|
||||
// GFX10: encoding: [0x00,0x00,0x40,0xd5,0x01,0xe8,0x0d,0x84]
|
||||
|
||||
image_bvh_intersect_ray v[4:7], v[9:24], s[4:7]
|
||||
// GFX10: encoding: [0x01,0x9f,0x98,0xf1,0x09,0x04,0x01,0x00]
|
||||
|
||||
image_bvh_intersect_ray v[4:7], v[9:16], s[4:7] a16
|
||||
// GFX10: encoding: [0x01,0x9f,0x98,0xf1,0x09,0x04,0x01,0x40]
|
||||
|
||||
image_bvh64_intersect_ray v[4:7], v[9:24], s[4:7]
|
||||
// GFX10: encoding: [0x01,0x9f,0x9c,0xf1,0x09,0x04,0x01,0x00]
|
||||
|
||||
image_bvh64_intersect_ray v[4:7], v[9:24], s[4:7] a16
|
||||
// GFX10: encoding: [0x01,0x9f,0x9c,0xf1,0x09,0x04,0x01,0x40]
|
||||
|
||||
image_bvh_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19, v37, v40], s[12:15]
|
||||
// GFX10: encoding: [0x07,0x9f,0x98,0xf1,0x32,0x27,0x03,0x00,0x2e,0x17,0x11,0x10,0x0f,0x15,0x14,0x13,0x25,0x28,0x00,0x00]
|
||||
|
||||
image_bvh_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20], s[12:15] a16
|
||||
// GFX10: encoding: [0x05,0x9f,0x98,0xf1,0x32,0x27,0x03,0x40,0x2e,0x17,0x11,0x10,0x0f,0x15,0x14,0x00]
|
||||
|
||||
image_bvh64_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19, v37, v40, v42], s[12:15]
|
||||
// GFX10: encoding: [0x07,0x9f,0x9c,0xf1,0x32,0x27,0x03,0x00,0x2e,0x17,0x11,0x10,0x0f,0x15,0x14,0x13,0x25,0x28,0x2a,0x00]
|
||||
|
||||
image_bvh64_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19], s[12:15] a16
|
||||
// GFX10: encoding: [0x05,0x9f,0x9c,0xf1,0x32,0x27,0x03,0x40,0x2e,0x17,0x11,0x10,0x0f,0x15,0x14,0x13]
|
||||
|
||||
image_msaa_load v[1:4], v5, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
// GFX10: encoding: [0x01,0x0f,0x00,0xf0,0x05,0x01,0x02,0x00]
|
||||
|
||||
|
|
|
|||
|
|
@ -52,6 +52,30 @@
|
|||
# GFX10: v_fma_legacy_f32 v0, s1, 2.0, -v3
|
||||
0x00,0x00,0x40,0xd5,0x01,0xe8,0x0d,0x84
|
||||
|
||||
# GFX10: image_bvh_intersect_ray v[4:7], v[9:24], s[4:7]
|
||||
0x01,0x9f,0x98,0xf1,0x09,0x04,0x01,0x00
|
||||
|
||||
# GFX10: image_bvh_intersect_ray v[4:7], v[9:16], s[4:7] a16
|
||||
0x01,0x9f,0x98,0xf1,0x09,0x04,0x01,0x40
|
||||
|
||||
# GFX10: image_bvh64_intersect_ray v[4:7], v[9:24], s[4:7]
|
||||
0x01,0x9f,0x9c,0xf1,0x09,0x04,0x01,0x00
|
||||
|
||||
# GFX10: image_bvh64_intersect_ray v[4:7], v[9:24], s[4:7] a16
|
||||
0x01,0x9f,0x9c,0xf1,0x09,0x04,0x01,0x40
|
||||
|
||||
# GFX10: image_bvh_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19, v37, v40], s[12:15]
|
||||
0x07,0x9f,0x98,0xf1,0x32,0x27,0x03,0x00,0x2e,0x17,0x11,0x10,0x0f,0x15,0x14,0x13,0x25,0x28,0x00,0x00
|
||||
|
||||
# GFX10: image_bvh_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20], s[12:15] a16
|
||||
0x05,0x9f,0x98,0xf1,0x32,0x27,0x03,0x40,0x2e,0x17,0x11,0x10,0x0f,0x15,0x14,0x00
|
||||
|
||||
# GFX10: image_bvh64_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19, v37, v40, v42], s[12:15]
|
||||
0x07,0x9f,0x9c,0xf1,0x32,0x27,0x03,0x00,0x2e,0x17,0x11,0x10,0x0f,0x15,0x14,0x13,0x25,0x28,0x2a,0x00
|
||||
|
||||
# GFX10: image_bvh64_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19], s[12:15] a16
|
||||
0x05,0x9f,0x9c,0xf1,0x32,0x27,0x03,0x40,0x2e,0x17,0x11,0x10,0x0f,0x15,0x14,0x13
|
||||
|
||||
# GFX10: image_msaa_load v[1:4], v5, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
0x01,0x0f,0x00,0xf0,0x05,0x01,0x02,0x00
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue