forked from OSchip/llvm-project
[X86] Replace MVT::SimpleValueType in the AsmParser library and getX86SubSuperRegister with just an unsigned representing size.
This a is step towards fixing a layering violation so the X86 AsmParser won't depending on CodeGen types. llvm-svn: 256425
This commit is contained in:
Craig Topper
parent
2c7d7c2584
commit
91dab7baee
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@ -13,7 +13,6 @@
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#include "X86RegisterInfo.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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@ -131,26 +130,26 @@ public:
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public:
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RegisterContext(unsigned AddressReg, unsigned ShadowReg,
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unsigned ScratchReg) {
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BusyRegs.push_back(convReg(AddressReg, MVT::i64));
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BusyRegs.push_back(convReg(ShadowReg, MVT::i64));
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BusyRegs.push_back(convReg(ScratchReg, MVT::i64));
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BusyRegs.push_back(convReg(AddressReg, 64));
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BusyRegs.push_back(convReg(ShadowReg, 64));
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BusyRegs.push_back(convReg(ScratchReg, 64));
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}
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unsigned AddressReg(MVT::SimpleValueType VT) const {
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return convReg(BusyRegs[REG_OFFSET_ADDRESS], VT);
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unsigned AddressReg(unsigned Size) const {
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return convReg(BusyRegs[REG_OFFSET_ADDRESS], Size);
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}
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unsigned ShadowReg(MVT::SimpleValueType VT) const {
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return convReg(BusyRegs[REG_OFFSET_SHADOW], VT);
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unsigned ShadowReg(unsigned Size) const {
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return convReg(BusyRegs[REG_OFFSET_SHADOW], Size);
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}
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unsigned ScratchReg(MVT::SimpleValueType VT) const {
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return convReg(BusyRegs[REG_OFFSET_SCRATCH], VT);
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unsigned ScratchReg(unsigned Size) const {
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return convReg(BusyRegs[REG_OFFSET_SCRATCH], Size);
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}
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void AddBusyReg(unsigned Reg) {
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if (Reg != X86::NoRegister)
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BusyRegs.push_back(convReg(Reg, MVT::i64));
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BusyRegs.push_back(convReg(Reg, 64));
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}
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void AddBusyRegs(const X86Operand &Op) {
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@ -158,20 +157,20 @@ public:
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AddBusyReg(Op.getMemIndexReg());
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}
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unsigned ChooseFrameReg(MVT::SimpleValueType VT) const {
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unsigned ChooseFrameReg(unsigned Size) const {
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static const MCPhysReg Candidates[] = { X86::RBP, X86::RAX, X86::RBX,
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X86::RCX, X86::RDX, X86::RDI,
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X86::RSI };
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for (unsigned Reg : Candidates) {
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if (!std::count(BusyRegs.begin(), BusyRegs.end(), Reg))
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return convReg(Reg, VT);
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return convReg(Reg, Size);
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}
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return X86::NoRegister;
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}
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private:
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unsigned convReg(unsigned Reg, MVT::SimpleValueType VT) const {
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return Reg == X86::NoRegister ? Reg : getX86SubSuperRegister(Reg, VT);
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unsigned convReg(unsigned Reg, unsigned Size) const {
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return Reg == X86::NoRegister ? Reg : getX86SubSuperRegister(Reg, Size);
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}
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std::vector<unsigned> BusyRegs;
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@ -235,17 +234,16 @@ public:
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protected:
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void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
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void EmitLEA(X86Operand &Op, MVT::SimpleValueType VT, unsigned Reg,
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MCStreamer &Out) {
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assert(VT == MVT::i32 || VT == MVT::i64);
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void EmitLEA(X86Operand &Op, unsigned Size, unsigned Reg, MCStreamer &Out) {
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assert(Size == 32 || Size == 64);
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MCInst Inst;
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Inst.setOpcode(VT == MVT::i32 ? X86::LEA32r : X86::LEA64r);
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Inst.addOperand(MCOperand::createReg(getX86SubSuperRegister(Reg, VT)));
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Inst.setOpcode(Size == 32 ? X86::LEA32r : X86::LEA64r);
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Inst.addOperand(MCOperand::createReg(getX86SubSuperRegister(Reg, Size)));
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Op.addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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void ComputeMemOperandAddress(X86Operand &Op, MVT::SimpleValueType VT,
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void ComputeMemOperandAddress(X86Operand &Op, unsigned Size,
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unsigned Reg, MCContext &Ctx, MCStreamer &Out);
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// Creates new memory operand with Displacement added to an original
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@ -432,7 +430,7 @@ void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
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}
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void X86AddressSanitizer::ComputeMemOperandAddress(X86Operand &Op,
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MVT::SimpleValueType VT,
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unsigned Size,
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unsigned Reg, MCContext &Ctx,
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MCStreamer &Out) {
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int64_t Displacement = 0;
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@ -445,14 +443,14 @@ void X86AddressSanitizer::ComputeMemOperandAddress(X86Operand &Op,
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// Emit Op as is.
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if (Displacement == 0) {
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EmitLEA(Op, VT, Reg, Out);
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EmitLEA(Op, Size, Reg, Out);
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return;
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}
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int64_t Residue;
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std::unique_ptr<X86Operand> NewOp =
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AddDisplacement(Op, Displacement, Ctx, &Residue);
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EmitLEA(*NewOp, VT, Reg, Out);
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EmitLEA(*NewOp, Size, Reg, Out);
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while (Residue != 0) {
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const MCConstantExpr *Disp =
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@ -460,7 +458,7 @@ void X86AddressSanitizer::ComputeMemOperandAddress(X86Operand &Op,
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std::unique_ptr<X86Operand> DispOp =
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X86Operand::CreateMem(getPointerWidth(), 0, Disp, Reg, 0, 1, SMLoc(),
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SMLoc());
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EmitLEA(*DispOp, VT, Reg, Out);
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EmitLEA(*DispOp, Size, Reg, Out);
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Residue -= Disp->getValue();
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}
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}
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@ -507,7 +505,7 @@ public:
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unsigned FrameReg = GetFrameRegGeneric(Ctx, Out);
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if (FrameReg == X86::NoRegister)
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return FrameReg;
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return getX86SubSuperRegister(FrameReg, MVT::i32);
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return getX86SubSuperRegister(FrameReg, 32);
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}
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void SpillReg(MCStreamer &Out, unsigned Reg) {
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@ -533,7 +531,7 @@ public:
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void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
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MCContext &Ctx,
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MCStreamer &Out) override {
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unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i32);
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unsigned LocalFrameReg = RegCtx.ChooseFrameReg(32);
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assert(LocalFrameReg != X86::NoRegister);
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const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
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@ -553,24 +551,24 @@ public:
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MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */));
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}
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SpillReg(Out, RegCtx.AddressReg(MVT::i32));
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SpillReg(Out, RegCtx.ShadowReg(MVT::i32));
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if (RegCtx.ScratchReg(MVT::i32) != X86::NoRegister)
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SpillReg(Out, RegCtx.ScratchReg(MVT::i32));
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SpillReg(Out, RegCtx.AddressReg(32));
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SpillReg(Out, RegCtx.ShadowReg(32));
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if (RegCtx.ScratchReg(32) != X86::NoRegister)
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SpillReg(Out, RegCtx.ScratchReg(32));
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StoreFlags(Out);
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}
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void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
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MCContext &Ctx,
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MCStreamer &Out) override {
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unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i32);
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unsigned LocalFrameReg = RegCtx.ChooseFrameReg(32);
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assert(LocalFrameReg != X86::NoRegister);
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RestoreFlags(Out);
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if (RegCtx.ScratchReg(MVT::i32) != X86::NoRegister)
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RestoreReg(Out, RegCtx.ScratchReg(MVT::i32));
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RestoreReg(Out, RegCtx.ShadowReg(MVT::i32));
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RestoreReg(Out, RegCtx.AddressReg(MVT::i32));
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if (RegCtx.ScratchReg(32) != X86::NoRegister)
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RestoreReg(Out, RegCtx.ScratchReg(32));
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RestoreReg(Out, RegCtx.ShadowReg(32));
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RestoreReg(Out, RegCtx.AddressReg(32));
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unsigned FrameReg = GetFrameReg(Ctx, Out);
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if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
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@ -605,7 +603,7 @@ private:
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.addReg(X86::ESP)
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.addImm(-16));
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EmitInstruction(
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Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.AddressReg(MVT::i32)));
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Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.AddressReg(32)));
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MCSymbol *FnSym = Ctx.getOrCreateSymbol(llvm::Twine("__asan_report_") +
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(IsWrite ? "store" : "load") +
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@ -619,14 +617,14 @@ private:
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void X86AddressSanitizer32::InstrumentMemOperandSmall(
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X86Operand &Op, unsigned AccessSize, bool IsWrite,
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const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
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unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
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unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
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unsigned ShadowRegI8 = RegCtx.ShadowReg(MVT::i8);
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unsigned AddressRegI32 = RegCtx.AddressReg(32);
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unsigned ShadowRegI32 = RegCtx.ShadowReg(32);
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unsigned ShadowRegI8 = RegCtx.ShadowReg(8);
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assert(RegCtx.ScratchReg(MVT::i32) != X86::NoRegister);
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unsigned ScratchRegI32 = RegCtx.ScratchReg(MVT::i32);
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assert(RegCtx.ScratchReg(32) != X86::NoRegister);
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unsigned ScratchRegI32 = RegCtx.ScratchReg(32);
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ComputeMemOperandAddress(Op, MVT::i32, AddressRegI32, Ctx, Out);
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ComputeMemOperandAddress(Op, 32, AddressRegI32, Ctx, Out);
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EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
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AddressRegI32));
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@ -669,7 +667,7 @@ void X86AddressSanitizer32::InstrumentMemOperandSmall(
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(getPointerWidth(), 0, Disp, ScratchRegI32, 0, 1,
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SMLoc(), SMLoc()));
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EmitLEA(*Op, MVT::i32, ScratchRegI32, Out);
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EmitLEA(*Op, 32, ScratchRegI32, Out);
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break;
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}
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case 4:
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@ -694,10 +692,10 @@ void X86AddressSanitizer32::InstrumentMemOperandSmall(
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void X86AddressSanitizer32::InstrumentMemOperandLarge(
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X86Operand &Op, unsigned AccessSize, bool IsWrite,
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const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
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unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
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unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
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unsigned AddressRegI32 = RegCtx.AddressReg(32);
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unsigned ShadowRegI32 = RegCtx.ShadowReg(32);
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ComputeMemOperandAddress(Op, MVT::i32, AddressRegI32, Ctx, Out);
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ComputeMemOperandAddress(Op, 32, AddressRegI32, Ctx, Out);
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EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
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AddressRegI32));
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@ -765,7 +763,7 @@ public:
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unsigned FrameReg = GetFrameRegGeneric(Ctx, Out);
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if (FrameReg == X86::NoRegister)
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return FrameReg;
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return getX86SubSuperRegister(FrameReg, MVT::i64);
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return getX86SubSuperRegister(FrameReg, 64);
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}
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void SpillReg(MCStreamer &Out, unsigned Reg) {
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@ -791,7 +789,7 @@ public:
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void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
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MCContext &Ctx,
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MCStreamer &Out) override {
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unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i64);
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unsigned LocalFrameReg = RegCtx.ChooseFrameReg(64);
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assert(LocalFrameReg != X86::NoRegister);
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const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
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@ -812,24 +810,24 @@ public:
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}
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EmitAdjustRSP(Ctx, Out, -128);
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SpillReg(Out, RegCtx.ShadowReg(MVT::i64));
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SpillReg(Out, RegCtx.AddressReg(MVT::i64));
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if (RegCtx.ScratchReg(MVT::i64) != X86::NoRegister)
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SpillReg(Out, RegCtx.ScratchReg(MVT::i64));
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SpillReg(Out, RegCtx.ShadowReg(64));
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SpillReg(Out, RegCtx.AddressReg(64));
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if (RegCtx.ScratchReg(64) != X86::NoRegister)
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SpillReg(Out, RegCtx.ScratchReg(64));
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StoreFlags(Out);
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}
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void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
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MCContext &Ctx,
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MCStreamer &Out) override {
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unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i64);
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unsigned LocalFrameReg = RegCtx.ChooseFrameReg(64);
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assert(LocalFrameReg != X86::NoRegister);
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RestoreFlags(Out);
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if (RegCtx.ScratchReg(MVT::i64) != X86::NoRegister)
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RestoreReg(Out, RegCtx.ScratchReg(MVT::i64));
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RestoreReg(Out, RegCtx.AddressReg(MVT::i64));
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RestoreReg(Out, RegCtx.ShadowReg(MVT::i64));
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if (RegCtx.ScratchReg(64) != X86::NoRegister)
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RestoreReg(Out, RegCtx.ScratchReg(64));
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RestoreReg(Out, RegCtx.AddressReg(64));
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RestoreReg(Out, RegCtx.ShadowReg(64));
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EmitAdjustRSP(Ctx, Out, 128);
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unsigned FrameReg = GetFrameReg(Ctx, Out);
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@ -860,7 +858,7 @@ private:
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(getPointerWidth(), 0, Disp, X86::RSP, 0, 1,
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SMLoc(), SMLoc()));
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EmitLEA(*Op, MVT::i64, X86::RSP, Out);
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EmitLEA(*Op, 64, X86::RSP, Out);
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OrigSPOffset += Offset;
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}
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@ -874,9 +872,9 @@ private:
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.addReg(X86::RSP)
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.addImm(-16));
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if (RegCtx.AddressReg(MVT::i64) != X86::RDI) {
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if (RegCtx.AddressReg(64) != X86::RDI) {
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EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RDI).addReg(
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RegCtx.AddressReg(MVT::i64)));
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RegCtx.AddressReg(64)));
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}
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MCSymbol *FnSym = Ctx.getOrCreateSymbol(llvm::Twine("__asan_report_") +
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(IsWrite ? "store" : "load") +
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@ -890,16 +888,16 @@ private:
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void X86AddressSanitizer64::InstrumentMemOperandSmall(
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X86Operand &Op, unsigned AccessSize, bool IsWrite,
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const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
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unsigned AddressRegI64 = RegCtx.AddressReg(MVT::i64);
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unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
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unsigned ShadowRegI64 = RegCtx.ShadowReg(MVT::i64);
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unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
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unsigned ShadowRegI8 = RegCtx.ShadowReg(MVT::i8);
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unsigned AddressRegI64 = RegCtx.AddressReg(64);
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unsigned AddressRegI32 = RegCtx.AddressReg(32);
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unsigned ShadowRegI64 = RegCtx.ShadowReg(64);
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unsigned ShadowRegI32 = RegCtx.ShadowReg(32);
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unsigned ShadowRegI8 = RegCtx.ShadowReg(8);
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assert(RegCtx.ScratchReg(MVT::i32) != X86::NoRegister);
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unsigned ScratchRegI32 = RegCtx.ScratchReg(MVT::i32);
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assert(RegCtx.ScratchReg(32) != X86::NoRegister);
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unsigned ScratchRegI32 = RegCtx.ScratchReg(32);
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ComputeMemOperandAddress(Op, MVT::i64, AddressRegI64, Ctx, Out);
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ComputeMemOperandAddress(Op, 64, AddressRegI64, Ctx, Out);
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EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
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AddressRegI64));
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@ -941,7 +939,7 @@ void X86AddressSanitizer64::InstrumentMemOperandSmall(
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(getPointerWidth(), 0, Disp, ScratchRegI32, 0, 1,
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SMLoc(), SMLoc()));
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EmitLEA(*Op, MVT::i32, ScratchRegI32, Out);
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EmitLEA(*Op, 32, ScratchRegI32, Out);
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break;
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}
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case 4:
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@ -966,10 +964,10 @@ void X86AddressSanitizer64::InstrumentMemOperandSmall(
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void X86AddressSanitizer64::InstrumentMemOperandLarge(
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X86Operand &Op, unsigned AccessSize, bool IsWrite,
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const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
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unsigned AddressRegI64 = RegCtx.AddressReg(MVT::i64);
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unsigned ShadowRegI64 = RegCtx.ShadowReg(MVT::i64);
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unsigned AddressRegI64 = RegCtx.AddressReg(64);
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unsigned ShadowRegI64 = RegCtx.ShadowReg(64);
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ComputeMemOperandAddress(Op, MVT::i64, AddressRegI64, Ctx, Out);
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ComputeMemOperandAddress(Op, 64, AddressRegI64, Ctx, Out);
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EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
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AddressRegI64));
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@ -217,10 +217,10 @@ static void printOperand(X86AsmPrinter &P, const MachineInstr *MI,
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if (AsmVariant == 0) O << '%';
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unsigned Reg = MO.getReg();
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if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
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MVT::SimpleValueType VT = (strcmp(Modifier+6,"64") == 0) ?
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MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
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((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
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Reg = getX86SubSuperRegister(Reg, VT);
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unsigned Size = (strcmp(Modifier+6,"64") == 0) ? 64 :
|
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(strcmp(Modifier+6,"32") == 0) ? 32 :
|
||||
(strcmp(Modifier+6,"16") == 0) ? 16 : 8;
|
||||
Reg = getX86SubSuperRegister(Reg, Size);
|
||||
}
|
||||
O << X86ATTInstPrinter::getRegisterName(Reg);
|
||||
return;
|
||||
|
|
@ -361,22 +361,21 @@ static bool printAsmMRegister(X86AsmPrinter &P, const MachineOperand &MO,
|
|||
switch (Mode) {
|
||||
default: return true; // Unknown mode.
|
||||
case 'b': // Print QImode register
|
||||
Reg = getX86SubSuperRegister(Reg, MVT::i8);
|
||||
Reg = getX86SubSuperRegister(Reg, 8);
|
||||
break;
|
||||
case 'h': // Print QImode high register
|
||||
Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
|
||||
Reg = getX86SubSuperRegister(Reg, 8, true);
|
||||
break;
|
||||
case 'w': // Print HImode register
|
||||
Reg = getX86SubSuperRegister(Reg, MVT::i16);
|
||||
Reg = getX86SubSuperRegister(Reg, 16);
|
||||
break;
|
||||
case 'k': // Print SImode register
|
||||
Reg = getX86SubSuperRegister(Reg, MVT::i32);
|
||||
Reg = getX86SubSuperRegister(Reg, 32);
|
||||
break;
|
||||
case 'q':
|
||||
// Print 64-bit register names if 64-bit integer registers are available.
|
||||
// Otherwise, print 32-bit register names.
|
||||
MVT::SimpleValueType Ty = P.getSubtarget().is64Bit() ? MVT::i64 : MVT::i32;
|
||||
Reg = getX86SubSuperRegister(Reg, Ty);
|
||||
Reg = getX86SubSuperRegister(Reg, P.getSubtarget().is64Bit() ? 64 : 32);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -927,7 +927,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
|
|||
unsigned FramePtr = TRI->getFrameRegister(MF);
|
||||
const unsigned MachineFramePtr =
|
||||
STI.isTarget64BitILP32()
|
||||
? getX86SubSuperRegister(FramePtr, MVT::i64) : FramePtr;
|
||||
? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
|
||||
unsigned BasePtr = TRI->getBaseRegister();
|
||||
|
||||
// Debug location must be unknown since the first debug location is used
|
||||
|
|
@ -1465,7 +1465,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
|
|||
const bool Is64BitILP32 = STI.isTarget64BitILP32();
|
||||
unsigned FramePtr = TRI->getFrameRegister(MF);
|
||||
unsigned MachineFramePtr =
|
||||
Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64) : FramePtr;
|
||||
Is64BitILP32 ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
|
||||
|
||||
bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
|
||||
bool NeedsWinCFI =
|
||||
|
|
|
|||
|
|
@ -28523,17 +28523,13 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
|||
if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
|
||||
Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
|
||||
unsigned Size = VT.getSizeInBits();
|
||||
MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
|
||||
: Size == 16 ? MVT::i16
|
||||
: Size == 32 ? MVT::i32
|
||||
: Size == 64 ? MVT::i64
|
||||
: MVT::Other;
|
||||
unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
|
||||
if (Size == 1) Size = 8;
|
||||
unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, Size);
|
||||
if (DestReg > 0) {
|
||||
Res.first = DestReg;
|
||||
Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
|
||||
: SimpleTy == MVT::i16 ? &X86::GR16RegClass
|
||||
: SimpleTy == MVT::i32 ? &X86::GR32RegClass
|
||||
Res.second = Size == 8 ? &X86::GR8RegClass
|
||||
: Size == 16 ? &X86::GR16RegClass
|
||||
: Size == 32 ? &X86::GR32RegClass
|
||||
: &X86::GR64RegClass;
|
||||
assert(Res.second->contains(Res.first) && "Register in register class");
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -2570,7 +2570,7 @@ bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
|
|||
ImplicitOp = Src;
|
||||
ImplicitOp.setImplicit();
|
||||
|
||||
NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
|
||||
NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
|
||||
MachineBasicBlock::LivenessQueryResult LQR =
|
||||
MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
|
||||
|
||||
|
|
@ -4304,11 +4304,11 @@ static bool GRRegClassContains(unsigned Reg) {
|
|||
static
|
||||
unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
|
||||
if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
|
||||
DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
|
||||
DestReg = getX86SubSuperRegister(DestReg, 32);
|
||||
return X86::KMOVBrk;
|
||||
}
|
||||
if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
|
||||
SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
|
||||
SrcReg = getX86SubSuperRegister(SrcReg, 32);
|
||||
return X86::KMOVBkr;
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -4349,11 +4349,11 @@ unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
|
|||
if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
|
||||
return X86::KMOVWkk;
|
||||
if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
|
||||
SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
|
||||
SrcReg = getX86SubSuperRegister(SrcReg, 32);
|
||||
return X86::KMOVWkr;
|
||||
}
|
||||
if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
|
||||
DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
|
||||
DestReg = getX86SubSuperRegister(DestReg, 32);
|
||||
return X86::KMOVWrk;
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -5329,7 +5329,7 @@ bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
|
|||
BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
|
||||
MIB->setDesc(get(X86::POP64r));
|
||||
MIB->getOperand(0)
|
||||
.setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), MVT::i64));
|
||||
.setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
|
||||
} else {
|
||||
assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
|
||||
StackAdjustment = 4;
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@
|
|||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineModuleInfo.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/MachineValueType.h"
|
||||
#include "llvm/IR/Constants.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/IR/Type.h"
|
||||
|
|
@ -420,7 +419,7 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
|||
"Stack realignment in presence of dynamic allocas is not supported with"
|
||||
"this calling convention.");
|
||||
|
||||
unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), MVT::i64);
|
||||
unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
|
||||
for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
|
||||
I.isValid(); ++I)
|
||||
Reserved.set(*I);
|
||||
|
|
@ -573,7 +572,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
// register as source operand, semantic is the same and destination is
|
||||
// 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
|
||||
if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
|
||||
BasePtr = getX86SubSuperRegister(BasePtr, MVT::i64);
|
||||
BasePtr = getX86SubSuperRegister(BasePtr, 64);
|
||||
|
||||
// This must be part of a four operand memory reference. Replace the
|
||||
// FrameIndex with base register with EBP. Add an offset to the offset.
|
||||
|
|
@ -625,19 +624,18 @@ X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
|
|||
const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
|
||||
unsigned FrameReg = getFrameRegister(MF);
|
||||
if (Subtarget.isTarget64BitILP32())
|
||||
FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32);
|
||||
FrameReg = getX86SubSuperRegister(FrameReg, 32);
|
||||
return FrameReg;
|
||||
}
|
||||
|
||||
namespace llvm {
|
||||
unsigned getX86SubSuperRegisterOrZero(unsigned Reg, MVT::SimpleValueType VT,
|
||||
bool High) {
|
||||
switch (VT) {
|
||||
unsigned getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size, bool High) {
|
||||
switch (Size) {
|
||||
default: return 0;
|
||||
case MVT::i8:
|
||||
case 8:
|
||||
if (High) {
|
||||
switch (Reg) {
|
||||
default: return getX86SubSuperRegisterOrZero(Reg, MVT::i64);
|
||||
default: return getX86SubSuperRegisterOrZero(Reg, 64);
|
||||
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
||||
return X86::SI;
|
||||
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
||||
|
|
@ -692,7 +690,7 @@ unsigned getX86SubSuperRegisterOrZero(unsigned Reg, MVT::SimpleValueType VT,
|
|||
return X86::R15B;
|
||||
}
|
||||
}
|
||||
case MVT::i16:
|
||||
case 16:
|
||||
switch (Reg) {
|
||||
default: return 0;
|
||||
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
||||
|
|
@ -728,7 +726,7 @@ unsigned getX86SubSuperRegisterOrZero(unsigned Reg, MVT::SimpleValueType VT,
|
|||
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
||||
return X86::R15W;
|
||||
}
|
||||
case MVT::i32:
|
||||
case 32:
|
||||
switch (Reg) {
|
||||
default: return 0;
|
||||
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
||||
|
|
@ -764,7 +762,7 @@ unsigned getX86SubSuperRegisterOrZero(unsigned Reg, MVT::SimpleValueType VT,
|
|||
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
||||
return X86::R15D;
|
||||
}
|
||||
case MVT::i64:
|
||||
case 64:
|
||||
switch (Reg) {
|
||||
default: return 0;
|
||||
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
||||
|
|
@ -803,9 +801,8 @@ unsigned getX86SubSuperRegisterOrZero(unsigned Reg, MVT::SimpleValueType VT,
|
|||
}
|
||||
}
|
||||
|
||||
unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
|
||||
bool High) {
|
||||
unsigned Res = getX86SubSuperRegisterOrZero(Reg, VT, High);
|
||||
unsigned getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
|
||||
unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
|
||||
assert(Res != 0 && "Unexpected register or VT");
|
||||
return Res;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -136,13 +136,13 @@ public:
|
|||
};
|
||||
|
||||
/// Returns the sub or super register of a specific X86 register.
|
||||
/// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) returns X86::AX.
|
||||
/// e.g. getX86SubSuperRegister(X86::EAX, 16) returns X86::AX.
|
||||
/// Aborts on error.
|
||||
unsigned getX86SubSuperRegister(unsigned, MVT::SimpleValueType, bool High=false);
|
||||
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false);
|
||||
|
||||
/// Returns the sub or super register of a specific X86 register.
|
||||
/// Like getX86SubSuperRegister() but returns 0 on error.
|
||||
unsigned getX86SubSuperRegisterOrZero(unsigned, MVT::SimpleValueType,
|
||||
unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned,
|
||||
bool High = false);
|
||||
|
||||
//get512BitRegister - X86 utility - returns 512-bit super register
|
||||
|
|
|
|||
Loading…
Reference in New Issue