From 91c668a2765c7858e110aa9179f4d0a22aa86d3f Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Wed, 12 Sep 2018 19:44:26 +0000 Subject: [PATCH] [NFC][InstCombine] R38708 - inefficient pattern for high-bits checking. More complicated, canonical pattern: https://rise4fun.com/Alive/uhA https://godbolt.org/z/o4RB8D Also, we need to be careful not to skip some patters... https://bugs.llvm.org/show_bug.cgi?id=38708 llvm-svn: 342074 --- ...al-to-icmp-eq-of-lshr-val-by-bits-and-0.ll | 240 ++++++++++++++++++ ...al-to-icmp-ne-of-lshr-val-by-bits-and-0.ll | 240 ++++++++++++++++++ .../interference-tests-for-high-bit-check.ll | 141 ++++++++++ 3 files changed, 621 insertions(+) create mode 100644 llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll create mode 100644 llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll create mode 100644 llvm/test/Transforms/InstCombine/interference-tests-for-high-bit-check.ll diff --git a/llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll b/llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll new file mode 100644 index 000000000000..530cab60bdfa --- /dev/null +++ b/llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll @@ -0,0 +1,240 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -instcombine -S | FileCheck %s + +; https://bugs.llvm.org/show_bug.cgi?id=38708 + +; Pattern: +; ~(-1 << bits) u>= val +; Should be transformed into: +; (val l>> bits) == 0 + +; ============================================================================ ; +; Basic positive tests +; ============================================================================ ; + +define i1 @p0(i8 %val, i8 %bits) { +; CHECK-LABEL: @p0( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + %t1 = xor i8 %t0, -1 + %r = icmp uge i8 %t1, %val + ret i1 %r +} + +; ============================================================================ ; +; Vector tests +; ============================================================================ ; + +define <2 x i1> @p1_vec(<2 x i8> %val, <2 x i8> %bits) { +; CHECK-LABEL: @p1_vec( +; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor <2 x i8> [[T0]], +; CHECK-NEXT: [[R:%.*]] = icmp uge <2 x i8> [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %t0 = shl <2 x i8> , %bits + %t1 = xor <2 x i8> %t0, + %r = icmp uge <2 x i8> %t1, %val + ret <2 x i1> %r +} + +define <3 x i1> @p2_vec_undef0(<3 x i8> %val, <3 x i8> %bits) { +; CHECK-LABEL: @p2_vec_undef0( +; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor <3 x i8> [[T0]], +; CHECK-NEXT: [[R:%.*]] = icmp uge <3 x i8> [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret <3 x i1> [[R]] +; + %t0 = shl <3 x i8> , %bits + %t1 = xor <3 x i8> %t0, + %r = icmp uge <3 x i8> %t1, %val + ret <3 x i1> %r +} + +define <3 x i1> @p2_vec_undef1(<3 x i8> %val, <3 x i8> %bits) { +; CHECK-LABEL: @p2_vec_undef1( +; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor <3 x i8> [[T0]], +; CHECK-NEXT: [[R:%.*]] = icmp uge <3 x i8> [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret <3 x i1> [[R]] +; + %t0 = shl <3 x i8> , %bits + %t1 = xor <3 x i8> %t0, + %r = icmp uge <3 x i8> %t1, %val + ret <3 x i1> %r +} + +define <3 x i1> @p2_vec_undef2(<3 x i8> %val, <3 x i8> %bits) { +; CHECK-LABEL: @p2_vec_undef2( +; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor <3 x i8> [[T0]], +; CHECK-NEXT: [[R:%.*]] = icmp uge <3 x i8> [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret <3 x i1> [[R]] +; + %t0 = shl <3 x i8> , %bits + %t1 = xor <3 x i8> %t0, + %r = icmp uge <3 x i8> %t1, %val + ret <3 x i1> %r +} + +; ============================================================================ ; +; Commutativity tests. +; ============================================================================ ; + +declare i8 @gen8() + +define i1 @c0(i8 %bits) { +; CHECK-LABEL: @c0( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8() +; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[VAL]], [[T1]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + %t1 = xor i8 %t0, -1 + %val = call i8 @gen8() + %r = icmp ule i8 %val, %t1 ; swapped order and predicate + ret i1 %r +} + +; ============================================================================ ; +; One-use tests. +; ============================================================================ ; + +declare void @use8(i8) + +define i1 @oneuse0(i8 %val, i8 %bits) { +; CHECK-LABEL: @oneuse0( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: call void @use8(i8 [[T0]]) +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + call void @use8(i8 %t0) + %t1 = xor i8 %t0, -1 + %r = icmp uge i8 %t1, %val + ret i1 %r +} + +define i1 @oneuse1(i8 %val, i8 %bits) { +; CHECK-LABEL: @oneuse1( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: call void @use8(i8 [[T1]]) +; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + %t1 = xor i8 %t0, -1 + call void @use8(i8 %t1) + %r = icmp uge i8 %t1, %val + ret i1 %r +} + +define i1 @oneuse2(i8 %val, i8 %bits) { +; CHECK-LABEL: @oneuse2( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: call void @use8(i8 [[T0]]) +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: call void @use8(i8 [[T1]]) +; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + call void @use8(i8 %t0) + %t1 = xor i8 %t0, -1 + call void @use8(i8 %t1) + %r = icmp uge i8 %t1, %val + ret i1 %r +} + +; ============================================================================ ; +; Negative tests +; ============================================================================ ; + +define i1 @n0(i8 %val, i8 %bits) { +; CHECK-LABEL: @n0( +; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 1, %bits ; constant is not -1 + %t1 = xor i8 %t0, -1 + %r = icmp uge i8 %t1, %val + ret i1 %r +} + +define i1 @n1(i8 %val, i8 %bits) { +; CHECK-LABEL: @n1( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], 1 +; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + %t1 = xor i8 %t0, 1 ; not 'not' + %r = icmp uge i8 %t1, %val + ret i1 %r +} + +define <2 x i1> @n2_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) { +; CHECK-LABEL: @n2_vec_nonsplat( +; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor <2 x i8> [[T0]], +; CHECK-NEXT: [[R:%.*]] = icmp uge <2 x i8> [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %t0 = shl <2 x i8> , %bits ; again, wrong constant + %t1 = xor <2 x i8> %t0, + %r = icmp uge <2 x i8> %t1, %val + ret <2 x i1> %r +} + +define <2 x i1> @n3_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) { +; CHECK-LABEL: @n3_vec_nonsplat( +; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor <2 x i8> [[T0]], +; CHECK-NEXT: [[R:%.*]] = icmp uge <2 x i8> [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %t0 = shl <2 x i8> , %bits + %t1 = xor <2 x i8> %t0, ; again, wrong constant + %r = icmp uge <2 x i8> %t1, %val + ret <2 x i1> %r +} + +define i1 @n3(i8 %val, i8 %bits) { +; CHECK-LABEL: @n3( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + %t1 = xor i8 %t0, -1 + %r = icmp ugt i8 %t1, %val ; wrong predicate + ret i1 %r +} + +define i1 @n4(i8 %bits) { +; CHECK-LABEL: @n4( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8() +; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[VAL]], [[T1]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + %t1 = xor i8 %t0, -1 + %val = call i8 @gen8() + %r = icmp ult i8 %val, %t1 ; swapped order and [wrong] predicate + ret i1 %r +} diff --git a/llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll b/llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll new file mode 100644 index 000000000000..d6d7cce9ffa8 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll @@ -0,0 +1,240 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -instcombine -S | FileCheck %s + +; https://bugs.llvm.org/show_bug.cgi?id=38708 + +; Pattern: +; ~(-1 << bits) u< val +; Should be transformed into: +; (val l>> bits) != 0 + +; ============================================================================ ; +; Basic positive tests +; ============================================================================ ; + +define i1 @p0(i8 %val, i8 %bits) { +; CHECK-LABEL: @p0( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + %t1 = xor i8 %t0, -1 + %r = icmp ult i8 %t1, %val + ret i1 %r +} + +; ============================================================================ ; +; Vector tests +; ============================================================================ ; + +define <2 x i1> @p1_vec(<2 x i8> %val, <2 x i8> %bits) { +; CHECK-LABEL: @p1_vec( +; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor <2 x i8> [[T0]], +; CHECK-NEXT: [[R:%.*]] = icmp ult <2 x i8> [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %t0 = shl <2 x i8> , %bits + %t1 = xor <2 x i8> %t0, + %r = icmp ult <2 x i8> %t1, %val + ret <2 x i1> %r +} + +define <3 x i1> @p2_vec_undef0(<3 x i8> %val, <3 x i8> %bits) { +; CHECK-LABEL: @p2_vec_undef0( +; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor <3 x i8> [[T0]], +; CHECK-NEXT: [[R:%.*]] = icmp ult <3 x i8> [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret <3 x i1> [[R]] +; + %t0 = shl <3 x i8> , %bits + %t1 = xor <3 x i8> %t0, + %r = icmp ult <3 x i8> %t1, %val + ret <3 x i1> %r +} + +define <3 x i1> @p2_vec_undef1(<3 x i8> %val, <3 x i8> %bits) { +; CHECK-LABEL: @p2_vec_undef1( +; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor <3 x i8> [[T0]], +; CHECK-NEXT: [[R:%.*]] = icmp ult <3 x i8> [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret <3 x i1> [[R]] +; + %t0 = shl <3 x i8> , %bits + %t1 = xor <3 x i8> %t0, + %r = icmp ult <3 x i8> %t1, %val + ret <3 x i1> %r +} + +define <3 x i1> @p2_vec_undef2(<3 x i8> %val, <3 x i8> %bits) { +; CHECK-LABEL: @p2_vec_undef2( +; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor <3 x i8> [[T0]], +; CHECK-NEXT: [[R:%.*]] = icmp ult <3 x i8> [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret <3 x i1> [[R]] +; + %t0 = shl <3 x i8> , %bits + %t1 = xor <3 x i8> %t0, + %r = icmp ult <3 x i8> %t1, %val + ret <3 x i1> %r +} + +; ============================================================================ ; +; Commutativity tests. +; ============================================================================ ; + +declare i8 @gen8() + +define i1 @c0(i8 %bits) { +; CHECK-LABEL: @c0( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8() +; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[VAL]], [[T1]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + %t1 = xor i8 %t0, -1 + %val = call i8 @gen8() + %r = icmp ugt i8 %val, %t1 ; swapped order and predicate + ret i1 %r +} + +; ============================================================================ ; +; One-use tests. +; ============================================================================ ; + +declare void @use8(i8) + +define i1 @oneuse0(i8 %val, i8 %bits) { +; CHECK-LABEL: @oneuse0( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: call void @use8(i8 [[T0]]) +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + call void @use8(i8 %t0) + %t1 = xor i8 %t0, -1 + %r = icmp ult i8 %t1, %val + ret i1 %r +} + +define i1 @oneuse1(i8 %val, i8 %bits) { +; CHECK-LABEL: @oneuse1( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: call void @use8(i8 [[T1]]) +; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + %t1 = xor i8 %t0, -1 + call void @use8(i8 %t1) + %r = icmp ult i8 %t1, %val + ret i1 %r +} + +define i1 @oneuse2(i8 %val, i8 %bits) { +; CHECK-LABEL: @oneuse2( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: call void @use8(i8 [[T0]]) +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: call void @use8(i8 [[T1]]) +; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + call void @use8(i8 %t0) + %t1 = xor i8 %t0, -1 + call void @use8(i8 %t1) + %r = icmp ult i8 %t1, %val + ret i1 %r +} + +; ============================================================================ ; +; Negative tests +; ============================================================================ ; + +define i1 @n0(i8 %val, i8 %bits) { +; CHECK-LABEL: @n0( +; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 1, %bits ; constant is not -1 + %t1 = xor i8 %t0, -1 + %r = icmp ult i8 %t1, %val + ret i1 %r +} + +define i1 @n1(i8 %val, i8 %bits) { +; CHECK-LABEL: @n1( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], 1 +; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + %t1 = xor i8 %t0, 1 ; not 'not' + %r = icmp ult i8 %t1, %val + ret i1 %r +} + +define <2 x i1> @n2_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) { +; CHECK-LABEL: @n2_vec_nonsplat( +; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor <2 x i8> [[T0]], +; CHECK-NEXT: [[R:%.*]] = icmp ult <2 x i8> [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %t0 = shl <2 x i8> , %bits ; again, wrong constant + %t1 = xor <2 x i8> %t0, + %r = icmp ult <2 x i8> %t1, %val + ret <2 x i1> %r +} + +define <2 x i1> @n3_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) { +; CHECK-LABEL: @n3_vec_nonsplat( +; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor <2 x i8> [[T0]], +; CHECK-NEXT: [[R:%.*]] = icmp ult <2 x i8> [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %t0 = shl <2 x i8> , %bits + %t1 = xor <2 x i8> %t0, ; again, wrong constant + %r = icmp ult <2 x i8> %t1, %val + ret <2 x i1> %r +} + +define i1 @n3(i8 %val, i8 %bits) { +; CHECK-LABEL: @n3( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[T1]], [[VAL:%.*]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + %t1 = xor i8 %t0, -1 + %r = icmp ule i8 %t1, %val ; wrong predicate + ret i1 %r +} + +define i1 @n4(i8 %bits) { +; CHECK-LABEL: @n4( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8() +; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[VAL]], [[T1]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits + %t1 = xor i8 %t0, -1 + %val = call i8 @gen8() + %r = icmp uge i8 %val, %t1 ; swapped order and [wrong] predicate + ret i1 %r +} diff --git a/llvm/test/Transforms/InstCombine/interference-tests-for-high-bit-check.ll b/llvm/test/Transforms/InstCombine/interference-tests-for-high-bit-check.ll new file mode 100644 index 000000000000..c3de610ee8f6 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/interference-tests-for-high-bit-check.ll @@ -0,0 +1,141 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -instcombine -S | FileCheck %s + +; https://bugs.llvm.org/show_bug.cgi?id=38708 + +; ============================================================================ ; +; Interference tests. +; We might accidentally skip some of these, if we are not careful. +; ============================================================================ ; + +declare i8 @gen8() + +define i1 @interference0(i8 %bits0, i8 %bits1) { +; CHECK-LABEL: @interference0( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[T1_HIGHBITS:%.*]] = lshr i8 [[T1]], [[BITS1:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[T1_HIGHBITS]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits0 + %t1 = xor i8 %t0, -1 + %t2 = shl i8 1, %bits1 + %r = icmp ult i8 %t1, %t2 + ret i1 %r +} + +define i1 @interference1(i8 %bits0, i8 %bits1) { +; CHECK-LABEL: @interference1( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[T2:%.*]] = shl i8 1, [[BITS1:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T2]], [[T1]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits0 + %t1 = xor i8 %t0, -1 + %t2 = shl i8 1, %bits1 + %r = icmp ule i8 %t1, %t2 + ret i1 %r +} + +define i1 @interference2(i8 %bits0, i8 %bits1) { +; CHECK-LABEL: @interference2( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[T2:%.*]] = shl i8 1, [[BITS1:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T2]], [[T1]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits0 + %t1 = xor i8 %t0, -1 + %t2 = shl i8 1, %bits1 + %r = icmp ugt i8 %t1, %t2 + ret i1 %r +} + +define i1 @interference3(i8 %bits0, i8 %bits1) { +; CHECK-LABEL: @interference3( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[T1_HIGHBITS:%.*]] = lshr i8 [[T1]], [[BITS1:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[T1_HIGHBITS]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits0 + %t1 = xor i8 %t0, -1 + %t2 = shl i8 1, %bits1 + %r = icmp uge i8 %t1, %t2 + ret i1 %r +} + + + +define i1 @commuted_interference0(i8 %bits0) { +; CHECK-LABEL: @commuted_interference0( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[BITS1:%.*]] = call i8 @gen8() +; CHECK-NEXT: [[T1_HIGHBITS:%.*]] = lshr i8 [[T1]], [[BITS1]] +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[T1_HIGHBITS]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits0 + %t1 = xor i8 %t0, -1 + %bits1 = call i8 @gen8() + %t2 = shl i8 1, %bits1 + %r = icmp ult i8 %t1, %t2 + ret i1 %r +} + +define i1 @commuted_interference1(i8 %bits0) { +; CHECK-LABEL: @commuted_interference1( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[BITS1:%.*]] = call i8 @gen8() +; CHECK-NEXT: [[T2:%.*]] = shl i8 1, [[BITS1]] +; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T2]], [[T1]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits0 + %t1 = xor i8 %t0, -1 + %bits1 = call i8 @gen8() + %t2 = shl i8 1, %bits1 + %r = icmp ule i8 %t1, %t2 + ret i1 %r +} + +define i1 @commuted_interference2(i8 %bits0) { +; CHECK-LABEL: @commuted_interference2( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[BITS1:%.*]] = call i8 @gen8() +; CHECK-NEXT: [[T2:%.*]] = shl i8 1, [[BITS1]] +; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T2]], [[T1]] +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits0 + %t1 = xor i8 %t0, -1 + %bits1 = call i8 @gen8() + %t2 = shl i8 1, %bits1 + %r = icmp ugt i8 %t1, %t2 + ret i1 %r +} + +define i1 @commuted_interference3(i8 %bits0) { +; CHECK-LABEL: @commuted_interference3( +; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 +; CHECK-NEXT: [[BITS1:%.*]] = call i8 @gen8() +; CHECK-NEXT: [[T1_HIGHBITS:%.*]] = lshr i8 [[T1]], [[BITS1]] +; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[T1_HIGHBITS]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %t0 = shl i8 -1, %bits0 + %t1 = xor i8 %t0, -1 + %bits1 = call i8 @gen8() + %t2 = shl i8 1, %bits1 + %r = icmp uge i8 %t1, %t2 + ret i1 %r +}