forked from OSchip/llvm-project
[NFC][InstCombine] R38708 - inefficient pattern for high-bits checking.
More complicated, canonical pattern: https://rise4fun.com/Alive/uhA https://godbolt.org/z/o4RB8D Also, we need to be careful not to skip some patters... https://bugs.llvm.org/show_bug.cgi?id=38708 llvm-svn: 342074
This commit is contained in:
Roman Lebedev
parent
f56972e224
commit
91c668a276
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; https://bugs.llvm.org/show_bug.cgi?id=38708
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; Pattern:
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; ~(-1 << bits) u>= val
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; Should be transformed into:
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; (val l>> bits) == 0
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; ============================================================================ ;
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; Basic positive tests
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; ============================================================================ ;
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define i1 @p0(i8 %val, i8 %bits) {
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; CHECK-LABEL: @p0(
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; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
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; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret i1 [[R]]
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;
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%t0 = shl i8 -1, %bits
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%t1 = xor i8 %t0, -1
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%r = icmp uge i8 %t1, %val
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ret i1 %r
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}
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; ============================================================================ ;
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; Vector tests
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; ============================================================================ ;
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define <2 x i1> @p1_vec(<2 x i8> %val, <2 x i8> %bits) {
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; CHECK-LABEL: @p1_vec(
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; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> <i8 -1, i8 -1>, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor <2 x i8> [[T0]], <i8 -1, i8 -1>
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; CHECK-NEXT: [[R:%.*]] = icmp uge <2 x i8> [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret <2 x i1> [[R]]
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;
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%t0 = shl <2 x i8> <i8 -1, i8 -1>, %bits
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%t1 = xor <2 x i8> %t0, <i8 -1, i8 -1>
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%r = icmp uge <2 x i8> %t1, %val
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ret <2 x i1> %r
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}
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define <3 x i1> @p2_vec_undef0(<3 x i8> %val, <3 x i8> %bits) {
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; CHECK-LABEL: @p2_vec_undef0(
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; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor <3 x i8> [[T0]], <i8 -1, i8 -1, i8 -1>
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; CHECK-NEXT: [[R:%.*]] = icmp uge <3 x i8> [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret <3 x i1> [[R]]
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;
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%t0 = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, %bits
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%t1 = xor <3 x i8> %t0, <i8 -1, i8 -1, i8 -1>
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%r = icmp uge <3 x i8> %t1, %val
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ret <3 x i1> %r
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}
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define <3 x i1> @p2_vec_undef1(<3 x i8> %val, <3 x i8> %bits) {
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; CHECK-LABEL: @p2_vec_undef1(
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; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> <i8 -1, i8 -1, i8 -1>, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor <3 x i8> [[T0]], <i8 -1, i8 undef, i8 -1>
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; CHECK-NEXT: [[R:%.*]] = icmp uge <3 x i8> [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret <3 x i1> [[R]]
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;
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%t0 = shl <3 x i8> <i8 -1, i8 -1, i8 -1>, %bits
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%t1 = xor <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
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%r = icmp uge <3 x i8> %t1, %val
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ret <3 x i1> %r
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}
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define <3 x i1> @p2_vec_undef2(<3 x i8> %val, <3 x i8> %bits) {
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; CHECK-LABEL: @p2_vec_undef2(
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; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor <3 x i8> [[T0]], <i8 -1, i8 undef, i8 -1>
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; CHECK-NEXT: [[R:%.*]] = icmp uge <3 x i8> [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret <3 x i1> [[R]]
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;
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%t0 = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, %bits
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%t1 = xor <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
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%r = icmp uge <3 x i8> %t1, %val
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ret <3 x i1> %r
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}
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; ============================================================================ ;
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; Commutativity tests.
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; ============================================================================ ;
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declare i8 @gen8()
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define i1 @c0(i8 %bits) {
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; CHECK-LABEL: @c0(
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; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
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; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8()
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; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[VAL]], [[T1]]
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; CHECK-NEXT: ret i1 [[R]]
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;
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%t0 = shl i8 -1, %bits
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%t1 = xor i8 %t0, -1
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%val = call i8 @gen8()
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%r = icmp ule i8 %val, %t1 ; swapped order and predicate
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ret i1 %r
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}
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; ============================================================================ ;
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; One-use tests.
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; ============================================================================ ;
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declare void @use8(i8)
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define i1 @oneuse0(i8 %val, i8 %bits) {
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; CHECK-LABEL: @oneuse0(
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; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
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; CHECK-NEXT: call void @use8(i8 [[T0]])
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; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
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; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret i1 [[R]]
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;
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%t0 = shl i8 -1, %bits
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call void @use8(i8 %t0)
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%t1 = xor i8 %t0, -1
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%r = icmp uge i8 %t1, %val
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ret i1 %r
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}
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define i1 @oneuse1(i8 %val, i8 %bits) {
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; CHECK-LABEL: @oneuse1(
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; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
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; CHECK-NEXT: call void @use8(i8 [[T1]])
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; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret i1 [[R]]
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;
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%t0 = shl i8 -1, %bits
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%t1 = xor i8 %t0, -1
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call void @use8(i8 %t1)
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%r = icmp uge i8 %t1, %val
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ret i1 %r
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}
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define i1 @oneuse2(i8 %val, i8 %bits) {
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; CHECK-LABEL: @oneuse2(
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; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
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; CHECK-NEXT: call void @use8(i8 [[T0]])
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; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
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; CHECK-NEXT: call void @use8(i8 [[T1]])
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; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret i1 [[R]]
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;
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%t0 = shl i8 -1, %bits
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call void @use8(i8 %t0)
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%t1 = xor i8 %t0, -1
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call void @use8(i8 %t1)
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%r = icmp uge i8 %t1, %val
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ret i1 %r
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}
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; ============================================================================ ;
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; Negative tests
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; ============================================================================ ;
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define i1 @n0(i8 %val, i8 %bits) {
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; CHECK-LABEL: @n0(
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; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
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; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret i1 [[R]]
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;
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%t0 = shl i8 1, %bits ; constant is not -1
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%t1 = xor i8 %t0, -1
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%r = icmp uge i8 %t1, %val
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ret i1 %r
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}
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define i1 @n1(i8 %val, i8 %bits) {
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; CHECK-LABEL: @n1(
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; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], 1
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; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret i1 [[R]]
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;
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%t0 = shl i8 -1, %bits
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%t1 = xor i8 %t0, 1 ; not 'not'
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%r = icmp uge i8 %t1, %val
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ret i1 %r
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}
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define <2 x i1> @n2_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) {
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; CHECK-LABEL: @n2_vec_nonsplat(
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; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> <i8 -1, i8 1>, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor <2 x i8> [[T0]], <i8 -1, i8 -1>
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; CHECK-NEXT: [[R:%.*]] = icmp uge <2 x i8> [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret <2 x i1> [[R]]
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;
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%t0 = shl <2 x i8> <i8 -1, i8 1>, %bits ; again, wrong constant
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%t1 = xor <2 x i8> %t0, <i8 -1, i8 -1>
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%r = icmp uge <2 x i8> %t1, %val
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ret <2 x i1> %r
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}
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define <2 x i1> @n3_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) {
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; CHECK-LABEL: @n3_vec_nonsplat(
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; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> <i8 -1, i8 -1>, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor <2 x i8> [[T0]], <i8 -1, i8 1>
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; CHECK-NEXT: [[R:%.*]] = icmp uge <2 x i8> [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret <2 x i1> [[R]]
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;
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%t0 = shl <2 x i8> <i8 -1, i8 -1>, %bits
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%t1 = xor <2 x i8> %t0, <i8 -1, i8 1> ; again, wrong constant
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%r = icmp uge <2 x i8> %t1, %val
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ret <2 x i1> %r
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}
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define i1 @n3(i8 %val, i8 %bits) {
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; CHECK-LABEL: @n3(
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; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
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; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret i1 [[R]]
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;
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%t0 = shl i8 -1, %bits
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%t1 = xor i8 %t0, -1
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%r = icmp ugt i8 %t1, %val ; wrong predicate
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ret i1 %r
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}
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define i1 @n4(i8 %bits) {
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; CHECK-LABEL: @n4(
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; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
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; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8()
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; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[VAL]], [[T1]]
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; CHECK-NEXT: ret i1 [[R]]
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;
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%t0 = shl i8 -1, %bits
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%t1 = xor i8 %t0, -1
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%val = call i8 @gen8()
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%r = icmp ult i8 %val, %t1 ; swapped order and [wrong] predicate
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ret i1 %r
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}
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@ -0,0 +1,240 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; https://bugs.llvm.org/show_bug.cgi?id=38708
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; Pattern:
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; ~(-1 << bits) u< val
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; Should be transformed into:
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; (val l>> bits) != 0
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; ============================================================================ ;
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; Basic positive tests
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; ============================================================================ ;
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define i1 @p0(i8 %val, i8 %bits) {
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; CHECK-LABEL: @p0(
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; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
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; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret i1 [[R]]
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;
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%t0 = shl i8 -1, %bits
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%t1 = xor i8 %t0, -1
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%r = icmp ult i8 %t1, %val
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ret i1 %r
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}
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; ============================================================================ ;
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; Vector tests
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; ============================================================================ ;
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define <2 x i1> @p1_vec(<2 x i8> %val, <2 x i8> %bits) {
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; CHECK-LABEL: @p1_vec(
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; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> <i8 -1, i8 -1>, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor <2 x i8> [[T0]], <i8 -1, i8 -1>
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; CHECK-NEXT: [[R:%.*]] = icmp ult <2 x i8> [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret <2 x i1> [[R]]
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;
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%t0 = shl <2 x i8> <i8 -1, i8 -1>, %bits
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%t1 = xor <2 x i8> %t0, <i8 -1, i8 -1>
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%r = icmp ult <2 x i8> %t1, %val
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ret <2 x i1> %r
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}
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define <3 x i1> @p2_vec_undef0(<3 x i8> %val, <3 x i8> %bits) {
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; CHECK-LABEL: @p2_vec_undef0(
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; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor <3 x i8> [[T0]], <i8 -1, i8 -1, i8 -1>
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; CHECK-NEXT: [[R:%.*]] = icmp ult <3 x i8> [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret <3 x i1> [[R]]
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;
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%t0 = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, %bits
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%t1 = xor <3 x i8> %t0, <i8 -1, i8 -1, i8 -1>
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%r = icmp ult <3 x i8> %t1, %val
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ret <3 x i1> %r
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}
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define <3 x i1> @p2_vec_undef1(<3 x i8> %val, <3 x i8> %bits) {
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; CHECK-LABEL: @p2_vec_undef1(
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; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> <i8 -1, i8 -1, i8 -1>, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor <3 x i8> [[T0]], <i8 -1, i8 undef, i8 -1>
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; CHECK-NEXT: [[R:%.*]] = icmp ult <3 x i8> [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret <3 x i1> [[R]]
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;
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%t0 = shl <3 x i8> <i8 -1, i8 -1, i8 -1>, %bits
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%t1 = xor <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
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%r = icmp ult <3 x i8> %t1, %val
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ret <3 x i1> %r
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}
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define <3 x i1> @p2_vec_undef2(<3 x i8> %val, <3 x i8> %bits) {
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; CHECK-LABEL: @p2_vec_undef2(
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; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor <3 x i8> [[T0]], <i8 -1, i8 undef, i8 -1>
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; CHECK-NEXT: [[R:%.*]] = icmp ult <3 x i8> [[T1]], [[VAL:%.*]]
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; CHECK-NEXT: ret <3 x i1> [[R]]
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;
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%t0 = shl <3 x i8> <i8 -1, i8 undef, i8 -1>, %bits
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%t1 = xor <3 x i8> %t0, <i8 -1, i8 undef, i8 -1>
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%r = icmp ult <3 x i8> %t1, %val
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ret <3 x i1> %r
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}
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; ============================================================================ ;
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; Commutativity tests.
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; ============================================================================ ;
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declare i8 @gen8()
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define i1 @c0(i8 %bits) {
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; CHECK-LABEL: @c0(
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; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
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; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8()
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; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[VAL]], [[T1]]
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; CHECK-NEXT: ret i1 [[R]]
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;
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%t0 = shl i8 -1, %bits
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%t1 = xor i8 %t0, -1
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%val = call i8 @gen8()
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%r = icmp ugt i8 %val, %t1 ; swapped order and predicate
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ret i1 %r
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}
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; ============================================================================ ;
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; One-use tests.
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; ============================================================================ ;
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declare void @use8(i8)
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define i1 @oneuse0(i8 %val, i8 %bits) {
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; CHECK-LABEL: @oneuse0(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
|
||||
; CHECK-NEXT: call void @use8(i8 [[T0]])
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]]
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits
|
||||
call void @use8(i8 %t0)
|
||||
%t1 = xor i8 %t0, -1
|
||||
%r = icmp ult i8 %t1, %val
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define i1 @oneuse1(i8 %val, i8 %bits) {
|
||||
; CHECK-LABEL: @oneuse1(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: call void @use8(i8 [[T1]])
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]]
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits
|
||||
%t1 = xor i8 %t0, -1
|
||||
call void @use8(i8 %t1)
|
||||
%r = icmp ult i8 %t1, %val
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define i1 @oneuse2(i8 %val, i8 %bits) {
|
||||
; CHECK-LABEL: @oneuse2(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
|
||||
; CHECK-NEXT: call void @use8(i8 [[T0]])
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: call void @use8(i8 [[T1]])
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]]
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits
|
||||
call void @use8(i8 %t0)
|
||||
%t1 = xor i8 %t0, -1
|
||||
call void @use8(i8 %t1)
|
||||
%r = icmp ult i8 %t1, %val
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
; ============================================================================ ;
|
||||
; Negative tests
|
||||
; ============================================================================ ;
|
||||
|
||||
define i1 @n0(i8 %val, i8 %bits) {
|
||||
; CHECK-LABEL: @n0(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]]
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 1, %bits ; constant is not -1
|
||||
%t1 = xor i8 %t0, -1
|
||||
%r = icmp ult i8 %t1, %val
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define i1 @n1(i8 %val, i8 %bits) {
|
||||
; CHECK-LABEL: @n1(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], 1
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]]
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits
|
||||
%t1 = xor i8 %t0, 1 ; not 'not'
|
||||
%r = icmp ult i8 %t1, %val
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define <2 x i1> @n2_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) {
|
||||
; CHECK-LABEL: @n2_vec_nonsplat(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> <i8 -1, i8 1>, [[BITS:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor <2 x i8> [[T0]], <i8 -1, i8 -1>
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp ult <2 x i8> [[T1]], [[VAL:%.*]]
|
||||
; CHECK-NEXT: ret <2 x i1> [[R]]
|
||||
;
|
||||
%t0 = shl <2 x i8> <i8 -1, i8 1>, %bits ; again, wrong constant
|
||||
%t1 = xor <2 x i8> %t0, <i8 -1, i8 -1>
|
||||
%r = icmp ult <2 x i8> %t1, %val
|
||||
ret <2 x i1> %r
|
||||
}
|
||||
|
||||
define <2 x i1> @n3_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) {
|
||||
; CHECK-LABEL: @n3_vec_nonsplat(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> <i8 -1, i8 -1>, [[BITS:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor <2 x i8> [[T0]], <i8 -1, i8 1>
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp ult <2 x i8> [[T1]], [[VAL:%.*]]
|
||||
; CHECK-NEXT: ret <2 x i1> [[R]]
|
||||
;
|
||||
%t0 = shl <2 x i8> <i8 -1, i8 -1>, %bits
|
||||
%t1 = xor <2 x i8> %t0, <i8 -1, i8 1> ; again, wrong constant
|
||||
%r = icmp ult <2 x i8> %t1, %val
|
||||
ret <2 x i1> %r
|
||||
}
|
||||
|
||||
define i1 @n3(i8 %val, i8 %bits) {
|
||||
; CHECK-LABEL: @n3(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[T1]], [[VAL:%.*]]
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits
|
||||
%t1 = xor i8 %t0, -1
|
||||
%r = icmp ule i8 %t1, %val ; wrong predicate
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define i1 @n4(i8 %bits) {
|
||||
; CHECK-LABEL: @n4(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8()
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[VAL]], [[T1]]
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits
|
||||
%t1 = xor i8 %t0, -1
|
||||
%val = call i8 @gen8()
|
||||
%r = icmp uge i8 %val, %t1 ; swapped order and [wrong] predicate
|
||||
ret i1 %r
|
||||
}
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
|
||||
; RUN: opt < %s -instcombine -S | FileCheck %s
|
||||
|
||||
; https://bugs.llvm.org/show_bug.cgi?id=38708
|
||||
|
||||
; ============================================================================ ;
|
||||
; Interference tests.
|
||||
; We might accidentally skip some of these, if we are not careful.
|
||||
; ============================================================================ ;
|
||||
|
||||
declare i8 @gen8()
|
||||
|
||||
define i1 @interference0(i8 %bits0, i8 %bits1) {
|
||||
; CHECK-LABEL: @interference0(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: [[T1_HIGHBITS:%.*]] = lshr i8 [[T1]], [[BITS1:%.*]]
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[T1_HIGHBITS]], 0
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits0
|
||||
%t1 = xor i8 %t0, -1
|
||||
%t2 = shl i8 1, %bits1
|
||||
%r = icmp ult i8 %t1, %t2
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define i1 @interference1(i8 %bits0, i8 %bits1) {
|
||||
; CHECK-LABEL: @interference1(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: [[T2:%.*]] = shl i8 1, [[BITS1:%.*]]
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T2]], [[T1]]
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits0
|
||||
%t1 = xor i8 %t0, -1
|
||||
%t2 = shl i8 1, %bits1
|
||||
%r = icmp ule i8 %t1, %t2
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define i1 @interference2(i8 %bits0, i8 %bits1) {
|
||||
; CHECK-LABEL: @interference2(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: [[T2:%.*]] = shl i8 1, [[BITS1:%.*]]
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T2]], [[T1]]
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits0
|
||||
%t1 = xor i8 %t0, -1
|
||||
%t2 = shl i8 1, %bits1
|
||||
%r = icmp ugt i8 %t1, %t2
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define i1 @interference3(i8 %bits0, i8 %bits1) {
|
||||
; CHECK-LABEL: @interference3(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: [[T1_HIGHBITS:%.*]] = lshr i8 [[T1]], [[BITS1:%.*]]
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[T1_HIGHBITS]], 0
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits0
|
||||
%t1 = xor i8 %t0, -1
|
||||
%t2 = shl i8 1, %bits1
|
||||
%r = icmp uge i8 %t1, %t2
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
|
||||
|
||||
define i1 @commuted_interference0(i8 %bits0) {
|
||||
; CHECK-LABEL: @commuted_interference0(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: [[BITS1:%.*]] = call i8 @gen8()
|
||||
; CHECK-NEXT: [[T1_HIGHBITS:%.*]] = lshr i8 [[T1]], [[BITS1]]
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[T1_HIGHBITS]], 0
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits0
|
||||
%t1 = xor i8 %t0, -1
|
||||
%bits1 = call i8 @gen8()
|
||||
%t2 = shl i8 1, %bits1
|
||||
%r = icmp ult i8 %t1, %t2
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define i1 @commuted_interference1(i8 %bits0) {
|
||||
; CHECK-LABEL: @commuted_interference1(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: [[BITS1:%.*]] = call i8 @gen8()
|
||||
; CHECK-NEXT: [[T2:%.*]] = shl i8 1, [[BITS1]]
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T2]], [[T1]]
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits0
|
||||
%t1 = xor i8 %t0, -1
|
||||
%bits1 = call i8 @gen8()
|
||||
%t2 = shl i8 1, %bits1
|
||||
%r = icmp ule i8 %t1, %t2
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define i1 @commuted_interference2(i8 %bits0) {
|
||||
; CHECK-LABEL: @commuted_interference2(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: [[BITS1:%.*]] = call i8 @gen8()
|
||||
; CHECK-NEXT: [[T2:%.*]] = shl i8 1, [[BITS1]]
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T2]], [[T1]]
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits0
|
||||
%t1 = xor i8 %t0, -1
|
||||
%bits1 = call i8 @gen8()
|
||||
%t2 = shl i8 1, %bits1
|
||||
%r = icmp ugt i8 %t1, %t2
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define i1 @commuted_interference3(i8 %bits0) {
|
||||
; CHECK-LABEL: @commuted_interference3(
|
||||
; CHECK-NEXT: [[T0:%.*]] = shl i8 -1, [[BITS0:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1
|
||||
; CHECK-NEXT: [[BITS1:%.*]] = call i8 @gen8()
|
||||
; CHECK-NEXT: [[T1_HIGHBITS:%.*]] = lshr i8 [[T1]], [[BITS1]]
|
||||
; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[T1_HIGHBITS]], 0
|
||||
; CHECK-NEXT: ret i1 [[R]]
|
||||
;
|
||||
%t0 = shl i8 -1, %bits0
|
||||
%t1 = xor i8 %t0, -1
|
||||
%bits1 = call i8 @gen8()
|
||||
%t2 = shl i8 1, %bits1
|
||||
%r = icmp uge i8 %t1, %t2
|
||||
ret i1 %r
|
||||
}
|
||||
Loading…
Reference in New Issue