forked from OSchip/llvm-project
[VE][NFC] re-write RR* isel class using null_frag
Summary: Re-write RR* using null_frag to avoid duplication in upcoming patches. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73259
This commit is contained in:
Simon Moll
parent
98ea4b30c2
commit
9187073f3e
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@ -225,7 +225,9 @@ def CC_AT : CC_VAL<21>; // Always true
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//===----------------------------------------------------------------------===//
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multiclass RMm<string opcStr, bits<8>opc,
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RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> {
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RegisterClass RC, ValueType Ty,
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Operand immOp, Operand immOp2,
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SDPatternOperator OpNode=null_frag> {
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def rri : RM<
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opc, (outs RC:$sx), (ins RC:$sy, RC:$sz, immOp2:$imm32),
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!strconcat(opcStr, " $sx, ${imm32}($sy, ${sz})")> {
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@ -235,7 +237,8 @@ multiclass RMm<string opcStr, bits<8>opc,
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}
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def rzi : RM<
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opc, (outs RC:$sx), (ins RC:$sz, immOp2:$imm32),
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!strconcat(opcStr, " $sx, ${imm32}(${sz})")> {
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!strconcat(opcStr, " $sx, ${imm32}(${sz})"),
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[(set Ty:$sx, (OpNode Ty:$sz, (Ty simm32:$imm32)))]> {
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let cy = 0;
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let sy = 0;
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let cz = 1;
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@ -254,26 +257,20 @@ multiclass RMm<string opcStr, bits<8>opc,
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// Multiclass for RR type instructions
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multiclass RRmrr<string opcStr, bits<8>opc, SDNode OpNode,
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multiclass RRmrr<string opcStr, bits<8>opc,
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RegisterClass RCo, ValueType Tyo,
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RegisterClass RCi, ValueType Tyi> {
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RegisterClass RCi, ValueType Tyi,
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SDPatternOperator OpNode=null_frag> {
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def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz),
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!strconcat(opcStr, " $sx, $sy, $sz"),
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[(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>
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{ let cy = 1; let cz = 1; let hasSideEffects = 0; }
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}
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multiclass RRNDmrr<string opcStr, bits<8>opc,
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multiclass RRmri<string opcStr, bits<8>opc,
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RegisterClass RCo, ValueType Tyo,
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RegisterClass RCi, ValueType Tyi> {
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def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz),
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!strconcat(opcStr, " $sx, $sy, $sz")>
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{ let cy = 1; let cz = 1; let hasSideEffects = 0; }
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}
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multiclass RRmri<string opcStr, bits<8>opc, SDNode OpNode,
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RegisterClass RCo, ValueType Tyo,
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RegisterClass RCi, ValueType Tyi, Operand immOp> {
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RegisterClass RCi, ValueType Tyi, Operand immOp,
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SDPatternOperator OpNode=null_frag> {
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// VE calculates (OpNode $sy, $sz), but llvm requires to have immediate
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// in RHS, so we use following definition.
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def ri : RR<opc, (outs RCo:$sx), (ins RCi:$sz, immOp:$sy),
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@ -282,9 +279,10 @@ multiclass RRmri<string opcStr, bits<8>opc, SDNode OpNode,
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{ let cy = 0; let cz = 1; let hasSideEffects = 0; }
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}
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multiclass RRmiz<string opcStr, bits<8>opc, SDNode OpNode,
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multiclass RRmiz<string opcStr, bits<8>opc,
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RegisterClass RCo, ValueType Tyo,
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RegisterClass RCi, ValueType Tyi, Operand immOp> {
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RegisterClass RCi, ValueType Tyi, Operand immOp,
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SDPatternOperator OpNode=null_frag> {
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def zi : RR<opc, (outs RCo:$sx), (ins immOp:$sy),
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!strconcat(opcStr, " $sx, $sy"),
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[(set Tyo:$sx, (OpNode (Tyi simm7:$sy), 0))]>
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@ -326,25 +324,15 @@ multiclass RRNDmim<string opcStr, bits<8>opc,
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// Used by add, mul, div, and similar commutative instructions
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// The order of operands are "$sx, $sy, $sz"
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multiclass RRm<string opcStr, bits<8>opc, SDNode OpNode,
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RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> :
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RRmrr<opcStr, opc, OpNode, RC, Ty, RC, Ty>,
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RRmri<opcStr, opc, OpNode, RC, Ty, RC, Ty, immOp>,
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RRmiz<opcStr, opc, OpNode, RC, Ty, RC, Ty, immOp>,
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multiclass RRm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty,
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Operand immOp, Operand immOp2,
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SDPatternOperator OpNode=null_frag> :
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RRmrr<opcStr, opc, RC, Ty, RC, Ty, OpNode>,
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RRmri<opcStr, opc, RC, Ty, RC, Ty, immOp, OpNode>,
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RRmiz<opcStr, opc, RC, Ty, RC, Ty, immOp, OpNode>,
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RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>,
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RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, immOp2>;
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// Used by cmp instruction
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// The order of operands are "$sx, $sy, $sz"
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multiclass RRNDm<string opcStr, bits<8>opc,
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RegisterClass RC, ValueType Ty,
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Operand immOp, Operand immOp2> :
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RRNDmrr<opcStr, opc, RC, Ty, RC, Ty>,
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//RRNDmir<opcStr, opc, RC, Ty, RC, Ty, immOp>,
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//RRNDmiz<opcStr, opc, RC, Ty, RC, Ty, immOp>,
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RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>,
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RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, immOp2>;
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// Multiclass for RR type instructions
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// Used by sra, sla, sll, and similar instructions
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@ -432,53 +420,53 @@ defm LEA32 : RMm<"lea", 0x06, I32, i32, simm7Op32, simm32Op32>;
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// ADS instruction
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let cx = 0 in
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defm ADS : RRm<"adds.w.sx", 0x4A, add, I32, i32, simm7Op32, uimm6Op32>;
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defm ADS : RRm<"adds.w.sx", 0x4A, I32, i32, simm7Op32, uimm6Op32, add>;
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let cx = 1 in
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defm ADSU : RRm<"adds.w.zx", 0x4A, add, I32, i32, simm7Op32, uimm6Op32>;
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defm ADSU : RRm<"adds.w.zx", 0x4A, I32, i32, simm7Op32, uimm6Op32, add>;
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// ADX instruction
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let cx = 0 in
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defm ADX : RRm<"adds.l", 0x59, add, I64, i64, simm7Op64, uimm6Op64>;
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defm ADX : RRm<"adds.l", 0x59, I64, i64, simm7Op64, uimm6Op64, add>;
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// CMP instruction
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let cx = 0 in
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defm CMP : RRNDm<"cmpu.l", 0x55, I64, i64, simm7Op64, uimm6Op64>;
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defm CMP : RRm<"cmpu.l", 0x55, I64, i64, simm7Op64, uimm6Op64>;
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let cx = 1 in
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defm CMPUW : RRNDm<"cmpu.w", 0x55, I32, i32, simm7Op32, uimm6Op32>;
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defm CMPUW : RRm<"cmpu.w", 0x55, I32, i32, simm7Op32, uimm6Op32>;
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// CPS instruction
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let cx = 0 in
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defm CPS : RRNDm<"cmps.w.sx", 0x7A, I32, i32, simm7Op32, uimm6Op32>;
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defm CPS : RRm<"cmps.w.sx", 0x7A, I32, i32, simm7Op32, uimm6Op32>;
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let cx = 1 in
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defm CPSU : RRNDm<"cmps.w.zx", 0x7A, I32, i32, simm7Op32, uimm6Op32>;
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defm CPSU : RRm<"cmps.w.zx", 0x7A, I32, i32, simm7Op32, uimm6Op32>;
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// CPX instruction
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let cx = 0 in
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defm CPX : RRNDm<"cmps.l", 0x6A, I64, i64, simm7Op64, uimm6Op64>;
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defm CPX : RRm<"cmps.l", 0x6A, I64, i64, simm7Op64, uimm6Op64>;
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// cx: sx/zx, cw: max/min
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let cw = 0 in defm CMXa :
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RRNDm<"maxs.l", 0x68, I64, i64, simm7Op64, uimm6Op64>;
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RRm<"maxs.l", 0x68, I64, i64, simm7Op64, uimm6Op64>;
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let cx = 0, cw = 0 in defm CMSa :
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RRNDm<"maxs.w.zx", 0x78, I32, i32, simm7Op32, uimm6Op32>;
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RRm<"maxs.w.zx", 0x78, I32, i32, simm7Op32, uimm6Op32>;
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let cw = 1 in defm CMXi :
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RRNDm<"mins.l", 0x68, I64, i64, simm7Op64, uimm6Op64>;
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RRm<"mins.l", 0x68, I64, i64, simm7Op64, uimm6Op64>;
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let cx = 1, cw = 0 in defm CMSi :
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RRNDm<"mins.w.zx", 0x78, I32, i32, simm7Op32, uimm6Op32>;
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RRm<"mins.w.zx", 0x78, I32, i32, simm7Op32, uimm6Op32>;
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// 5.3.2.3. Logical Arithmetic Operation Instructions
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let cx = 0 in {
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defm AND : RRm<"and", 0x44, and, I64, i64, simm7Op64, uimm6Op64>;
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defm OR : RRm<"or", 0x45, or, I64, i64, simm7Op64, uimm6Op64>;
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defm AND : RRm<"and", 0x44, I64, i64, simm7Op64, uimm6Op64, and>;
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defm OR : RRm<"or", 0x45, I64, i64, simm7Op64, uimm6Op64, or>;
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let isCodeGenOnly = 1 in {
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defm AND32 : RRm<"and", 0x44, and, I32, i32, simm7Op32, uimm6Op32>;
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defm OR32 : RRm<"or", 0x45, or, I32, i32, simm7Op32, uimm6Op32>;
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defm XOR32 : RRm<"xor", 0x46, xor, I32, i32, simm7Op32, uimm6Op32>;
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defm AND32 : RRm<"and", 0x44, I32, i32, simm7Op32, uimm6Op32, and>;
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defm OR32 : RRm<"or", 0x45, I32, i32, simm7Op32, uimm6Op32, or>;
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defm XOR32 : RRm<"xor", 0x46, I32, i32, simm7Op32, uimm6Op32, xor>;
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}
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}
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@ -497,22 +485,22 @@ defm SLA : RRIm<"sla.w.sx", 0x66, shl, I32, i32, simm7Op32, uimm6Op32>;
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// FCP instruction
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let cx = 0 in
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defm FCP : RRNDm<"fcmp.d", 0x7E, I64, f64, simm7Op64, uimm6Op64>;
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defm FCP : RRm<"fcmp.d", 0x7E, I64, f64, simm7Op64, uimm6Op64>;
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let cx = 1 in
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defm FCPS : RRNDm<"fcmp.s", 0x7E, F32, f32, simm7Op32, uimm6Op32>;
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defm FCPS : RRm<"fcmp.s", 0x7E, F32, f32, simm7Op32, uimm6Op32>;
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// FCM
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let cw = 0 in {
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let cx = 0 in
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defm FCMA : RRNDm<"fmax.d", 0x3E, I64, f64, simm7Op64, uimm6Op64>;
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defm FCMA : RRm<"fmax.d", 0x3E, I64, f64, simm7Op64, uimm6Op64>;
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let cx = 1 in
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defm FCMAS : RRNDm<"fmax.s", 0x3E, F32, f32, simm7Op32, uimm6Op32>;
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defm FCMAS : RRm<"fmax.s", 0x3E, F32, f32, simm7Op32, uimm6Op32>;
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}
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let cw = 1 in {
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let cx = 0 in
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defm FCMI : RRNDm<"fmin.d", 0x3E, I64, f64, simm7Op64, uimm6Op64>;
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defm FCMI : RRm<"fmin.d", 0x3E, I64, f64, simm7Op64, uimm6Op64>;
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let cx = 1 in
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defm FCMIS : RRNDm<"fmin.s", 0x3E, F32, f32, simm7Op32, uimm6Op32>;
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defm FCMIS : RRm<"fmin.s", 0x3E, F32, f32, simm7Op32, uimm6Op32>;
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}
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// Load and Store instructions
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