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SPARCv9: recognize SIR trap instruction

This commit is contained in:
Joerg Sonnenberger 2021-02-06 01:34:02 +01:00
parent c3e4f3b231
commit 9179764710
3 changed files with 13 additions and 1 deletions
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3
llvm/lib/Target/Sparc/SparcInstrAliases.td
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@ -521,3 +521,6 @@ def : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<
// signx reg, rd -> sra reg, %g0, rd
def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;
// sir -> sir 0
def : InstAlias<"sir", (SIR 0), 0>;

5
llvm/lib/Target/Sparc/SparcInstrInfo.td
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@ -1534,6 +1534,11 @@ let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
def MEMBARi : F3_2<2, 0b101000, (outs), (ins MembarTag:$simm13),
"membar $simm13", []>;
let Predicates = [HasV9], rd = 15, rs1 = 0b00000 in
def SIR: F3_2<2, 0b110000, (outs),
(ins simm13Op:$simm13),
"sir $simm13", []>;
// The CAS instruction, unlike other instructions, only comes in a
// form which requires an ASI be provided. The ASI value hardcoded
// here is ASI_PRIMARY, the default unprivileged ASI for SparcV9.

6
llvm/test/MC/Sparc/sparc-v9-traps.s
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@ -300,4 +300,8 @@
tvs %xcc, 82
tvs %xcc, %g1 + %i2
tvs %xcc, %i5 + 41
! CHECK: sir 0 ! encoding: [0x9f,0x80,0x20,0x00]
! CHECK: sir 123 ! encoding: [0x9f,0x80,0x20,0x7b]
sir
sir 123