forked from OSchip/llvm-project
[AArch64] Adjust the cost model for Exynos M1 and M2
Refine the model of loads and stores using the register offset addressing modes. llvm-svn: 313554
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9cd1bd7a83
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91650ef061
llvm/lib/Target/AArch64
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@ -736,6 +736,7 @@ bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
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bool AArch64InstrInfo::isExynosShiftLeftFast(const MachineInstr &MI) const {
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bool AArch64InstrInfo::isExynosShiftLeftFast(const MachineInstr &MI) const {
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unsigned Imm, Shift;
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unsigned Imm, Shift;
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AArch64_AM::ShiftExtendType Ext;
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switch (MI.getOpcode()) {
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switch (MI.getOpcode()) {
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default:
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default:
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@ -779,8 +780,8 @@ bool AArch64InstrInfo::isExynosShiftLeftFast(const MachineInstr &MI) const {
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case AArch64::SUBXrs:
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case AArch64::SUBXrs:
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Imm = MI.getOperand(3).getImm();
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Imm = MI.getOperand(3).getImm();
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Shift = AArch64_AM::getShiftValue(Imm);
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Shift = AArch64_AM::getShiftValue(Imm);
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return (Shift == 0 ||
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Ext = AArch64_AM::getShiftType(Imm);
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(Shift <= 3 && AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL));
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return (Shift == 0 || (Shift <= 3 && Ext == AArch64_AM::LSL));
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// WriteIEReg
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// WriteIEReg
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case AArch64::ADDSWrx:
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case AArch64::ADDSWrx:
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@ -797,9 +798,62 @@ bool AArch64InstrInfo::isExynosShiftLeftFast(const MachineInstr &MI) const {
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case AArch64::SUBXrx64:
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case AArch64::SUBXrx64:
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Imm = MI.getOperand(3).getImm();
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Imm = MI.getOperand(3).getImm();
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Shift = AArch64_AM::getArithShiftValue(Imm);
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Shift = AArch64_AM::getArithShiftValue(Imm);
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return (Shift == 0 ||
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Ext = AArch64_AM::getArithExtendType(Imm);
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(Shift <= 3 &&
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return (Shift == 0 || (Shift <= 3 && Ext == AArch64_AM::UXTX));
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AArch64_AM::getArithExtendType(Imm) == AArch64_AM::UXTX));
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case AArch64::PRFMroW:
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case AArch64::PRFMroX:
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// WriteLDIdx
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case AArch64::LDRBBroW:
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case AArch64::LDRBBroX:
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case AArch64::LDRHHroW:
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case AArch64::LDRHHroX:
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case AArch64::LDRSBWroW:
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case AArch64::LDRSBWroX:
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case AArch64::LDRSBXroW:
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case AArch64::LDRSBXroX:
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case AArch64::LDRSHWroW:
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case AArch64::LDRSHWroX:
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case AArch64::LDRSHXroW:
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case AArch64::LDRSHXroX:
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case AArch64::LDRSWroW:
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case AArch64::LDRSWroX:
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case AArch64::LDRWroW:
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case AArch64::LDRWroX:
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case AArch64::LDRXroW:
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case AArch64::LDRXroX:
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case AArch64::LDRBroW:
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case AArch64::LDRBroX:
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case AArch64::LDRDroW:
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case AArch64::LDRDroX:
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case AArch64::LDRHroW:
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case AArch64::LDRHroX:
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case AArch64::LDRSroW:
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case AArch64::LDRSroX:
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// WriteSTIdx
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case AArch64::STRBBroW:
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case AArch64::STRBBroX:
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case AArch64::STRHHroW:
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case AArch64::STRHHroX:
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case AArch64::STRWroW:
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case AArch64::STRWroX:
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case AArch64::STRXroW:
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case AArch64::STRXroX:
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case AArch64::STRBroW:
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case AArch64::STRBroX:
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case AArch64::STRDroW:
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case AArch64::STRDroX:
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case AArch64::STRHroW:
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case AArch64::STRHroX:
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case AArch64::STRSroW:
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case AArch64::STRSroX:
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Imm = MI.getOperand(3).getImm();
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Ext = AArch64_AM::getMemExtendType(Imm);
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return (Ext == AArch64_AM::SXTX || Ext == AArch64_AM::UXTX);
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}
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}
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}
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}
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@ -88,16 +88,19 @@ def M1WriteBX : SchedWriteVariant<[SchedVar<M1BranchLinkFastPred, [M1WriteA1,
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M1WriteC1]>]>;
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M1WriteC1]>]>;
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def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
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def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
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def M1WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteL5,
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def M1WriteLX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
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M1WriteA1]>,
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SchedVar<NoSchedPred, [M1WriteA1,
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SchedVar<NoSchedPred, [M1WriteL5]>]>;
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M1WriteL5]>]>;
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def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; }
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def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; }
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def M1WriteS2 : SchedWriteRes<[M1UnitS]> { let Latency = 2; }
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def M1WriteS2 : SchedWriteRes<[M1UnitS]> { let Latency = 2; }
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def M1WriteS4 : SchedWriteRes<[M1UnitS]> { let Latency = 4; }
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def M1WriteS4 : SchedWriteRes<[M1UnitS]> { let Latency = 4; }
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def M1WriteSX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteS2,
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def M1WriteSX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
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M1WriteA1]>,
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SchedVar<NoSchedPred, [M1WriteA1,
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SchedVar<NoSchedPred, [M1WriteS1]>]>;
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M1WriteS1]>]>;
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def M1WriteSY : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
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SchedVar<NoSchedPred, [M1WriteA1,
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M1WriteS2]>]>;
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def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
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def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
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SchedVar<NoSchedPred, [ReadDefault]>]>;
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SchedVar<NoSchedPred, [ReadDefault]>]>;
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@ -369,6 +372,8 @@ def : InstRW<[WriteLD,
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WriteLDHi,
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WriteLDHi,
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WriteAdr,
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WriteAdr,
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M1WriteA1], (instregex "^LDP(SW|W|X)(post|pre)")>;
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M1WriteA1], (instregex "^LDP(SW|W|X)(post|pre)")>;
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def : InstRW<[M1WriteLX,
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ReadAdrBase], (instregex "^PRFMro[WX]")>;
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// Store instructions.
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// Store instructions.
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@ -401,20 +406,30 @@ def : InstRW<[M1WriteNEONI], (instregex "^FMOV[DS][WX](High)?r")>;
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// FP load instructions.
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// FP load instructions.
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def : InstRW<[WriteVLD,
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def : InstRW<[WriteVLD,
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WriteAdr,
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WriteAdr,
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M1WriteA1], (instregex "^LDP[DS](post|pre)")>;
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M1WriteA1], (instregex "^LDP[DS](post|pre)")>;
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def : InstRW<[WriteVLD,
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def : InstRW<[WriteVLD,
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WriteVLD,
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WriteVLD,
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WriteAdr,
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WriteAdr,
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M1WriteA1], (instregex "^LDPQ(post|pre)")>;
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M1WriteA1], (instregex "^LDPQ(post|pre)")>;
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def : InstRW<[M1WriteLX,
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ReadAdrBase], (instregex "^LDR[BDHS]ro[WX]")>;
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def : InstRW<[M1WriteA1,
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M1WriteL5,
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ReadAdrBase], (instregex "^LDRQro[WX]")>;
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// FP store instructions.
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// FP store instructions.
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def : InstRW<[WriteVST,
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def : InstRW<[WriteVST,
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WriteAdr,
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WriteAdr,
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M1WriteA1], (instregex "^STP[DS](post|pre)")>;
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M1WriteA1], (instregex "^STP[DS](post|pre)")>;
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def : InstRW<[WriteVST,
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def : InstRW<[WriteVST,
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WriteVST,
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WriteVST,
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WriteAdr,
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WriteAdr,
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M1WriteA1], (instregex "^STPQ(post|pre)")>;
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M1WriteA1], (instregex "^STPQ(post|pre)")>;
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def : InstRW<[M1WriteSY,
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ReadAdrBase], (instregex "^STR[BDHS]ro[WX]")>;
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def : InstRW<[M1WriteA1,
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M1WriteS2,
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ReadAdrBase], (instregex "^STRQro[WX]")>;
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// ASIMD instructions.
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// ASIMD instructions.
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def : InstRW<[M1WriteNMISC3], (instregex "^[SU]ABAL?v")>;
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def : InstRW<[M1WriteNMISC3], (instregex "^[SU]ABAL?v")>;
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