diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h index f7006517e3df..4a7406473b11 100644 --- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h +++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h @@ -347,7 +347,7 @@ struct ScalarEnumerationTraits { static void enumeration(yaml::IO &IO, TargetStackID::Value &ID) { IO.enumCase(ID, "default", TargetStackID::Default); IO.enumCase(ID, "sgpr-spill", TargetStackID::SGPRSpill); - IO.enumCase(ID, "sve-vec", TargetStackID::SVEVector); + IO.enumCase(ID, "scalable-vector", TargetStackID::ScalableVector); IO.enumCase(ID, "noalloc", TargetStackID::NoAlloc); } }; diff --git a/llvm/include/llvm/CodeGen/TargetFrameLowering.h b/llvm/include/llvm/CodeGen/TargetFrameLowering.h index c6806793f248..792452f6e81d 100644 --- a/llvm/include/llvm/CodeGen/TargetFrameLowering.h +++ b/llvm/include/llvm/CodeGen/TargetFrameLowering.h @@ -27,7 +27,7 @@ namespace TargetStackID { enum Value { Default = 0, SGPRSpill = 1, - SVEVector = 2, + ScalableVector = 2, NoAlloc = 255 }; } diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index 1687fd0116a5..65ee5016042c 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -249,7 +249,7 @@ static unsigned estimateRSStackSizeLimit(MachineFunction &MF) { TargetStackID::Value AArch64FrameLowering::getStackIDForScalableVectors() const { - return TargetStackID::SVEVector; + return TargetStackID::ScalableVector; } /// Returns the size of the fixed object area (allocated next to sp on entry) @@ -496,7 +496,7 @@ void AArch64FrameLowering::emitCalleeSavedFrameMoves( continue; StackOffset Offset; - if (MFI.getStackID(Info.getFrameIdx()) == TargetStackID::SVEVector) { + if (MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector) { AArch64FunctionInfo *AFI = MF.getInfo(); Offset = StackOffset::getScalable(MFI.getObjectOffset(Info.getFrameIdx())) - @@ -1856,7 +1856,7 @@ StackOffset AArch64FrameLowering::resolveFrameIndexReference( const auto &MFI = MF.getFrameInfo(); int64_t ObjectOffset = MFI.getObjectOffset(FI); bool isFixed = MFI.isFixedObjectIndex(FI); - bool isSVE = MFI.getStackID(FI) == TargetStackID::SVEVector; + bool isSVE = MFI.getStackID(FI) == TargetStackID::ScalableVector; return resolveFrameOffsetReference(MF, ObjectOffset, isFixed, isSVE, FrameReg, PreferFP, ForSimm); } @@ -2412,7 +2412,7 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( // Update the StackIDs of the SVE stack slots. MachineFrameInfo &MFI = MF.getFrameInfo(); if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) - MFI.setStackID(RPI.FrameIdx, TargetStackID::SVEVector); + MFI.setStackID(RPI.FrameIdx, TargetStackID::ScalableVector); } return true; @@ -2761,7 +2761,7 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI, #ifndef NDEBUG // First process all fixed stack objects. for (int I = MFI.getObjectIndexBegin(); I != 0; ++I) - assert(MFI.getStackID(I) != TargetStackID::SVEVector && + assert(MFI.getStackID(I) != TargetStackID::ScalableVector && "SVE vectors should never be passed on the stack by value, only by " "reference."); #endif @@ -2791,7 +2791,7 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI, SmallVector ObjectsToAllocate; for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) { unsigned StackID = MFI.getStackID(I); - if (StackID != TargetStackID::SVEVector) + if (StackID != TargetStackID::ScalableVector) continue; if (MaxCSFrameIndex >= I && I >= MinCSFrameIndex) continue; diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.h b/llvm/lib/Target/AArch64/AArch64FrameLowering.h index 819df2610b8a..80079a9d9836 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.h +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.h @@ -107,7 +107,7 @@ public: default: return false; case TargetStackID::Default: - case TargetStackID::SVEVector: + case TargetStackID::ScalableVector: case TargetStackID::NoAlloc: return true; } @@ -116,7 +116,7 @@ public: bool isStackIdSafeForLocalArea(unsigned StackId) const override { // We don't support putting SVE objects into the pre-allocated local // frame block at the moment. - return StackId != TargetStackID::SVEVector; + return StackId != TargetStackID::ScalableVector; } void diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index b4cb62cd5348..b500cd534a1f 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -5400,7 +5400,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, Type *Ty = EVT(VA.getValVT()).getTypeForEVT(*DAG.getContext()); Align Alignment = DAG.getDataLayout().getPrefTypeAlign(Ty); int FI = MFI.CreateStackObject(StoreSize, Alignment, false); - MFI.setStackID(FI, TargetStackID::SVEVector); + MFI.setStackID(FI, TargetStackID::ScalableVector); MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 8a5447eeeb3c..ab5bb88759e5 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -3291,7 +3291,7 @@ void AArch64InstrInfo::storeRegToStackSlot( else if (AArch64::PPRRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); Opc = AArch64::STR_PXI; - StackID = TargetStackID::SVEVector; + StackID = TargetStackID::ScalableVector; } break; case 4: @@ -3335,7 +3335,7 @@ void AArch64InstrInfo::storeRegToStackSlot( } else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); Opc = AArch64::STR_ZXI; - StackID = TargetStackID::SVEVector; + StackID = TargetStackID::ScalableVector; } break; case 24: @@ -3357,7 +3357,7 @@ void AArch64InstrInfo::storeRegToStackSlot( } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC)) { assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); Opc = AArch64::STR_ZZXI; - StackID = TargetStackID::SVEVector; + StackID = TargetStackID::ScalableVector; } break; case 48: @@ -3368,7 +3368,7 @@ void AArch64InstrInfo::storeRegToStackSlot( } else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) { assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); Opc = AArch64::STR_ZZZXI; - StackID = TargetStackID::SVEVector; + StackID = TargetStackID::ScalableVector; } break; case 64: @@ -3379,7 +3379,7 @@ void AArch64InstrInfo::storeRegToStackSlot( } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC)) { assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); Opc = AArch64::STR_ZZZZXI; - StackID = TargetStackID::SVEVector; + StackID = TargetStackID::ScalableVector; } break; } @@ -3445,7 +3445,7 @@ void AArch64InstrInfo::loadRegFromStackSlot( else if (AArch64::PPRRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasSVE() && "Unexpected register load without SVE"); Opc = AArch64::LDR_PXI; - StackID = TargetStackID::SVEVector; + StackID = TargetStackID::ScalableVector; } break; case 4: @@ -3489,7 +3489,7 @@ void AArch64InstrInfo::loadRegFromStackSlot( } else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasSVE() && "Unexpected register load without SVE"); Opc = AArch64::LDR_ZXI; - StackID = TargetStackID::SVEVector; + StackID = TargetStackID::ScalableVector; } break; case 24: @@ -3511,7 +3511,7 @@ void AArch64InstrInfo::loadRegFromStackSlot( } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC)) { assert(Subtarget.hasSVE() && "Unexpected register load without SVE"); Opc = AArch64::LDR_ZZXI; - StackID = TargetStackID::SVEVector; + StackID = TargetStackID::ScalableVector; } break; case 48: @@ -3522,7 +3522,7 @@ void AArch64InstrInfo::loadRegFromStackSlot( } else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) { assert(Subtarget.hasSVE() && "Unexpected register load without SVE"); Opc = AArch64::LDR_ZZZXI; - StackID = TargetStackID::SVEVector; + StackID = TargetStackID::ScalableVector; } break; case 64: @@ -3533,7 +3533,7 @@ void AArch64InstrInfo::loadRegFromStackSlot( } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC)) { assert(Subtarget.hasSVE() && "Unexpected register load without SVE"); Opc = AArch64::LDR_ZZZZXI; - StackID = TargetStackID::SVEVector; + StackID = TargetStackID::ScalableVector; } break; } diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index c934341c2451..65f1ac353969 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -783,7 +783,7 @@ bool SIFrameLowering::isSupportedStackID(TargetStackID::Value ID) const { case TargetStackID::NoAlloc: case TargetStackID::SGPRSpill: return true; - case TargetStackID::SVEVector: + case TargetStackID::ScalableVector: return false; } llvm_unreachable("Invalid TargetStackID::Value"); diff --git a/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir b/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir index 39b11ef7bfea..32b8cd092024 100644 --- a/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir +++ b/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir @@ -158,16 +158,16 @@ frameInfo: maxCallFrameSize: 0 localFrameSize: 8 stack: - - { id: 0, name: z0.addr, size: 16, alignment: 16, stack-id: sve-vec, + - { id: 0, name: z0.addr, size: 16, alignment: 16, stack-id: scalable-vector, debug-info-variable: '!29', debug-info-expression: '!DIExpression()', debug-info-location: '!30' } - - { id: 1, name: z1.addr, size: 16, alignment: 16, stack-id: sve-vec, + - { id: 1, name: z1.addr, size: 16, alignment: 16, stack-id: scalable-vector, debug-info-variable: '!31', debug-info-expression: '!DIExpression()', debug-info-location: '!32' } - - { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: sve-vec, + - { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-vector, debug-info-variable: '!33', debug-info-expression: '!DIExpression()', debug-info-location: '!34' } - - { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: sve-vec, + - { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-vector, debug-info-variable: '!35', debug-info-expression: '!DIExpression()', debug-info-location: '!36' } - { id: 4, name: w0.addr, size: 4, alignment: 4, local-offset: -4, debug-info-variable: '!37', @@ -175,16 +175,16 @@ stack: - { id: 5, name: local_gpr0, size: 4, alignment: 4, local-offset: -8, debug-info-variable: '!39', debug-info-expression: '!DIExpression()', debug-info-location: '!40' } - - { id: 6, name: localv0, size: 16, alignment: 16, stack-id: sve-vec, + - { id: 6, name: localv0, size: 16, alignment: 16, stack-id: scalable-vector, debug-info-variable: '!42', debug-info-expression: '!DIExpression()', debug-info-location: '!43' } - - { id: 7, name: localv1, size: 16, alignment: 16, stack-id: sve-vec, + - { id: 7, name: localv1, size: 16, alignment: 16, stack-id: scalable-vector, debug-info-variable: '!45', debug-info-expression: '!DIExpression()', debug-info-location: '!46' } - - { id: 8, name: localp0, size: 2, alignment: 2, stack-id: sve-vec, + - { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-vector, debug-info-variable: '!48', debug-info-expression: '!DIExpression()', debug-info-location: '!49' } - - { id: 9, name: localp1, size: 2, alignment: 2, stack-id: sve-vec, + - { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-vector, debug-info-variable: '!51', debug-info-expression: '!DIExpression()', debug-info-location: '!52' } machineFunctionInfo: {} diff --git a/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir b/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir index 84d34ce3d2ac..75917ef32ae2 100644 --- a/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir +++ b/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir @@ -94,10 +94,10 @@ frameInfo: stack: - { id: 0, size: 8, alignment: 8 } - { id: 1, size: 8, alignment: 8 } - - { id: 2, size: 16, alignment: 16, stack-id: sve-vec } - - { id: 3, size: 16, alignment: 16, stack-id: sve-vec } - - { id: 4, size: 2, alignment: 2, stack-id: sve-vec } - - { id: 5, size: 2, alignment: 2, stack-id: sve-vec } + - { id: 2, size: 16, alignment: 16, stack-id: scalable-vector } + - { id: 3, size: 16, alignment: 16, stack-id: scalable-vector } + - { id: 4, size: 2, alignment: 2, stack-id: scalable-vector } + - { id: 5, size: 2, alignment: 2, stack-id: scalable-vector } machineFunctionInfo: {} body: | bb.0.entry: diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir b/llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir index a366744d8fa2..623c0f240be4 100644 --- a/llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir +++ b/llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir @@ -14,7 +14,7 @@ frameInfo: stack: - { id: 0, type: variable-sized, alignment: 1 } - { id: 1, name: '', size: 16, alignment: 8 } - - { id: 2, stack-id: sve-vec, size: 16, alignment: 16 } + - { id: 2, stack-id: scalable-vector, size: 16, alignment: 16 } body: | bb.0: liveins: $x0 diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir b/llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir index a3cbd39c6531..61f2e37963ab 100644 --- a/llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir +++ b/llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir @@ -24,7 +24,7 @@ ... name: fix_restorepoint_p4 stack: - - { id: 0, stack-id: sve-vec, size: 16, alignment: 16 } + - { id: 0, stack-id: scalable-vector, size: 16, alignment: 16 } body: | bb.0.entry: $z8 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir b/llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir index 2ee6007db289..f15ab4ee0c6f 100644 --- a/llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir +++ b/llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir @@ -16,7 +16,7 @@ frameInfo: isFrameAddressTaken: true stack: - { id: 0, name: '', size: 32761, alignment: 8 } - - { id: 1, stack-id: sve-vec, size: 16, alignment: 16 } + - { id: 1, stack-id: scalable-vector, size: 16, alignment: 16 } body: | bb.0: liveins: $x0, $x8 diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve.mir b/llvm/test/CodeGen/AArch64/framelayout-sve.mir index 1c8a44223eb0..b3d17cf17bbe 100644 --- a/llvm/test/CodeGen/AArch64/framelayout-sve.mir +++ b/llvm/test/CodeGen/AArch64/framelayout-sve.mir @@ -74,7 +74,7 @@ # UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16 name: test_allocate_sve stack: - - { id: 0, stack-id: sve-vec, size: 18, alignment: 2 } + - { id: 0, stack-id: scalable-vector, size: 18, alignment: 2 } - { id: 1, stack-id: default, size: 16, alignment: 8 } body: | bb.0.entry: @@ -120,7 +120,7 @@ body: | # UNWINDINFO-NEXT: DW_CFA_offset: reg29 -32 name: test_allocate_sve_gpr_callee_saves stack: - - { id: 0, stack-id: sve-vec, size: 18, alignment: 2 } + - { id: 0, stack-id: scalable-vector, size: 18, alignment: 2 } - { id: 1, stack-id: default, size: 16, alignment: 8 } body: | bb.0.entry: @@ -162,7 +162,7 @@ body: | name: test_allocate_sve_gpr_realigned stack: - - { id: 0, stack-id: sve-vec, size: 18, alignment: 2 } + - { id: 0, stack-id: scalable-vector, size: 18, alignment: 2 } - { id: 1, stack-id: default, size: 16, alignment: 32 } body: | bb.0.entry: @@ -211,9 +211,9 @@ name: test_address_sve frameInfo: maxAlignment: 16 stack: - - { id: 0, stack-id: sve-vec, size: 16, alignment: 8 } - - { id: 1, stack-id: sve-vec, size: 16, alignment: 8 } - - { id: 2, stack-id: sve-vec, size: 2, alignment: 2 } + - { id: 0, stack-id: scalable-vector, size: 16, alignment: 8 } + - { id: 1, stack-id: scalable-vector, size: 16, alignment: 8 } + - { id: 2, stack-id: scalable-vector, size: 2, alignment: 2 } - { id: 3, stack-id: default, size: 16, alignment: 8 } body: | bb.0.entry: @@ -269,9 +269,9 @@ frameInfo: maxAlignment: 16 isFrameAddressTaken: true stack: - - { id: 0, stack-id: sve-vec, size: 16, alignment: 8 } - - { id: 1, stack-id: sve-vec, size: 16, alignment: 8 } - - { id: 2, stack-id: sve-vec, size: 2, alignment: 2 } + - { id: 0, stack-id: scalable-vector, size: 16, alignment: 8 } + - { id: 1, stack-id: scalable-vector, size: 16, alignment: 8 } + - { id: 2, stack-id: scalable-vector, size: 2, alignment: 2 } - { id: 3, stack-id: default, size: 16, alignment: 8 } body: | bb.0.entry: @@ -321,7 +321,7 @@ name: test_stack_arg_sve fixedStack: - { id: 0, stack-id: default, size: 16, alignment: 16, offset: 0 } stack: - - { id: 0, stack-id: sve-vec, size: 16, alignment: 16 } + - { id: 0, stack-id: scalable-vector, size: 16, alignment: 16 } - { id: 1, stack-id: default, size: 16, alignment: 16 } body: | bb.0.entry: @@ -387,9 +387,9 @@ name: test_address_sve_out_of_range frameInfo: maxAlignment: 16 stack: - - { id: 0, stack-id: sve-vec, size: 16, alignment: 16 } - - { id: 1, stack-id: sve-vec, size: 3584, alignment: 16 } - - { id: 2, stack-id: sve-vec, size: 512, alignment: 16 } + - { id: 0, stack-id: scalable-vector, size: 16, alignment: 16 } + - { id: 1, stack-id: scalable-vector, size: 3584, alignment: 16 } + - { id: 2, stack-id: scalable-vector, size: 512, alignment: 16 } body: | bb.0.entry: @@ -432,7 +432,7 @@ name: test_address_gpr_vla frameInfo: maxAlignment: 16 stack: - - { id: 0, stack-id: sve-vec, size: 16, alignment: 8 } + - { id: 0, stack-id: scalable-vector, size: 16, alignment: 8 } - { id: 1, stack-id: default, size: 16, alignment: 8 } - { id: 2, stack-id: default, type: variable-sized } body: | @@ -588,7 +588,7 @@ body: | name: save_restore_sve stack: - - { id: 0, stack-id: sve-vec, size: 16, alignment: 16 } + - { id: 0, stack-id: scalable-vector, size: 16, alignment: 16 } - { id: 1, stack-id: default, size: 32, alignment: 16 } body: | bb.0.entry: @@ -679,7 +679,7 @@ body: | # UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16 name: save_restore_sve_realign stack: - - { id: 0, stack-id: sve-vec, size: 16, alignment: 16 } + - { id: 0, stack-id: scalable-vector, size: 16, alignment: 16 } - { id: 1, stack-id: default, size: 16, alignment: 32 } body: | bb.0.entry: @@ -721,25 +721,25 @@ body: | # CHECK-LABEL: name: frame_layout # CHECK: stack: # CHECK: - { id: 0, name: '', type: default, offset: -80, size: 32, alignment: 16, -# CHECK-NEXT: stack-id: sve-vec, +# CHECK-NEXT: stack-id: scalable-vector, # CHECK: - { id: 1, name: '', type: default, offset: -84, size: 4, alignment: 2, -# CHECK-NEXT: stack-id: sve-vec, +# CHECK-NEXT: stack-id: scalable-vector, # CHECK: - { id: 2, name: '', type: default, offset: -112, size: 16, alignment: 16, -# CHECK-NEXT: stack-id: sve-vec, +# CHECK-NEXT: stack-id: scalable-vector, # CHECK: - { id: 3, name: '', type: default, offset: -114, size: 2, alignment: 2, -# CHECK-NEXT: stack-id: sve-vec, +# CHECK-NEXT: stack-id: scalable-vector, # CHECK: - { id: 4, name: '', type: spill-slot, offset: -144, size: 16, alignment: 16, -# CHECK-NEXT: stack-id: sve-vec, +# CHECK-NEXT: stack-id: scalable-vector, # CHECK: - { id: 5, name: '', type: spill-slot, offset: -146, size: 2, alignment: 2, -# CHECK-NEXT: stack-id: sve-vec, +# CHECK-NEXT: stack-id: scalable-vector, # CHECK: - { id: 6, name: '', type: spill-slot, offset: -16, size: 16, alignment: 16, -# CHECK-NEXT: stack-id: sve-vec, callee-saved-register: '$z8', +# CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: '$z8', # CHECK: - { id: 7, name: '', type: spill-slot, offset: -32, size: 16, alignment: 16, -# CHECK-NEXT: stack-id: sve-vec, callee-saved-register: '$z23', +# CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: '$z23', # CHECK: - { id: 8, name: '', type: spill-slot, offset: -34, size: 2, alignment: 2, -# CHECK-NEXT: stack-id: sve-vec, callee-saved-register: '$p4', +# CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: '$p4', # CHECK: - { id: 9, name: '', type: spill-slot, offset: -36, size: 2, alignment: 2, -# CHECK-NEXT: stack-id: sve-vec, callee-saved-register: '$p15', +# CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: '$p15', # CHECK: - { id: 10, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16, # CHECK-NEXT: stack-id: default, callee-saved-register: '$fp', # @@ -762,12 +762,12 @@ body: | # UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16 name: frame_layout stack: - - { id: 0, type: default, size: 32, alignment: 16, stack-id: sve-vec } - - { id: 1, type: default, size: 4, alignment: 2, stack-id: sve-vec } - - { id: 2, type: default, size: 16, alignment: 16, stack-id: sve-vec } - - { id: 3, type: default, size: 2, alignment: 2, stack-id: sve-vec } - - { id: 4, type: spill-slot, size: 16, alignment: 16, stack-id: sve-vec } - - { id: 5, type: spill-slot, size: 2, alignment: 2, stack-id: sve-vec } + - { id: 0, type: default, size: 32, alignment: 16, stack-id: scalable-vector } + - { id: 1, type: default, size: 4, alignment: 2, stack-id: scalable-vector } + - { id: 2, type: default, size: 16, alignment: 16, stack-id: scalable-vector } + - { id: 3, type: default, size: 2, alignment: 2, stack-id: scalable-vector } + - { id: 4, type: spill-slot, size: 16, alignment: 16, stack-id: scalable-vector } + - { id: 5, type: spill-slot, size: 2, alignment: 2, stack-id: scalable-vector } body: | bb.0.entry: @@ -784,7 +784,7 @@ body: | # FIXME: Should there be an offset? # CHECK-LABEL: name: fp_relative_index_with_float_save # CHECK: - { id: 0, name: '', type: default, offset: -16, size: 16, alignment: 16, -# CHECK-NEXT: stack-id: sve-vec +# CHECK-NEXT: stack-id: scalable-vector # CHECK: - { id: 1, name: '', type: default, offset: -64, size: 16, alignment: 32, # CHECK-NEXT: stack-id: default # CHECK: - { id: 2, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8, @@ -799,7 +799,7 @@ body: | name: fp_relative_index_with_float_save stack: - - { id: 0, stack-id: sve-vec, size: 16, alignment: 16 } + - { id: 0, stack-id: scalable-vector, size: 16, alignment: 16 } - { id: 1, stack-id: default, size: 16, alignment: 32 } frameInfo: maxAlignment: 16 diff --git a/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir b/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir index db05e7ef7f60..493f3ea4ead5 100644 --- a/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir +++ b/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir @@ -120,7 +120,7 @@ frameInfo: savePoint: '%bb.1' restorePoint: '%bb.1' stack: - - { id: 0, size: 16, alignment: 16, stack-id: sve-vec } + - { id: 0, size: 16, alignment: 16, stack-id: scalable-vector } machineFunctionInfo: {} body: | bb.0.entry: diff --git a/llvm/test/CodeGen/AArch64/spillfill-sve.mir b/llvm/test/CodeGen/AArch64/spillfill-sve.mir index 982d232f12f4..951dbc72defc 100644 --- a/llvm/test/CodeGen/AArch64/spillfill-sve.mir +++ b/llvm/test/CodeGen/AArch64/spillfill-sve.mir @@ -30,7 +30,7 @@ body: | ; CHECK-LABEL: name: spills_fills_stack_id_ppr ; CHECK: stack: ; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 2, alignment: 2 - ; CHECK-NEXT: stack-id: sve-vec, callee-saved-register: '' + ; CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: '' ; EXPAND-LABEL: name: spills_fills_stack_id_ppr ; EXPAND: STR_PXI $p0, $sp, 7 @@ -73,7 +73,7 @@ body: | ; CHECK-LABEL: name: spills_fills_stack_id_zpr ; CHECK: stack: ; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 16, alignment: 16 - ; CHECK-NEXT: stack-id: sve-vec, callee-saved-register: '' + ; CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: '' ; EXPAND-LABEL: name: spills_fills_stack_id_zpr ; EXPAND: STR_ZXI $z0, $sp, 0 @@ -108,7 +108,7 @@ body: | ; CHECK-LABEL: name: spills_fills_stack_id_zpr2 ; CHECK: stack: ; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 32, alignment: 16 - ; CHECK-NEXT: stack-id: sve-vec + ; CHECK-NEXT: stack-id: scalable-vector ; EXPAND-LABEL: name: spills_fills_stack_id_zpr2 ; EXPAND: STR_ZXI $z0, $sp, 0 @@ -145,7 +145,7 @@ body: | ; CHECK-LABEL: name: spills_fills_stack_id_zpr3 ; CHECK: stack: ; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 48, alignment: 16 - ; CHECK-NEXT: stack-id: sve-vec + ; CHECK-NEXT: stack-id: scalable-vector ; EXPAND-LABEL: name: spills_fills_stack_id_zpr3 ; EXPAND: STR_ZXI $z0, $sp, 0 @@ -184,7 +184,7 @@ body: | ; CHECK-LABEL: name: spills_fills_stack_id_zpr4 ; CHECK: stack: ; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 64, alignment: 16 - ; CHECK-NEXT: stack-id: sve-vec + ; CHECK-NEXT: stack-id: scalable-vector ; EXPAND-LABEL: name: spills_fills_stack_id_zpr4 ; EXPAND: STR_ZXI $z0, $sp, 0 diff --git a/llvm/test/CodeGen/AArch64/sve-alloca-stackid.ll b/llvm/test/CodeGen/AArch64/sve-alloca-stackid.ll index 4e9ac5a50eb9..dd7d108b7a4e 100644 --- a/llvm/test/CodeGen/AArch64/sve-alloca-stackid.ll +++ b/llvm/test/CodeGen/AArch64/sve-alloca-stackid.ll @@ -11,7 +11,7 @@ ; CHECKISEL-LABEL: name: foo ; CHECKISEL: stack: ; CHECKISEL: id: 0, name: ptr, type: default, offset: 0, size: 16, alignment: 16, -; CHECKISEL-NEXT: stack-id: sve-vec +; CHECKISEL-NEXT: stack-id: scalable-vector define i32 @foo( %val) { %ptr = alloca %res = call i32 @bar(* %ptr) @@ -26,7 +26,7 @@ declare i32 @bar(* %ptr); ; CHECKISEL-LABEL: name: foo2 ; CHECKISEL: stack: ; CHECKISEL: id: 0, name: ptr, type: default, offset: 0, size: 32, alignment: 16, -; CHECKISEL-NEXT: stack-id: sve-vec +; CHECKISEL-NEXT: stack-id: scalable-vector define i32 @foo2( %val) { %ptr = alloca , align 16 diff --git a/llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll b/llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll index bceb39af0bee..4c3920e76f49 100644 --- a/llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll +++ b/llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll @@ -25,9 +25,9 @@ define aarch64_sve_vector_pcs @caller_with_many_sve_arg( @caller_with_many_svepred_arg( @caller_with_many_gpr_sve_arg(i ; CHECK: name: caller_with_many_gpr_sve_arg ; CHECK: stack: ; CHECK: - { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 16, -; CHECK-NEXT: stack-id: sve-vec +; CHECK-NEXT: stack-id: scalable-vector ; CHECK: - { id: 1, name: '', type: default, offset: 0, size: 16, alignment: 16, -; CHECK-NEXT: stack-id: sve-vec +; CHECK-NEXT: stack-id: scalable-vector ; CHECK-DAG: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31 ; CHECK-DAG: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31 ; CHECK-DAG: ST1D_IMM %{{[0-9]+}}, killed [[PTRUE_D]], %stack.0, 0 diff --git a/llvm/test/CodeGen/AArch64/sve-localstackalloc.mir b/llvm/test/CodeGen/AArch64/sve-localstackalloc.mir index c20846c54b6a..3fbb7889c8b7 100644 --- a/llvm/test/CodeGen/AArch64/sve-localstackalloc.mir +++ b/llvm/test/CodeGen/AArch64/sve-localstackalloc.mir @@ -38,7 +38,7 @@ frameInfo: # CHECK: localFrameSize: 0 stack: - { id: 0, name: '', type: default, offset: 0, size: 32, alignment: 16, - stack-id: sve-vec, callee-saved-register: '', callee-saved-restored: true, + stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } machineFunctionInfo: {} body: |