forked from OSchip/llvm-project
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.
* Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! llvm-svn: 155704
This commit is contained in:
Benjamin Kramer
parent
b7ff9b1599
commit
913da4b261
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@ -8214,6 +8214,30 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
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return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
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}
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/// Convert a comparison if required by the subtarget.
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SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
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SelectionDAG &DAG) const {
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// If the subtarget does not support the FUCOMI instruction, floating-point
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// comparisons have to be converted.
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if (Subtarget->hasCMov() ||
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Cmp.getOpcode() != X86ISD::CMP ||
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!Cmp.getOperand(0).getValueType().isFloatingPoint() ||
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!Cmp.getOperand(1).getValueType().isFloatingPoint())
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return Cmp;
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// The instruction selector will select an FUCOM instruction instead of
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// FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
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// build an SDNode sequence that transfers the result from FPSW into EFLAGS:
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// (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
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DebugLoc dl = Cmp.getDebugLoc();
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SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
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SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
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SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
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DAG.getConstant(8, MVT::i8));
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SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
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return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
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}
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/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
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/// if it's possible.
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SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
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@ -8335,6 +8359,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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return SDValue();
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SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
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EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
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return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), EFLAGS);
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}
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@ -8503,7 +8528,8 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
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// isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
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static bool isX86LogicalCmp(SDValue Op) {
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unsigned Opc = Op.getNode()->getOpcode();
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if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
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if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
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Opc == X86ISD::SAHF)
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return true;
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if (Op.getResNo() == 1 &&
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(Opc == X86ISD::ADD ||
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@ -8567,6 +8593,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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SDValue CmpOp0 = Cmp.getOperand(0);
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Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
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CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
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Cmp = ConvertCmpIfNecessary(Cmp, DAG);
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SDValue Res = // Res = 0 or -1.
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DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
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@ -8673,6 +8700,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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// a >= b ? -1 : 0 -> RES = setcc_carry
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// a >= b ? 0 : -1 -> RES = ~setcc_carry
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if (Cond.getOpcode() == X86ISD::CMP) {
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Cond = ConvertCmpIfNecessary(Cond, DAG);
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unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
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if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
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@ -8911,6 +8939,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
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SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
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Cond.getOperand(0), Cond.getOperand(1));
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Cmp = ConvertCmpIfNecessary(Cmp, DAG);
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CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
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Chain, Dest, CC, Cmp);
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@ -8940,6 +8969,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
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SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
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Cond.getOperand(0), Cond.getOperand(1));
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Cmp = ConvertCmpIfNecessary(Cmp, DAG);
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CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
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Chain, Dest, CC, Cmp);
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@ -8973,6 +9003,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
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CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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Cond = EmitTest(Cond, X86::COND_NE, DAG);
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}
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Cond = ConvertCmpIfNecessary(Cond, DAG);
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return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
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Chain, Dest, CC, Cond);
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}
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@ -11111,6 +11142,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
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case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
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case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
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case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
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case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
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case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
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case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
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@ -11179,6 +11211,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
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case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
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case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
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case X86ISD::SAHF: return "X86ISD::SAHF";
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}
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}
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@ -315,6 +315,12 @@ namespace llvm {
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SFENCE,
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LFENCE,
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// FNSTSW16r - Store FP status word into i16 register.
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FNSTSW16r,
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// SAHF - Store contents of %ah into %eflags.
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SAHF,
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// ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
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// ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
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// Atomic 64-bit binary operations.
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@ -909,6 +915,9 @@ namespace llvm {
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/// equivalent, for use with the given x86 condition code.
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SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
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SelectionDAG &DAG) const;
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/// Convert a comparison if required by the subtarget.
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SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
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};
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namespace X86 {
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@ -27,6 +27,7 @@ def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
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SDTCisVT<2, OtherVT>]>;
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def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
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SDTCisVT<2, OtherVT>]>;
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def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
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def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
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def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
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@ -41,6 +42,7 @@ def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
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def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
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[SDNPHasChain, SDNPOutGlue, SDNPMayLoad,
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SDNPMemOperand]>;
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def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>;
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def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
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@ -203,6 +205,7 @@ def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
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}
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}
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let Defs = [FPSW] in {
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defm ADD : FPBinary_rr<fadd>;
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defm SUB : FPBinary_rr<fsub>;
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defm MUL : FPBinary_rr<fmul>;
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@ -213,6 +216,7 @@ defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
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defm MUL : FPBinary<fmul, MRM1m, "mul">;
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defm DIV : FPBinary<fdiv, MRM6m, "div">;
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defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
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}
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class FPST0rInst<bits<8> o, string asm>
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: FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
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@ -257,6 +261,7 @@ def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
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def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
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}
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let Defs = [FPSW] in {
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defm CHS : FPUnary<fneg, 0xE0, "fchs">;
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defm ABS : FPUnary<fabs, 0xE1, "fabs">;
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defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
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@ -269,6 +274,7 @@ def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
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def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
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}
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def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
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} // Defs = [FPSW]
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// Versions of FP instructions that take a single memory operand. Added for the
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// disassembler; remove as they are included with patterns elsewhere.
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@ -316,6 +322,7 @@ multiclass FPCMov<PatLeaf cc> {
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Requires<[HasCMov]>;
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}
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let Defs = [FPSW] in {
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let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
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defm CMOVB : FPCMov<X86_COND_B>;
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defm CMOVBE : FPCMov<X86_COND_BE>;
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@ -492,15 +499,16 @@ def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
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// Floating point compares.
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let Defs = [EFLAGS] in {
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def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
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[]>; // FPSW = cmp ST(0) with ST(i)
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[(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>;
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def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
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[]>; // FPSW = cmp ST(0) with ST(i)
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[(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>;
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def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
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[]>; // FPSW = cmp ST(0) with ST(i)
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[(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>;
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} // Defs = [FPSW]
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// CC = ST(0) cmp ST(i)
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let Defs = [EFLAGS, FPSW] in {
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def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
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[(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>;
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def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
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@ -509,7 +517,7 @@ def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
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[(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
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}
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let Defs = [EFLAGS], Uses = [ST0] in {
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let Defs = [FPSW], Uses = [ST0] in {
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def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
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(outs), (ins RST:$reg),
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"fucom\t$reg">, DD;
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@ -519,7 +527,9 @@ def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
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def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
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(outs), (ins),
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"fucompp">, DA;
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}
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let Defs = [EFLAGS, FPSW], Uses = [ST0] in {
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def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
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(outs), (ins RST:$reg),
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"fucomi\t$reg">, DB;
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@ -528,15 +538,18 @@ def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
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"fucompi\t$reg">, DF;
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}
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let Defs = [EFLAGS, FPSW] in {
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def COM_FIr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
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"fcomi\t$reg">, DB;
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def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
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"fcompi\t$reg">, DF;
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}
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// Floating point flag ops.
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let Defs = [AX] in
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def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
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(outs), (ins), "fnstsw %ax", []>, DF;
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let Defs = [AX], Uses = [FPSW] in
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def FNSTSW16r : I<0xE0, RawFrm, // AX = fp flags
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(outs), (ins), "fnstsw %ax",
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[(set AX, (X86fp_stsw FPSW))]>, DF;
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def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
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(outs), (ins i16mem:$dst), "fnstcw\t$dst",
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@ -547,12 +560,14 @@ def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
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(outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
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// FPU control instructions
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let Defs = [FPSW] in
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def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
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def FFREE : FPI<0xC0, AddRegFrm, (outs), (ins RST:$reg),
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"ffree\t$reg">, DD;
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// Clear exceptions
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let Defs = [FPSW] in
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def FNCLEX : I<0xE2, RawFrm, (outs), (ins), "fnclex", []>, DB;
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// Operandless floating-point instructions for the disassembler.
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@ -63,6 +63,8 @@ def SDTX86SetCC_C : SDTypeProfile<1, 2,
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[SDTCisInt<0>,
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SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
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def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
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def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
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SDTCisVT<2, i8>]>;
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def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
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@ -131,6 +133,8 @@ def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
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def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
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def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
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def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
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def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
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[SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
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SDNPMayLoad, SDNPMemOperand]>;
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@ -1016,8 +1020,9 @@ def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
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// Condition code ops, incl. set if equal/not equal/...
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let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
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def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
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let Defs = [EFLAGS], Uses = [AH] in
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def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
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[(set EFLAGS, (X86sahf AH))]>;
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let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
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def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
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@ -1774,9 +1779,9 @@ def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
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def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
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// We accept "fnstsw %eax" even though it only writes %ax.
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def : InstAlias<"fnstsw %eax", (FNSTSW8r)>;
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def : InstAlias<"fnstsw %al" , (FNSTSW8r)>;
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def : InstAlias<"fnstsw" , (FNSTSW8r)>;
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def : InstAlias<"fnstsw %eax", (FNSTSW16r)>;
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def : InstAlias<"fnstsw %al" , (FNSTSW16r)>;
|
||||
def : InstAlias<"fnstsw" , (FNSTSW16r)>;
|
||||
|
||||
// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
|
||||
// this is compatible with what GAS does.
|
||||
|
|
|
|||
|
|
@ -223,6 +223,9 @@ let Namespace = "X86" in {
|
|||
def ST6 : STRegister<"st(6)", [FP1]>, DwarfRegNum<[39, 18, 17]>;
|
||||
def ST7 : STRegister<"st(7)", [FP0]>, DwarfRegNum<[40, 19, 18]>;
|
||||
|
||||
// Floating-point status word
|
||||
def FPSW : Register<"fpsw">;
|
||||
|
||||
// Status flags register
|
||||
def EFLAGS : Register<"flags">;
|
||||
|
||||
|
|
@ -472,3 +475,7 @@ def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> {
|
|||
let CopyCost = -1; // Don't allow copying of status registers.
|
||||
let isAllocatable = 0;
|
||||
}
|
||||
def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> {
|
||||
let CopyCost = -1; // Don't allow copying of status registers.
|
||||
let isAllocatable = 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
; RUN: llc < %s -march=x86 -mcpu=pentiumpro | FileCheck %s
|
||||
; PR1012
|
||||
|
||||
define float @foo(float* %col.2.0) {
|
||||
; CHECK: fucompi
|
||||
; CHECK: fcmov
|
||||
%tmp = load float* %col.2.0
|
||||
%tmp16 = fcmp olt float %tmp, 0.000000e+00
|
||||
%tmp20 = fsub float -0.000000e+00, %tmp
|
||||
%iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp
|
||||
ret float %iftmp.2.0
|
||||
}
|
||||
|
|
@ -1,8 +1,11 @@
|
|||
; RUN: llc < %s -march=x86 -mcpu=i386 | FileCheck %s
|
||||
; PR1012
|
||||
; PR6679
|
||||
|
||||
define float @foo(float* %col.2.0) {
|
||||
; CHECK: fucompi
|
||||
; CHECK: fucomp
|
||||
; CHECK-NOT: fucompi
|
||||
; CHECK: j
|
||||
; CHECK-NOT: fcmov
|
||||
%tmp = load float* %col.2.0
|
||||
%tmp16 = fcmp olt float %tmp, 0.000000e+00
|
||||
%tmp20 = fsub float -0.000000e+00, %tmp
|
||||
|
|
|
|||
Loading…
Reference in New Issue