forked from OSchip/llvm-project
Add support for promoting stores from one legal type to another, allowing us
to write one pattern for vector stores instead of 4. llvm-svn: 27730
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@ -1544,6 +1544,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Tmp1 = TLI.LowerOperation(Result, DAG);
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if (Tmp1.Val) Result = Tmp1;
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break;
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case TargetLowering::Promote:
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assert(MVT::isVector(VT) && "Unknown legal promote case!");
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Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
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TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
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Node->getOperand(3));
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break;
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}
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break;
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}
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@ -1576,6 +1583,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
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Node->getOperand(3));
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Result = LegalizeOp(Result);
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break;
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} else if (NumElems == 1) {
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// Turn this into a normal store of the scalar type.
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