forked from OSchip/llvm-project
parent
030e2f8f1a
commit
91118a6155
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@ -752,7 +752,7 @@ class AsmParser {
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def DefaultAsmParser : AsmParser;
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//===----------------------------------------------------------------------===//
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// AsmParserVariant - Subtargets can have multiple different assembly parsers
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// AsmParserVariant - Subtargets can have multiple different assembly parsers
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// (e.g. AT&T vs Intel syntax on X86 for example). This class can be
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// implemented by targets to describe such variants.
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//
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@ -885,7 +885,7 @@ class Target {
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// AssemblyParsers - The AsmParser instances available for this target.
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list<AsmParser> AssemblyParsers = [DefaultAsmParser];
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/// AssemblyParserVariants - The AsmParserVariant instances available for
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/// AssemblyParserVariants - The AsmParserVariant instances available for
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/// this target.
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list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
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@ -155,18 +155,18 @@ Record *CodeGenTarget::getAsmParser() const {
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/// this target.
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///
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Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
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std::vector<Record*> LI =
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std::vector<Record*> LI =
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TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
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if (i >= LI.size())
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throw "Target does not have an AsmParserVariant #" + utostr(i) + "!";
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return LI[i];
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}
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/// getAsmParserVariantCount - Return the AssmblyParserVariant definition
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/// getAsmParserVariantCount - Return the AssmblyParserVariant definition
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/// available for this target.
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///
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unsigned CodeGenTarget::getAsmParserVariantCount() const {
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std::vector<Record*> LI =
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std::vector<Record*> LI =
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TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
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return LI.size();
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}
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