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[RISCV][NFC] Add tests for checking isnan patterns 

Summary:
I worked on adding some SelectionDag patterns to address code generated by these
examples, which came out of some differential testing against GCC. The pattern
additions will be in a follow-up patch.

Reviewers: luismarques, asb

Reviewed By: luismarques, asb

Differential Revision: https://reviews.llvm.org/D78907
This commit is contained in:
Sam Elliott 2020-05-02 14:56:35 +01:00
parent d10c995b4d
commit 910ca0e435
2 changed files with 78 additions and 0 deletions
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39
llvm/test/CodeGen/RISCV/double-isnan.ll Normal file
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@ -0,0 +1,39 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV64IFD %s
define zeroext i1 @double_is_nan(double %a) nounwind {
; RV32IFD-LABEL: double_is_nan:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: feq.d a0, fa0, fa0
; RV32IFD-NEXT: and a0, a0, a0
; RV32IFD-NEXT: seqz a0, a0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: double_is_nan:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
; RV64IFD-NEXT: and a0, a0, a0
; RV64IFD-NEXT: seqz a0, a0
; RV64IFD-NEXT: ret
%1 = fcmp uno double %a, 0.000000e+00
ret i1 %1
}
define zeroext i1 @double_not_nan(double %a) nounwind {
; RV32IFD-LABEL: double_not_nan:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: feq.d a0, fa0, fa0
; RV32IFD-NEXT: and a0, a0, a0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: double_not_nan:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
; RV64IFD-NEXT: and a0, a0, a0
; RV64IFD-NEXT: ret
%1 = fcmp ord double %a, 0.000000e+00
ret i1 %1
}

39
llvm/test/CodeGen/RISCV/float-isnan.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV64IF %s
define zeroext i1 @float_is_nan(float %a) nounwind {
; RV32IF-LABEL: float_is_nan:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: and a0, a0, a0
; RV32IF-NEXT: seqz a0, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: float_is_nan:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: and a0, a0, a0
; RV64IF-NEXT: seqz a0, a0
; RV64IF-NEXT: ret
%1 = fcmp uno float %a, 0.000000e+00
ret i1 %1
}
define zeroext i1 @float_not_nan(float %a) nounwind {
; RV32IF-LABEL: float_not_nan:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: and a0, a0, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: float_not_nan:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: and a0, a0, a0
; RV64IF-NEXT: ret
%1 = fcmp ord float %a, 0.000000e+00
ret i1 %1
}