forked from OSchip/llvm-project
[GlobalISel][InlineAsm] Add support for basic input operand constraints
Reviewers: arsenm, dsanders, aemerson, volkan, t.p.northover, paquette Reviewed By: arsenm Subscribers: gargaroff, wdng, rovka, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78319
This commit is contained in:
Konstantin Schwarz
parent
104e38cf76
commit
91063cf85a
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@ -20,6 +20,7 @@
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namespace llvm {
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class CallBase;
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class MachineIRBuilder;
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class MachineOperand;
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class Register;
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class TargetLowering;
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class Value;
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@ -30,10 +31,23 @@ class InlineAsmLowering {
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virtual void anchor();
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public:
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/// Lower the given inline asm call instruction
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/// \p GetOrCreateVRegs is a callback to materialize a register for the
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/// input and output operands of the inline asm
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/// \return True if the lowering succeeds, false otherwise.
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bool lowerInlineAsm(MachineIRBuilder &MIRBuilder, const CallBase &CB,
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std::function<ArrayRef<Register>(const Value &Val)>
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GetOrCreateVRegs) const;
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/// Lower the specified operand into the Ops vector.
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/// \p Val is the IR input value to be lowered
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/// \p Constraint is the user supplied constraint string
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/// \p Ops is the vector to be filled with the lowered operands
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/// \return True if the lowering succeeds, false otherwise.
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virtual bool lowerAsmOperandForConstraint(Value *Val, StringRef Constraint,
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std::vector<MachineOperand> &Ops,
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MachineIRBuilder &MIRBuilder) const;
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protected:
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/// Getter for generic TargetLowering class.
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const TargetLowering *getTLI() const { return TLI; }
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@ -252,6 +252,7 @@ bool InlineAsmLowering::lowerInlineAsm(
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TLI->ParseConstraints(DL, TRI, Call);
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ExtraFlags ExtraInfo(Call);
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unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
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unsigned ResNo = 0; // ResNo - The result number of the next output.
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for (auto &T : TargetConstraints) {
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ConstraintOperands.push_back(GISelAsmOperandInfo(T));
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@ -261,9 +262,32 @@ bool InlineAsmLowering::lowerInlineAsm(
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if (OpInfo.Type == InlineAsm::isInput ||
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(OpInfo.Type == InlineAsm::isOutput && OpInfo.isIndirect)) {
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LLVM_DEBUG(dbgs() << "Input operands and indirect output operands are "
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"not supported yet\n");
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return false;
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OpInfo.CallOperandVal = const_cast<Value *>(Call.getArgOperand(ArgNo++));
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if (const auto *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
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LLVM_DEBUG(dbgs() << "Basic block input operands not supported yet\n");
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return false;
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}
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Type *OpTy = OpInfo.CallOperandVal->getType();
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// If this is an indirect operand, the operand is a pointer to the
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// accessed type.
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if (OpInfo.isIndirect) {
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PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
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if (!PtrTy)
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report_fatal_error("Indirect operand for inline asm not a pointer!");
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OpTy = PtrTy->getElementType();
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}
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// FIXME: Support aggregate input operands
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if (!OpTy->isSingleValueType()) {
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LLVM_DEBUG(
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dbgs() << "Aggregate input operands are not supported yet\n");
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return false;
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}
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OpInfo.ConstraintVT = TLI->getValueType(DL, OpTy, true).getSimpleVT();
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} else if (OpInfo.Type == InlineAsm::isOutput && !OpInfo.isIndirect) {
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assert(!Call.getType()->isVoidTy() && "Bad inline asm!");
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@ -363,8 +387,97 @@ bool InlineAsmLowering::lowerInlineAsm(
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}
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break;
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case InlineAsm::isInput:
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return false;
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case InlineAsm::isInput: {
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if (OpInfo.isMatchingInputConstraint()) {
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LLVM_DEBUG(dbgs() << "Tied input operands not supported yet\n");
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return false;
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}
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if (OpInfo.ConstraintType == TargetLowering::C_Other &&
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OpInfo.isIndirect) {
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LLVM_DEBUG(dbgs() << "Indirect input operands with unknown constraint "
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"not supported yet\n");
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return false;
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}
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if (OpInfo.ConstraintType == TargetLowering::C_Immediate ||
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OpInfo.ConstraintType == TargetLowering::C_Other) {
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std::vector<MachineOperand> Ops;
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if (!lowerAsmOperandForConstraint(OpInfo.CallOperandVal,
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OpInfo.ConstraintCode, Ops,
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MIRBuilder)) {
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LLVM_DEBUG(dbgs() << "Don't support constraint: "
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<< OpInfo.ConstraintCode << " yet\n");
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return false;
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}
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assert(Ops.size() > 0 &&
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"Expected constraint to be lowered to at least one operand");
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// Add information to the INLINEASM node to know about this input.
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unsigned OpFlags =
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InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
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Inst.addImm(OpFlags);
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Inst.add(Ops);
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break;
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}
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if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
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assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
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unsigned ConstraintID =
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TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
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unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
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OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
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Inst.addImm(OpFlags);
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ArrayRef<Register> SourceRegs =
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GetOrCreateVRegs(*OpInfo.CallOperandVal);
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assert(
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SourceRegs.size() == 1 &&
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"Expected the memory input to fit into a single virtual register");
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Inst.addReg(SourceRegs[0]);
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break;
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}
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assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
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OpInfo.ConstraintType == TargetLowering::C_Register) &&
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"Unknown constraint type!");
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if (OpInfo.isIndirect) {
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LLVM_DEBUG(dbgs() << "Can't handle indirect register inputs yet "
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"for constraint '"
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<< OpInfo.ConstraintCode << "'\n");
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return false;
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}
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// Copy the input into the appropriate registers.
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if (OpInfo.Regs.empty()) {
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LLVM_DEBUG(
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dbgs()
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<< "Couldn't allocate input register for register constraint\n");
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return false;
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}
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unsigned NumRegs = OpInfo.Regs.size();
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ArrayRef<Register> SourceRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal);
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assert(NumRegs == SourceRegs.size() &&
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"Expected the number of input registers to match the number of "
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"source registers");
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if (NumRegs > 1) {
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LLVM_DEBUG(dbgs() << "Input operands with multiple input registers are "
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"not supported yet\n");
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return false;
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}
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unsigned Flag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, NumRegs);
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Inst.addImm(Flag);
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MIRBuilder.buildCopy(OpInfo.Regs[0], SourceRegs[0]);
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Inst.addReg(OpInfo.Regs[0]);
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break;
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}
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case InlineAsm::isClobber: {
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unsigned NumRegs = OpInfo.Regs.size();
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@ -441,3 +554,27 @@ bool InlineAsmLowering::lowerInlineAsm(
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return true;
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}
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bool InlineAsmLowering::lowerAsmOperandForConstraint(
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Value *Val, StringRef Constraint, std::vector<MachineOperand> &Ops,
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MachineIRBuilder &MIRBuilder) const {
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if (Constraint.size() > 1)
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return false;
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char ConstraintLetter = Constraint[0];
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switch (ConstraintLetter) {
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default:
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return false;
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case 'i': // Simple Integer or Relocatable Constant
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if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
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assert(CI->getBitWidth() <= 64 &&
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"expected immediate to fit into 64-bits");
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// Boolean constants should be zero-extended, others are sign-extended
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bool IsBool = CI->getBitWidth() == 1;
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int64_t ExtVal = IsBool ? CI->getZExtValue() : CI->getSExtValue();
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Ops.push_back(MachineOperand::CreateImm(ExtVal));
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return true;
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}
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return false;
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}
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}
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@ -132,3 +132,66 @@ define float @test_vector_output() nounwind {
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%2 = extractelement <2 x float> %1, i32 0
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ret float %2
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}
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define void @test_input_register_imm() {
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; CHECK-LABEL: name: test_input_register_imm
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
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; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY [[C]](s64)
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; CHECK: INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, 9 /* reguse */, [[COPY]]
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; CHECK: RET_ReallyLR
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call void asm sideeffect "mov x0, $0", "r"(i64 42)
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ret void
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}
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; Make sure that boolean immediates are properly (zero) extended.
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define i32 @test_boolean_imm_ext() {
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; CHECK-LABEL: name: test_boolean_imm_ext
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; CHECK: bb.1.entry:
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK: INLINEASM &"#TEST 42 + ${0:c} - .\0A\09", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 1
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; CHECK: $w0 = COPY [[C]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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entry:
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tail call void asm sideeffect "#TEST 42 + ${0:c} - .\0A\09", "i"(i1 true)
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ret i32 1
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}
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define void @test_input_imm() {
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; CHECK-LABEL: name: test_input_imm
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: INLINEASM &"mov x0, $0", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42
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; CHECK: RET_ReallyLR
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call void asm sideeffect "mov x0, $0", "i"(i64 42)
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ret void
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}
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define zeroext i8 @test_input_register(i8* %src) nounwind {
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; CHECK-LABEL: name: test_input_register
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; CHECK: bb.1.entry:
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]](p0)
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; CHECK: INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %1, 9 /* reguse */, [[COPY1]]
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY %1
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; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
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; CHECK: $w0 = COPY [[ZEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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entry:
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%0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(i8* %src) nounwind
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ret i8 %0
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}
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define i32 @test_memory_constraint(i32* %a) nounwind {
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; CHECK-LABEL: name: test_memory_constraint
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, 655370 /* regdef:GPR32common */, def %1, 196622 /* mem:m */, [[COPY]](p0)
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
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; CHECK: $w0 = COPY [[COPY1]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%1 = tail call i32 asm "ldr $0, $1", "=r,*m"(i32* %a)
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ret i32 %1
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}
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