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[RISCV] Regenerate several tests now enableMultipleCopyHints is enabled by default 

r343851 caused codegen changes in several tests. This patch regenerates them.

llvm-svn: 343873
This commit is contained in:
Alex Bradbury 2018-10-05 18:25:55 +00:00
parent 208661b206
commit 90fc100742
3 changed files with 60 additions and 60 deletions
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42
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
View File

@ -537,13 +537,13 @@ define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
@ -578,13 +578,13 @@ define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a5, zero, 3
; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
@ -599,14 +599,14 @@ define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a6, zero, 3
; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: mv a4, a6
; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@ -620,13 +620,13 @@ define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a5, zero, 4
; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
@ -641,14 +641,14 @@ define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a6, zero, 4
; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: mv a4, a6
; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@ -662,13 +662,13 @@ define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
@ -683,14 +683,14 @@ define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a6, zero, 5
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: mv a4, a6
; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16

2
llvm/test/CodeGen/RISCV/double-select-fcmp.ll
View File

@ -5,8 +5,8 @@
define double @select_fcmp_false(double %a, double %b) nounwind {
; RV32IFD-LABEL: select_fcmp_false:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: mv a0, a2
; RV32IFD-NEXT: mv a1, a3
; RV32IFD-NEXT: mv a0, a2
; RV32IFD-NEXT: ret
%1 = fcmp false double %a, %b
%2 = select i1 %1, double %a, double %b

76
llvm/test/CodeGen/RISCV/vararg.ll
View File

@ -367,21 +367,21 @@ define double @va3(i32 %a, double %b, ...) nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 4(sp)
; RV32I-FPELIM-NEXT: mv t0, a2
; RV32I-FPELIM-NEXT: mv a0, a1
; RV32I-FPELIM-NEXT: sw a7, 28(sp)
; RV32I-FPELIM-NEXT: sw a6, 24(sp)
; RV32I-FPELIM-NEXT: sw a5, 20(sp)
; RV32I-FPELIM-NEXT: sw a4, 16(sp)
; RV32I-FPELIM-NEXT: sw a3, 12(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 27
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 19
; RV32I-FPELIM-NEXT: andi a0, a0, -8
; RV32I-FPELIM-NEXT: lw a4, 0(a0)
; RV32I-FPELIM-NEXT: ori a0, a0, 4
; RV32I-FPELIM-NEXT: lw a3, 0(a0)
; RV32I-FPELIM-NEXT: mv a0, a1
; RV32I-FPELIM-NEXT: mv a1, a2
; RV32I-FPELIM-NEXT: mv a2, a4
; RV32I-FPELIM-NEXT: addi a1, sp, 27
; RV32I-FPELIM-NEXT: sw a1, 0(sp)
; RV32I-FPELIM-NEXT: addi a1, sp, 19
; RV32I-FPELIM-NEXT: andi a1, a1, -8
; RV32I-FPELIM-NEXT: lw a2, 0(a1)
; RV32I-FPELIM-NEXT: ori a1, a1, 4
; RV32I-FPELIM-NEXT: lw a3, 0(a1)
; RV32I-FPELIM-NEXT: mv a1, t0
; RV32I-FPELIM-NEXT: call __adddf3
; RV32I-FPELIM-NEXT: lw ra, 4(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32
@ -393,21 +393,21 @@ define double @va3(i32 %a, double %b, ...) nounwind {
; RV32I-WITHFP-NEXT: sw ra, 20(sp)
; RV32I-WITHFP-NEXT: sw s0, 16(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 24
; RV32I-WITHFP-NEXT: mv t0, a2
; RV32I-WITHFP-NEXT: mv a0, a1
; RV32I-WITHFP-NEXT: sw a7, 20(s0)
; RV32I-WITHFP-NEXT: sw a6, 16(s0)
; RV32I-WITHFP-NEXT: sw a5, 12(s0)
; RV32I-WITHFP-NEXT: sw a4, 8(s0)
; RV32I-WITHFP-NEXT: sw a3, 4(s0)
; RV32I-WITHFP-NEXT: addi a0, s0, 19
; RV32I-WITHFP-NEXT: sw a0, -12(s0)
; RV32I-WITHFP-NEXT: addi a0, s0, 11
; RV32I-WITHFP-NEXT: andi a0, a0, -8
; RV32I-WITHFP-NEXT: lw a4, 0(a0)
; RV32I-WITHFP-NEXT: ori a0, a0, 4
; RV32I-WITHFP-NEXT: lw a3, 0(a0)
; RV32I-WITHFP-NEXT: mv a0, a1
; RV32I-WITHFP-NEXT: mv a1, a2
; RV32I-WITHFP-NEXT: mv a2, a4
; RV32I-WITHFP-NEXT: addi a1, s0, 19
; RV32I-WITHFP-NEXT: sw a1, -12(s0)
; RV32I-WITHFP-NEXT: addi a1, s0, 11
; RV32I-WITHFP-NEXT: andi a1, a1, -8
; RV32I-WITHFP-NEXT: lw a2, 0(a1)
; RV32I-WITHFP-NEXT: ori a1, a1, 4
; RV32I-WITHFP-NEXT: lw a3, 0(a1)
; RV32I-WITHFP-NEXT: mv a1, t0
; RV32I-WITHFP-NEXT: call __adddf3
; RV32I-WITHFP-NEXT: lw s0, 16(sp)
; RV32I-WITHFP-NEXT: lw ra, 20(sp)
@ -435,22 +435,22 @@ define double @va3_va_arg(i32 %a, double %b, ...) nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 4(sp)
; RV32I-FPELIM-NEXT: mv t0, a2
; RV32I-FPELIM-NEXT: mv a0, a1
; RV32I-FPELIM-NEXT: sw a7, 28(sp)
; RV32I-FPELIM-NEXT: sw a6, 24(sp)
; RV32I-FPELIM-NEXT: sw a5, 20(sp)
; RV32I-FPELIM-NEXT: sw a4, 16(sp)
; RV32I-FPELIM-NEXT: sw a3, 12(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 19
; RV32I-FPELIM-NEXT: andi a0, a0, -8
; RV32I-FPELIM-NEXT: ori a3, a0, 4
; RV32I-FPELIM-NEXT: addi a1, sp, 19
; RV32I-FPELIM-NEXT: andi a1, a1, -8
; RV32I-FPELIM-NEXT: ori a3, a1, 4
; RV32I-FPELIM-NEXT: sw a3, 0(sp)
; RV32I-FPELIM-NEXT: lw a4, 0(a0)
; RV32I-FPELIM-NEXT: addi a0, a3, 4
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
; RV32I-FPELIM-NEXT: lw a2, 0(a1)
; RV32I-FPELIM-NEXT: addi a1, a3, 4
; RV32I-FPELIM-NEXT: sw a1, 0(sp)
; RV32I-FPELIM-NEXT: lw a3, 0(a3)
; RV32I-FPELIM-NEXT: mv a0, a1
; RV32I-FPELIM-NEXT: mv a1, a2
; RV32I-FPELIM-NEXT: mv a2, a4
; RV32I-FPELIM-NEXT: mv a1, t0
; RV32I-FPELIM-NEXT: call __adddf3
; RV32I-FPELIM-NEXT: lw ra, 4(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32
@ -462,22 +462,22 @@ define double @va3_va_arg(i32 %a, double %b, ...) nounwind {
; RV32I-WITHFP-NEXT: sw ra, 20(sp)
; RV32I-WITHFP-NEXT: sw s0, 16(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 24
; RV32I-WITHFP-NEXT: mv t0, a2
; RV32I-WITHFP-NEXT: mv a0, a1
; RV32I-WITHFP-NEXT: sw a7, 20(s0)
; RV32I-WITHFP-NEXT: sw a6, 16(s0)
; RV32I-WITHFP-NEXT: sw a5, 12(s0)
; RV32I-WITHFP-NEXT: sw a4, 8(s0)
; RV32I-WITHFP-NEXT: sw a3, 4(s0)
; RV32I-WITHFP-NEXT: addi a0, s0, 11
; RV32I-WITHFP-NEXT: andi a0, a0, -8
; RV32I-WITHFP-NEXT: ori a3, a0, 4
; RV32I-WITHFP-NEXT: addi a1, s0, 11
; RV32I-WITHFP-NEXT: andi a1, a1, -8
; RV32I-WITHFP-NEXT: ori a3, a1, 4
; RV32I-WITHFP-NEXT: sw a3, -12(s0)
; RV32I-WITHFP-NEXT: lw a4, 0(a0)
; RV32I-WITHFP-NEXT: addi a0, a3, 4
; RV32I-WITHFP-NEXT: sw a0, -12(s0)
; RV32I-WITHFP-NEXT: lw a2, 0(a1)
; RV32I-WITHFP-NEXT: addi a1, a3, 4
; RV32I-WITHFP-NEXT: sw a1, -12(s0)
; RV32I-WITHFP-NEXT: lw a3, 0(a3)
; RV32I-WITHFP-NEXT: mv a0, a1
; RV32I-WITHFP-NEXT: mv a1, a2
; RV32I-WITHFP-NEXT: mv a2, a4
; RV32I-WITHFP-NEXT: mv a1, t0
; RV32I-WITHFP-NEXT: call __adddf3
; RV32I-WITHFP-NEXT: lw s0, 16(sp)
; RV32I-WITHFP-NEXT: lw ra, 20(sp)