forked from OSchip/llvm-project
[LegalizeVectorTypes] Remove a tautological compare.
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@ -1268,7 +1268,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
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// vector, and insert into the lower half of the split vector directly.
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// Similarly if the subvector is fully in the high half.
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unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
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if (IdxVal >= 0 && IdxVal + SubElems <= LoElems) {
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if (IdxVal + SubElems <= LoElems) {
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Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
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return;
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}
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