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[MC] Minor cleanup to MCFixup::Kind handling. NFC. 

Prefer `MCFixupKind` where possible and add getTargetKind() to
convert to `unsigned` when needed rather than scattering cast
operators around the place.

Differential Revision: https://reviews.llvm.org/D59890

llvm-svn: 369720
This commit is contained in:
Sam Clegg 2019-08-23 01:00:55 +00:00
parent 926f4f76c3
commit 90b6bb75e8
20 changed files with 49 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
llvm/include/llvm/MC/MCFixup.h
View File

@ -85,18 +85,18 @@ class MCFixup {
/// The target dependent kind of fixup item this is. The kind is used to
/// determine how the operand value should be encoded into the instruction.
unsigned Kind = 0;
MCFixupKind Kind = FK_NONE;
/// The source location which gave rise to the fixup, if any.
SMLoc Loc;
public:
static MCFixup create(uint32_t Offset, const MCExpr *Value,
MCFixupKind Kind, SMLoc Loc = SMLoc()) {
assert(unsigned(Kind) < MaxTargetFixupKind && "Kind out of range!");
assert(Kind < MaxTargetFixupKind && "Kind out of range!");
MCFixup FI;
FI.Value = Value;
FI.Offset = Offset;
FI.Kind = unsigned(Kind);
FI.Kind = Kind;
FI.Loc = Loc;
return FI;
}
@ -107,7 +107,7 @@ public:
MCFixup FI;
FI.Value = Fixup.getValue();
FI.Offset = Fixup.getOffset();
FI.Kind = (unsigned)getAddKindForKind(Fixup.getKind());
FI.Kind = getAddKindForKind(Fixup.getKind());
FI.Loc = Fixup.getLoc();
return FI;
}
@ -118,12 +118,14 @@ public:
MCFixup FI;
FI.Value = Fixup.getValue();
FI.Offset = Fixup.getOffset();
FI.Kind = (unsigned)getSubKindForKind(Fixup.getKind());
FI.Kind = getSubKindForKind(Fixup.getKind());
FI.Loc = Fixup.getLoc();
return FI;
}
MCFixupKind getKind() const { return MCFixupKind(Kind); }
MCFixupKind getKind() const { return Kind; }
unsigned getTargetKind() const { return Kind; }
uint32_t getOffset() const { return Offset; }
void setOffset(uint32_t Value) { Offset = Value; }
@ -168,7 +170,7 @@ public:
/// Return the generic fixup kind for an addition with a given size. It
/// is an error to pass an unsupported size.
static MCFixupKind getAddKindForKind(unsigned Kind) {
static MCFixupKind getAddKindForKind(MCFixupKind Kind) {
switch (Kind) {
default: llvm_unreachable("Unknown type to convert!");
case FK_Data_1: return FK_Data_Add_1;
@ -181,7 +183,7 @@ public:
/// Return the generic fixup kind for an subtraction with a given size. It
/// is an error to pass an unsupported size.
static MCFixupKind getSubKindForKind(unsigned Kind) {
static MCFixupKind getSubKindForKind(MCFixupKind Kind) {
switch (Kind) {
default: llvm_unreachable("Unknown type to convert!");
case FK_Data_1: return FK_Data_Sub_1;

3
llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
View File

@ -153,9 +153,8 @@ static unsigned AdrImmBits(unsigned Value) {
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target,
uint64_t Value, MCContext &Ctx,
const Triple &TheTriple, bool IsResolved) {
unsigned Kind = Fixup.getKind();
int64_t SignedValue = static_cast<int64_t>(Value);
switch (Kind) {
switch (Fixup.getTargetKind()) {
default:
llvm_unreachable("Unknown fixup kind!");
case AArch64::fixup_aarch64_pcrel_adr_imm21:

6
llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
View File

@ -57,7 +57,7 @@ AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
static bool isNonILP32reloc(const MCFixup &Fixup,
AArch64MCExpr::VariantKind RefKind,
MCContext &Ctx) {
if ((unsigned)Fixup.getKind() != AArch64::fixup_aarch64_movw)
if (Fixup.getTargetKind() != AArch64::fixup_aarch64_movw)
return false;
switch (RefKind) {
case AArch64MCExpr::VK_ABS_G3:
@ -120,7 +120,7 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
"Should only be expression-level modifiers here");
if (IsPCRel) {
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
case FK_Data_1:
Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
return ELF::R_AARCH64_NONE;
@ -184,7 +184,7 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
} else {
if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx))
return ELF::R_AARCH64_NONE;
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
case FK_NONE:
return ELF::R_AARCH64_NONE;
case FK_Data_1:

2
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
View File

@ -54,7 +54,7 @@ bool AArch64MachObjectWriter::getAArch64FixupKindMachOInfo(
RelocType = unsigned(MachO::ARM64_RELOC_UNSIGNED);
Log2Size = ~0U;
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
default:
return false;

2
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
View File

@ -109,7 +109,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
MCContext *Ctx) {
int64_t SignedValue = static_cast<int64_t>(Value);
switch (static_cast<unsigned>(Fixup.getKind())) {
switch (Fixup.getTargetKind()) {
case AMDGPU::fixup_si_sopp_br: {
int64_t BrImm = (SignedValue - 4) / 4;

4
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
View File

@ -233,7 +233,7 @@ static const char *checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max) {
const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup,
uint64_t Value) const {
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
case ARM::fixup_arm_thumb_br: {
// Relaxing tB to t2B. tB has a signed 12-bit displacement with the
// low bit being an implied zero. There's an implied +4 offset for the
@ -870,7 +870,7 @@ bool ARMAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
const MCValue &Target) {
const MCSymbolRefExpr *A = Target.getSymA();
const MCSymbol *Sym = A ? &A->getSymbol() : nullptr;
const unsigned FixupKind = Fixup.getKind() ;
const unsigned FixupKind = Fixup.getKind();
if (FixupKind == FK_NONE)
return true;
if (FixupKind == ARM::fixup_arm_thumb_bl) {

4
llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
View File

@ -82,7 +82,7 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant();
if (IsPCRel) {
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
default:
Ctx.reportFatalError(Fixup.getLoc(), "unsupported relocation on symbol");
return ELF::R_ARM_NONE;
@ -145,7 +145,7 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
return ELF::R_ARM_THM_BF18;
}
}
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
default:
Ctx.reportFatalError(Fixup.getLoc(), "unsupported relocation on symbol");
return ELF::R_ARM_NONE;

4
llvm/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
View File

@ -204,7 +204,7 @@ RecordARMScatteredHalfRelocation(MachObjectWriter *Writer,
// relocation entry in the low 16 bits of r_address field.
unsigned ThumbBit = 0;
unsigned MovtBit = 0;
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
default: break;
case ARM::fixup_arm_movt_hi16:
MovtBit = 1;
@ -480,7 +480,7 @@ void ARMMachObjectWriter::recordRelocation(MachObjectWriter *Writer,
// PAIR. I.e. it's correct that we insert the high bits of the addend in the
// MOVW case here. relocation entries.
uint32_t Value = 0;
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
default: break;
case ARM::fixup_arm_movw_lo16:
case ARM::fixup_t2_movw_lo16:

2
llvm/lib/Target/BPF/MCTargetDesc/BPFELFObjectWriter.cpp
View File

@ -39,7 +39,7 @@ unsigned BPFELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const {
// determine the type of the relocation
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getKind()) {
default:
llvm_unreachable("invalid fixup kind!");
case FK_SecRel_8:

6
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
View File

@ -201,9 +201,7 @@ public:
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
const MCValue &Target) override {
MCFixupKind Kind = Fixup.getKind();
switch((unsigned)Kind) {
switch(Fixup.getTargetKind()) {
default:
llvm_unreachable("Unknown Fixup Kind!");
@ -583,7 +581,7 @@ public:
return false;
// If we cannot resolve the fixup value, it requires relaxation.
if (!Resolved) {
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
case fixup_Hexagon_B22_PCREL:
// GetFixupCount assumes B22 won't relax
LLVM_FALLTHROUGH;

2
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
View File

@ -44,7 +44,7 @@ unsigned HexagonELFObjectWriter::getRelocType(MCContext &Ctx,
MCFixup const &Fixup,
bool IsPCRel) const {
MCSymbolRefExpr::VariantKind Variant = Target.getAccessVariant();
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
default:
report_fatal_error("Unrecognized relocation type");
break;

2
llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFObjectWriter.cpp
View File

@ -31,7 +31,7 @@ protected:
unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
const MCFixup &Fixup, bool IsPCRel) const override {
// Translate fixup kind to ELF relocation type.
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
case FK_Data_1: return ELF::R_MSP430_8;
case FK_Data_2: return ELF::R_MSP430_16_BYTE;
case FK_Data_4: return ELF::R_MSP430_32;

2
llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
View File

@ -219,7 +219,7 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx,
const MCFixup &Fixup,
bool IsPCRel) const {
// Determine the type of the relocation.
unsigned Kind = (unsigned)Fixup.getKind();
unsigned Kind = Fixup.getTargetKind();
switch (Kind) {
case FK_NONE:

4
llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
View File

@ -78,7 +78,7 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
// determine the type of the relocation
unsigned Type;
if (IsPCRel) {
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
default:
llvm_unreachable("Unimplemented");
case PPC::fixup_ppc_br24:
@ -131,7 +131,7 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
break;
}
} else {
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
default: llvm_unreachable("invalid fixup kind!");
case FK_NONE:
Type = ELF::R_PPC_NONE;

2
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp
View File

@ -178,7 +178,7 @@ static uint32_t getFixupOffset(const MCAsmLayout &Layout,
uint32_t FixupOffset = Layout.getFragmentOffset(Fragment) + Fixup.getOffset();
// On Mach-O, ppc_fixup_half16 relocations must refer to the
// start of the instruction, not the second halfword, as ELF does
if (unsigned(Fixup.getKind()) == PPC::fixup_ppc_half16)
if (Fixup.getTargetKind() == PPC::fixup_ppc_half16)
FixupOffset &= ~uint32_t(3);
return FixupOffset;
}

9
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
View File

@ -30,7 +30,7 @@ bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
const MCValue &Target) {
bool ShouldForce = false;
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
default:
break;
case FK_Data_1:
@ -55,7 +55,7 @@ bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
return false;
}
switch ((unsigned)T->getKind()) {
switch (T->getTargetKind()) {
default:
llvm_unreachable("Unexpected fixup kind for pcrel_lo12");
break;
@ -90,7 +90,7 @@ bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
return true;
int64_t Offset = int64_t(Value);
switch ((unsigned)Fixup.getKind()) {
switch (Fixup.getTargetKind()) {
default:
return false;
case RISCV::fixup_riscv_rvc_branch:
@ -181,8 +181,7 @@ bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
MCContext &Ctx) {
unsigned Kind = Fixup.getKind();
switch (Kind) {
switch (Fixup.getTargetKind()) {
default:
llvm_unreachable("Unknown fixup kind!");
case RISCV::fixup_riscv_got_hi20:

2
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
View File

@ -50,7 +50,7 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
bool IsPCRel) const {
const MCExpr *Expr = Fixup.getValue();
// Determine the type of the relocation
unsigned Kind = Fixup.getKind();
unsigned Kind = Fixup.getTargetKind();
if (IsPCRel) {
switch (Kind) {
default:

4
llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
View File

@ -49,7 +49,7 @@ unsigned SparcELFObjectWriter::getRelocType(MCContext &Ctx,
}
if (IsPCRel) {
switch((unsigned)Fixup.getKind()) {
switch(Fixup.getTargetKind()) {
default:
llvm_unreachable("Unimplemented fixup -> relocation");
case FK_Data_1: return ELF::R_SPARC_DISP8;
@ -65,7 +65,7 @@ unsigned SparcELFObjectWriter::getRelocType(MCContext &Ctx,
}
}
switch((unsigned)Fixup.getKind()) {
switch(Fixup.getTargetKind()) {
default:
llvm_unreachable("Unimplemented fixup -> relocation");
case FK_Data_1: return ELF::R_SPARC_8;

17
llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
View File

@ -46,10 +46,10 @@ X86ELFObjectWriter::X86ELFObjectWriter(bool IsELF64, uint8_t OSABI,
enum X86_64RelType { RT64_NONE, RT64_64, RT64_32, RT64_32S, RT64_16, RT64_8 };
static X86_64RelType getType64(unsigned Kind,
static X86_64RelType getType64(MCFixupKind Kind,
MCSymbolRefExpr::VariantKind &Modifier,
bool &IsPCRel) {
switch (Kind) {
switch (unsigned(Kind)) {
default:
llvm_unreachable("Unimplemented");
case FK_NONE:
@ -97,7 +97,7 @@ static void checkIs32(MCContext &Ctx, SMLoc Loc, X86_64RelType Type) {
static unsigned getRelocType64(MCContext &Ctx, SMLoc Loc,
MCSymbolRefExpr::VariantKind Modifier,
X86_64RelType Type, bool IsPCRel,
unsigned Kind) {
MCFixupKind Kind) {
switch (Modifier) {
default:
llvm_unreachable("Unimplemented");
@ -202,7 +202,7 @@ static unsigned getRelocType64(MCContext &Ctx, SMLoc Loc,
// and we want to keep back-compatibility.
if (!Ctx.getAsmInfo()->canRelaxRelocations())
return ELF::R_X86_64_GOTPCREL;
switch (Kind) {
switch (unsigned(Kind)) {
default:
return ELF::R_X86_64_GOTPCREL;
case X86::reloc_riprel_4byte_relax:
@ -237,7 +237,7 @@ static X86_32RelType getType32(X86_64RelType T) {
static unsigned getRelocType32(MCContext &Ctx,
MCSymbolRefExpr::VariantKind Modifier,
X86_32RelType Type, bool IsPCRel,
unsigned Kind) {
MCFixupKind Kind) {
switch (Modifier) {
default:
llvm_unreachable("Unimplemented");
@ -265,8 +265,9 @@ static unsigned getRelocType32(MCContext &Ctx,
if (!Ctx.getAsmInfo()->canRelaxRelocations())
return ELF::R_386_GOT32;
return Kind == X86::reloc_signed_4byte_relax ? ELF::R_386_GOT32X
: ELF::R_386_GOT32;
return Kind == MCFixupKind(X86::reloc_signed_4byte_relax)
? ELF::R_386_GOT32X
: ELF::R_386_GOT32;
case MCSymbolRefExpr::VK_GOTOFF:
assert(Type == RT32_32);
assert(!IsPCRel);
@ -317,7 +318,7 @@ unsigned X86ELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const {
MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant();
unsigned Kind = Fixup.getKind();
MCFixupKind Kind = Fixup.getKind();
X86_64RelType Type = getType64(Kind, Modifier, IsPCRel);
if (getEMachine() == ELF::EM_X86_64)
return getRelocType64(Ctx, Fixup.getLoc(), Modifier, Type, IsPCRel, Kind);

5
llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
View File

@ -276,7 +276,7 @@ void X86MachObjectWriter::RecordX86_64Relocation(
// x86_64 distinguishes movq foo@GOTPCREL so that the linker can
// rewrite the movq to an leaq at link time if the symbol ends up in
// the same linkage unit.
if (unsigned(Fixup.getKind()) == X86::reloc_riprel_4byte_movq_load)
if (Fixup.getTargetKind() == X86::reloc_riprel_4byte_movq_load)
Type = MachO::X86_64_RELOC_GOT_LOAD;
else
Type = MachO::X86_64_RELOC_GOT;
@ -339,8 +339,7 @@ void X86MachObjectWriter::RecordX86_64Relocation(
return;
} else {
Type = MachO::X86_64_RELOC_UNSIGNED;
unsigned Kind = Fixup.getKind();
if (Kind == X86::reloc_signed_4byte) {
if (Fixup.getTargetKind() == X86::reloc_signed_4byte) {
Asm.getContext().reportError(
Fixup.getLoc(),
"32-bit absolute addressing is not supported in 64-bit mode");