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[AArch64][SVE] Asm: Add support for RDVL/ADDVL/ADDPL instructions 

Reviewers: fhahn, rengolin, t.p.northover, echristo, olista01, SjoerdMeijer

Reviewed By: SjoerdMeijer

Subscribers: SjoerdMeijer, aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D41900

llvm-svn: 322951
This commit is contained in:
Sander de Smalen 2018-01-19 15:22:00 +00:00
parent 372c3f1f99
commit 909cf956a1
10 changed files with 186 additions and 1 deletions
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6
llvm/lib/Target/AArch64/AArch64InstrFormats.td
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@ -241,6 +241,12 @@ def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
let DecoderMethod = "DecodeSImm<9>";
}
def SImm6Operand : SImmOperand<6>;
def simm6_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -32 && Imm < 32; }]> {
let ParserMatchClass = SImm6Operand;
let DecoderMethod = "DecodeSImm<6>";
}
// simm7sN predicate - True if the immediate is a multiple of N in the range
// [-64 * N, 63 * N].
class SImm7Scaled<int Scale> : AsmOperandClass {

4
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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@ -25,4 +25,8 @@ let Predicates = [HasSVE] in {
defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">;
defm DUP_ZR : sve_int_perm_dup_r<"dup">;
def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">;
def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">;
def ADDPL_XXI : sve_int_arith_vl<0b1, "addpl">;
}

3
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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@ -3551,6 +3551,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
case Match_InvalidFPImm:
return Error(Loc,
"expected compatible register or floating-point constant");
case Match_InvalidMemoryIndexedSImm6:
return Error(Loc, "index must be an integer in range [-32, 31].");
case Match_InvalidMemoryIndexedSImm9:
return Error(Loc, "index must be an integer in range [-256, 255].");
case Match_InvalidMemoryIndexedSImm10:
@ -4063,6 +4065,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidMemoryXExtend32:
case Match_InvalidMemoryXExtend64:
case Match_InvalidMemoryXExtend128:
case Match_InvalidMemoryIndexedSImm6:
case Match_InvalidMemoryIndexed4SImm7:
case Match_InvalidMemoryIndexed8SImm7:
case Match_InvalidMemoryIndexed16SImm7:

39
llvm/lib/Target/AArch64/SVEInstrFormats.td
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@ -75,6 +75,43 @@ multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm> {
def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>;
}
//===----------------------------------------------------------------------===//
// SVE Stack Allocation Group
//===----------------------------------------------------------------------===//
class sve_int_arith_vl<bit opc, string asm>
: I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6),
asm, "\t$Rd, $Rn, $imm6",
"",
[]>, Sched<[]> {
bits<5> Rd;
bits<5> Rn;
bits<6> imm6;
let Inst{31-23} = 0b000001000;
let Inst{22} = opc;
let Inst{21} = 0b1;
let Inst{20-16} = Rn;
let Inst{15-11} = 0b01010;
let Inst{10-5} = imm6;
let Inst{4-0} = Rd;
}
class sve_int_read_vl_a<bit op, bits<5> opc2, string asm>
: I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
asm, "\t$Rd, $imm6",
"",
[]>, Sched<[]> {
bits<5> Rd;
bits<6> imm6;
let Inst{31-23} = 0b000001001;
let Inst{22} = op;
let Inst{21} = 0b1;
let Inst{20-16} = opc2{4-0};
let Inst{15-11} = 0b01010;
let Inst{10-5} = imm6;
let Inst{4-0} = Rd;
}
//===----------------------------------------------------------------------===//
// SVE Permute - In Lane Group
//===----------------------------------------------------------------------===//
@ -166,4 +203,4 @@ multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> {
def _H : sve_int_perm_bin_perm_pp<opc, 0b01, asm, PPR16>;
def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>;
def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>;
}
}

13
llvm/test/MC/AArch64/SVE/addpl-diagnostics.s Normal file
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@ -0,0 +1,13 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Immediate out of upper bound [-32, 31].
addpl x19, x14, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
// CHECK-NEXT: addpl x19, x14, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// addpl requires an immediate, not a register.
addpl x19, x14, x15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
// CHECK-NEXT: addpl x19, x14, x15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

32
llvm/test/MC/AArch64/SVE/addpl.s Normal file
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@ -0,0 +1,32 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
addpl x21, x21, #0
// CHECK-INST: addpl x21, x21, #0
// CHECK-ENCODING: [0x15,0x50,0x75,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 15 50 75 04 <unknown>
addpl x23, x8, #-1
// CHECK-INST: addpl x23, x8, #-1
// CHECK-ENCODING: [0xf7,0x57,0x68,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: f7 57 68 04 <unknown>
addpl sp, sp, #31
// CHECK-INST: addpl sp, sp, #31
// CHECK-ENCODING: [0xff,0x53,0x7f,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 53 7f 04 <unknown>
addpl x0, x0, #-32
// CHECK-INST: addpl x0, x0, #-32
// CHECK-ENCODING: [0x00,0x54,0x60,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 54 60 04 <unknown>

13
llvm/test/MC/AArch64/SVE/addvl-diagnostics.s Normal file
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@ -0,0 +1,13 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Immediate out of upper bound [-32, 31].
addvl x3, x5, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
// CHECK-NEXT: addvl x3, x5, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// addvl requires an immediate, not a register.
addvl x3, x5, x6
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
// CHECK-NEXT: addvl x3, x5, x6
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

32
llvm/test/MC/AArch64/SVE/addvl.s Normal file
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@ -0,0 +1,32 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
addvl x21, x21, #0
// CHECK-INST: addvl x21, x21, #0
// CHECK-ENCODING: [0x15,0x50,0x35,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 15 50 35 04 <unknown>
addvl x23, x8, #-1
// CHECK-INST: addvl x23, x8, #-1
// CHECK-ENCODING: [0xf7,0x57,0x28,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: f7 57 28 04 <unknown>
addvl sp, sp, #31
// CHECK-INST: addvl sp, sp, #31
// CHECK-ENCODING: [0xff,0x53,0x3f,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 53 3f 04 <unknown>
addvl x0, x0, #-32
// CHECK-INST: addvl x0, x0, #-32
// CHECK-ENCODING: [0x00,0x54,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 54 20 04 <unknown>

13
llvm/test/MC/AArch64/SVE/rdvl-diagnostics.s Normal file
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@ -0,0 +1,13 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Immediate out of upper bound [-32, 31].
rdvl x9, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
// CHECK-NEXT: rdvl x9, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// rdvl requires an immediate, not a register.
rdvl x9, x10
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
// CHECK-NEXT: rdvl x9, x10
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

32
llvm/test/MC/AArch64/SVE/rdvl.s Normal file
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@ -0,0 +1,32 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
rdvl x0, #0
// CHECK-INST: rdvl x0, #0
// CHECK-ENCODING: [0x00,0x50,0xbf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 50 bf 04 <unknown>
rdvl xzr, #-1
// CHECK-INST: rdvl xzr, #-1
// CHECK-ENCODING: [0xff,0x57,0xbf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 57 bf 04 <unknown>
rdvl x23, #31
// CHECK-INST: rdvl x23, #31
// CHECK-ENCODING: [0xf7,0x53,0xbf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: f7 53 bf 04 <unknown>
rdvl x21, #-32
// CHECK-INST: rdvl x21, #-32
// CHECK-ENCODING: [0x15,0x54,0xbf,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 15 54 bf 04 <unknown>