forked from OSchip/llvm-project
Fix a major regression last night that prevented us from producing [mem] op= reg
operations. The body of the if is less indented but unmodified in this patch. llvm-svn: 19638
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@ -2489,17 +2489,21 @@ void ISel::Select(SDOperand N) {
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// Check to see if this is a load/op/store combination.
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if (N.getOperand(1).Val->hasOneUse() &&
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N.getOperand(0).getOpcode() == ISD::LOAD &&
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N.getOperand(1).Val->getNumOperands() == 2 &&
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!MVT::isFloatingPoint(N.getOperand(0).getValue(0).getValueType()) &&
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isFoldableLoad(N.getOperand(0).getValue(0),
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N.getOperand(0).getValue(1))) {
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!MVT::isFloatingPoint(N.getOperand(0).getValue(0).getValueType())) {
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SDOperand TheLoad = N.getOperand(0).getValue(0);
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// Check to see if we are loading the same pointer that we're storing to.
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if (TheLoad.getOperand(1) == N.getOperand(2)) {
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// See if the stored value is a simple binary operator that uses the
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// load as one of its operands.
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// See if the stored value is a simple binary operator that uses the load
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// as one of its operands.
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SDOperand Op = N.getOperand(1);
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if ((Op.getOperand(0) == TheLoad || Op.getOperand(1) == TheLoad)) {
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// Check to see if we are loading the same pointer that we're storing to.
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if (TheLoad.getOperand(1) == N.getOperand(2) &&
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((Op.getOperand(0) == TheLoad &&
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isFoldableLoad(TheLoad, Op.getOperand(1))) ||
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(Op.getOperand(1) == TheLoad &&
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isFoldableLoad(TheLoad, Op.getOperand(0))))) {
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// Finally, check to see if this is one of the ops we can handle!
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static const unsigned ADDTAB[] = {
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X86::ADD8mi, X86::ADD16mi, X86::ADD32mi,
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@ -2608,8 +2612,6 @@ void ISel::Select(SDOperand N) {
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}
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}
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}
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}
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switch (N.getOperand(1).getValueType()) {
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default: assert(0 && "Cannot store this type!");
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