forked from OSchip/llvm-project
[LoopInterchange] Fix phi node ordering miscompile.
The way that splitInnerLoopHeader splits blocks requires that the induction PHI will be the first PHI in the inner loop header. This makes sure that is actually the case when there are both IV and reduction phis. Differential Revision: https://reviews.llvm.org/D38682 llvm-svn: 316261
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@ -1185,6 +1185,11 @@ bool LoopInterchangeTransform::transform() {
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else
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InnerIndexVar = dyn_cast<Instruction>(InductionPHI->getIncomingValue(0));
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// Ensure that InductionPHI is the first Phi node as required by
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// splitInnerLoopHeader
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if (&InductionPHI->getParent()->front() != InductionPHI)
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InductionPHI->moveBefore(&InductionPHI->getParent()->front());
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// Split at the place were the induction variable is
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// incremented/decremented.
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// TODO: This splitting logic may not work always. Fix this.
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@ -1218,7 +1223,7 @@ void LoopInterchangeTransform::splitInnerLoopHeader() {
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BasicBlock *InnerLoopHeader = InnerLoop->getHeader();
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BasicBlock *InnerLoopPreHeader = InnerLoop->getLoopPreheader();
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if (InnerLoopHasReduction) {
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// FIXME: Check if the induction PHI will always be the first PHI.
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// Note: The induction PHI must be the first PHI for this to work
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BasicBlock *New = InnerLoopHeader->splitBasicBlock(
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++(InnerLoopHeader->begin()), InnerLoopHeader->getName() + ".split");
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if (LI)
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@ -0,0 +1,90 @@
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; RUN: opt < %s -loop-interchange -S | FileCheck %s
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;; Checks the order of the inner phi nodes does not cause havoc.
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;; The inner loop has a reduction into c. The IV is not the first phi.
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "armv8--linux-gnueabihf"
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; Function Attrs: norecurse nounwind
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define void @test(i32 %T, [90 x i32]* noalias nocapture %C, i16* noalias nocapture readonly %A, i16* noalias nocapture readonly %B) local_unnamed_addr #0 {
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entry:
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%cmp45 = icmp sgt i32 %T, 0
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br i1 %cmp45, label %for.body3.lr.ph.preheader, label %for.end21
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for.body3.lr.ph.preheader: ; preds = %entry
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br label %for.body3.lr.ph
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for.body3.lr.ph: ; preds = %for.body3.lr.ph.preheader, %for.inc19
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%i.046 = phi i32 [ %inc20, %for.inc19 ], [ 0, %for.body3.lr.ph.preheader ]
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%mul = mul nsw i32 %i.046, %T
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br label %for.body6.lr.ph
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for.body6.lr.ph: ; preds = %for.inc16, %for.body3.lr.ph
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%j.043 = phi i32 [ 0, %for.body3.lr.ph ], [ %inc17, %for.inc16 ]
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%arrayidx14 = getelementptr inbounds [90 x i32], [90 x i32]* %C, i32 %i.046, i32 %j.043
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%arrayidx14.promoted = load i32, i32* %arrayidx14, align 4
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br label %for.body6
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for.body6: ; preds = %for.body6, %for.body6.lr.ph
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%add1541 = phi i32 [ %arrayidx14.promoted, %for.body6.lr.ph ], [ %add15, %for.body6 ]
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%k.040 = phi i32 [ 0, %for.body6.lr.ph ], [ %inc, %for.body6 ]
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%add = add nsw i32 %k.040, %mul
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%arrayidx = getelementptr inbounds i16, i16* %A, i32 %add
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%0 = load i16, i16* %arrayidx, align 2
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%conv = sext i16 %0 to i32
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%mul7 = mul nsw i32 %k.040, %T
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%add8 = add nsw i32 %mul7, %j.043
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%arrayidx9 = getelementptr inbounds i16, i16* %B, i32 %add8
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%1 = load i16, i16* %arrayidx9, align 2
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%conv10 = sext i16 %1 to i32
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%mul11 = mul nsw i32 %conv10, %conv
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%add15 = add nsw i32 %mul11, %add1541
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%inc = add nuw nsw i32 %k.040, 1
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%exitcond = icmp eq i32 %inc, %T
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br i1 %exitcond, label %for.inc16, label %for.body6
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for.inc16: ; preds = %for.body6
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%add15.lcssa = phi i32 [ %add15, %for.body6 ]
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store i32 %add15.lcssa, i32* %arrayidx14, align 4
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%inc17 = add nuw nsw i32 %j.043, 1
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%exitcond47 = icmp eq i32 %inc17, %T
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br i1 %exitcond47, label %for.inc19, label %for.body6.lr.ph
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for.inc19: ; preds = %for.inc16
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%inc20 = add nuw nsw i32 %i.046, 1
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%exitcond48 = icmp eq i32 %inc20, %T
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br i1 %exitcond48, label %for.end21.loopexit, label %for.body3.lr.ph
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for.end21.loopexit: ; preds = %for.inc19
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br label %for.end21
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for.end21: ; preds = %for.end21.loopexit, %entry
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ret void
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}
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; CHECK-LABEL: test
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; CHECK: entry:
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; CHECK: br i1 %cmp45, label %for.body6.preheader, label %for.end21
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; CHECK: for.body3.lr.ph.preheader:
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; CHECK: br label %for.body3.lr.ph
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; CHECK: for.body3.lr.ph:
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; CHECK: br label %for.body6.lr.ph.preheader
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; CHECK: for.body6.lr.ph.preheader:
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; CHECK: br label %for.body6.lr.ph
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; CHECK: for.body6.lr.ph:
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; CHECK: br label %for.body6.split1
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; CHECK: for.body6.preheader:
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; CHECK: br label %for.body6
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; CHECK: for.body6:
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; CHECK: br label %for.body3.lr.ph.preheader
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; CHECK: for.body6.split1:
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; CHECK: br label %for.inc16
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; CHECK: for.body6.split:
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; CHECK: add nuw nsw i32 %k.040, 1
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; CHECK: br i1 %exitcond, label %for.end21.loopexit, label %for.body6
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; CHECK: for.inc16:
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; CHECK: br i1 %exitcond47, label %for.inc19, label %for.body6.lr.ph
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; CHECK: for.inc19:
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; CHECK: br i1 %exitcond48, label %for.body6.split, label %for.body3.lr.ph
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; CHECK: for.end21:
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