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[Hexagon] Adding double word add/min/minu/max/maxu instructions and tests. 

llvm-svn: 224153
This commit is contained in:
Colin LeMahieu 2014-12-12 21:29:25 +00:00
parent cdab5b6935
commit 90482a77b1
2 changed files with 76 additions and 20 deletions
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82
llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td
View File

@ -92,27 +92,69 @@ let isCall = 1, hasSideEffects = 0,
// ALU64/ALU +
//===----------------------------------------------------------------------===//
let AddedComplexity = 200 in
def MAXw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
DoubleRegs:$src2),
"$dst = max($src2, $src1)",
[(set (i64 DoubleRegs:$dst),
(i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
(i64 DoubleRegs:$src1))),
(i64 DoubleRegs:$src1),
(i64 DoubleRegs:$src2))))]>,
Requires<[HasV3T]>;
let AddedComplexity = 200 in
def MINw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
DoubleRegs:$src2),
"$dst = min($src2, $src1)",
[(set (i64 DoubleRegs:$dst),
(i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
(i64 DoubleRegs:$src1))),
(i64 DoubleRegs:$src1),
(i64 DoubleRegs:$src2))))]>,
Requires<[HasV3T]>;
let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23,
validSubTargets = HasV3SubT, isCodeGenOnly = 0 in
def A2_addpsat : T_ALU64_arith<"add", 0b011, 0b101, 1, 0, 1>;
class T_ALU64_addsp_hl<string suffix, bits<3> MinOp>
: T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">;
let isCodeGenOnly = 0 in {
def A2_addspl : T_ALU64_addsp_hl<":raw:lo", 0b110>;
def A2_addsph : T_ALU64_addsp_hl<":raw:hi", 0b111>;
}
let hasSideEffects = 0, isCodeGenOnly = 0 in
def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd),
(ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
[(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))),
(i64 DoubleRegs:$Rt))))],
"", ALU64_tc_1_SLOT23>;
let hasSideEffects = 0 in
class T_XTYPE_MIN_MAX_P<bit isMax, bit isUnsigned>
: ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
"$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
#"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
bits<5> Rd;
bits<5> Rs;
bits<5> Rt;
let IClass = 0b1101;
let Inst{27-23} = 0b00111;
let Inst{22-21} = !if(isMax, 0b10, 0b01);
let Inst{20-16} = !if(isMax, Rt, Rs);
let Inst{12-8} = !if(isMax, Rs, Rt);
let Inst{7} = 0b1;
let Inst{6} = !if(isMax, 0b0, 0b1);
let Inst{5} = isUnsigned;
let Inst{4-0} = Rd;
}
let isCodeGenOnly = 0 in {
def A2_minp : T_XTYPE_MIN_MAX_P<0, 0>;
def A2_minup : T_XTYPE_MIN_MAX_P<0, 1>;
def A2_maxp : T_XTYPE_MIN_MAX_P<1, 0>;
def A2_maxup : T_XTYPE_MIN_MAX_P<1, 1>;
}
multiclass MinMax_pats_p<PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
defm: T_MinMax_pats<Op, DoubleRegs, i64, Inst, SwapInst>;
}
let AddedComplexity = 200 in {
defm: MinMax_pats_p<setge, A2_maxp, A2_minp>;
defm: MinMax_pats_p<setgt, A2_maxp, A2_minp>;
defm: MinMax_pats_p<setle, A2_minp, A2_maxp>;
defm: MinMax_pats_p<setlt, A2_minp, A2_maxp>;
defm: MinMax_pats_p<setuge, A2_maxup, A2_minup>;
defm: MinMax_pats_p<setugt, A2_maxup, A2_minup>;
defm: MinMax_pats_p<setule, A2_minup, A2_maxup>;
defm: MinMax_pats_p<setult, A2_minup, A2_maxup>;
}
//===----------------------------------------------------------------------===//
// ALU64/ALU -

14
llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt
View File

@ -28,16 +28,30 @@
# CHECK: r17 = add(r21.h, r31.h):sat:<<16
0xf0 0xde 0x14 0xd3
# CHECK: r17:16 = add(r21:20, r31:30)
0xb0 0xde 0x74 0xd3
# CHECK: r17:16 = add(r21:20, r31:30):sat
0xd0 0xde 0x74 0xd3
# CHECK: r17:16 = add(r21:20, r31:30):raw:lo
0xf0 0xde 0x74 0xd3
# CHECK: r17:16 = add(r21:20, r31:30):raw:hi
0x10 0xde 0xf4 0xd3
# CHECK: r17:16 = and(r21:20, r31:30)
0x11 0xdf 0xd5 0xd5
# CHECK: r17 = max(r21, r31)
0x91 0xdf 0xd5 0xd5
# CHECK: r17 = maxu(r21, r31)
0x90 0xde 0xd4 0xd3
# CHECK: r17:16 = max(r21:20, r31:30)
0xb0 0xde 0xd4 0xd3
# CHECK: r17:16 = maxu(r21:20, r31:30)
0x11 0xd5 0xbf 0xd5
# CHECK: r17 = min(r21, r31)
0x91 0xd5 0xbf 0xd5
# CHECK: r17 = minu(r21, r31)
0xd0 0xd4 0xbe 0xd3
# CHECK: r17:16 = min(r21:20, r31:30)
0xf0 0xd4 0xbe 0xd3
# CHECK: r17:16 = minu(r21:20, r31:30)
0x50 0xde 0xf4 0xd3
# CHECK: r17:16 = or(r21:20, r31:30)
0x11 0xd5 0x3f 0xd5