diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index 4890e3094fe6..16a1a29660e2 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -206,9 +206,11 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
 
   MFI->setStackSize(NumBytes);
 
-  //sub sp, sp, #NumBytes
-  splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::SUB), ARM::R13,
-			     ARM::R13, NumBytes);
+  if (NumBytes) {
+    //sub sp, sp, #NumBytes
+    splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::SUB), ARM::R13,
+                                  ARM::R13, NumBytes);
+  }
 
 
   if (HasFP) {
@@ -234,9 +236,11 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
     BuildMI(MBB, MBBI, TII.get(ARM::LDR), ARM::R11).addReg(ARM::R13).addImm(0);
   }
 
-  //add sp, sp, #NumBytes
-  splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::ADD), ARM::R13,
-			     ARM::R13, NumBytes);
+  if (NumBytes){
+    //add sp, sp, #NumBytes
+    splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::ADD), ARM::R13,
+                                  ARM::R13, NumBytes);
+  }
 
 }
 
diff --git a/llvm/test/Regression/CodeGen/ARM/spaddsub.ll b/llvm/test/Regression/CodeGen/ARM/spaddsub.ll
new file mode 100644
index 000000000000..ef3b9b7c1d13
--- /dev/null
+++ b/llvm/test/Regression/CodeGen/ARM/spaddsub.ll
@@ -0,0 +1,10 @@
+; RUN: llvm-upgrade < %s | llvm-as | llc -f -march=arm -o %t.s &&
+; RUN: not grep "add r13, r13, #0" < %t.s &&
+; RUN: not grep "sub r13, r13, #0" < %t.s
+
+int %f() {
+entry:
+	ret int 1
+}
+
+