forked from OSchip/llvm-project
[mips][msa] Direct Object Emission for I8 instructions.
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
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@ -147,7 +147,14 @@ class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
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}
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class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
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bits<8> u8;
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bits<5> ws;
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bits<5> wd;
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let Inst{25-24} = major;
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let Inst{23-16} = u8;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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@ -1095,34 +1095,34 @@ class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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}
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class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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SplatComplexPattern SplatImm, RegisterClass RCWD,
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RegisterClass RCWS = RCWD,
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SplatComplexPattern SplatImm, RegisterOperand ROWD,
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RegisterOperand ROWS = ROWD,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs RCWD:$wd);
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dag InOperandList = (ins RCWS:$ws, SplatImm.OpClass:$u8);
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dag OutOperandList = (outs ROWD:$wd);
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dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
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list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, SplatImm:$u8))];
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list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
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InstrItinClass Itinerary = itin;
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}
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// This class is deprecated and will be removed in the next few patches
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class MSA_I8_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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RegisterClass RCWD, RegisterClass RCWS = RCWD,
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RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs RCWD:$wd);
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dag InOperandList = (ins RCWS:$ws, uimm8:$u8);
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dag OutOperandList = (outs ROWD:$wd);
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dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
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list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt8:$u8))];
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list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt8:$u8))];
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InstrItinClass Itinerary = itin;
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}
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class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterClass RCWD,
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RegisterClass RCWS = RCWD,
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class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
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RegisterOperand ROWS = ROWD,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs RCWD:$wd);
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dag InOperandList = (ins RCWS:$ws, uimm8:$u8);
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dag OutOperandList = (outs ROWD:$wd);
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dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
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list<dag> Pattern = [(set RCWD:$wd, (MipsSHF immZExt8:$u8, RCWS:$ws))];
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list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))];
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InstrItinClass Itinerary = itin;
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}
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@ -1348,7 +1348,8 @@ class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128H>;
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class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128W>;
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class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128D>;
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class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8, MSA128B>;
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class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
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MSA128BOpnd>;
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class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
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MSA128BOpnd>;
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@ -1444,11 +1445,12 @@ class BINSRI_D_DESC : MSA_BIT_D_DESC_BASE<"binsri.d", int_mips_binsri_d,
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class BMNZ_V_DESC : MSA_VEC_DESC_BASE<"bmnz.v", int_mips_bmnz_v, MSA128B>;
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class BMNZI_B_DESC : MSA_I8_X_DESC_BASE<"bmnzi.b", int_mips_bmnzi_b, MSA128B>;
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class BMNZI_B_DESC : MSA_I8_X_DESC_BASE<"bmnzi.b", int_mips_bmnzi_b,
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MSA128BOpnd>;
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class BMZ_V_DESC : MSA_VEC_DESC_BASE<"bmz.v", int_mips_bmz_v, MSA128B>;
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class BMZI_B_DESC : MSA_I8_X_DESC_BASE<"bmzi.b", int_mips_bmzi_b, MSA128B>;
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class BMZI_B_DESC : MSA_I8_X_DESC_BASE<"bmzi.b", int_mips_bmzi_b, MSA128BOpnd>;
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class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", int_mips_bneg_b, MSA128BOpnd>;
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class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", int_mips_bneg_h, MSA128HOpnd>;
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@ -1478,11 +1480,12 @@ class BSEL_V_DESC {
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}
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class BSELI_B_DESC {
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dag OutOperandList = (outs MSA128B:$wd);
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dag InOperandList = (ins MSA128B:$wd_in, MSA128B:$ws, vsplat_uimm8:$u8);
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dag OutOperandList = (outs MSA128BOpnd:$wd);
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dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
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vsplat_uimm8:$u8);
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string AsmString = "bseli.b\t$wd, $ws, $u8";
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list<dag> Pattern = [(set MSA128B:$wd, (vselect MSA128B:$wd_in,
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MSA128B:$ws,
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list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
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MSA128BOpnd:$ws,
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vsplati8_uimm8:$u8))];
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InstrItinClass Itinerary = NoItinerary;
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string Constraints = "$wd = $wd_in";
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@ -2167,14 +2170,14 @@ class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128W>;
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class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128D>;
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class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
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MSA128B>;
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MSA128BOpnd>;
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class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128B>;
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class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128H>;
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class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128W>;
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class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128D>;
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class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128B>;
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class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
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class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
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class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
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@ -2201,9 +2204,9 @@ class SAT_U_H_DESC : MSA_BIT_H_DESC_BASE<"sat_u.h", int_mips_sat_u_h, MSA128H>;
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class SAT_U_W_DESC : MSA_BIT_W_DESC_BASE<"sat_u.w", int_mips_sat_u_w, MSA128W>;
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class SAT_U_D_DESC : MSA_BIT_D_DESC_BASE<"sat_u.d", int_mips_sat_u_d, MSA128D>;
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class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128B>;
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class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128H>;
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class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128W>;
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class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
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class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
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class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
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class SLD_B_DESC : MSA_3R_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
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class SLD_H_DESC : MSA_3R_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
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@ -2387,7 +2390,8 @@ class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128H>;
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class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128W>;
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class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128D>;
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class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8, MSA128B>;
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class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
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MSA128BOpnd>;
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// Instruction defs.
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def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
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@ -0,0 +1,36 @@
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# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 -mattr=+msa -arch=mips | FileCheck %s
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#
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# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -arch=mips -filetype=obj -o - | llvm-objdump -d -triple=mipsel-unknown-linux -mattr=+msa -arch=mips - | FileCheck %s -check-prefix=CHECKOBJDUMP
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#
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# CHECK: andi.b $w2, $w29, 48 # encoding: [0x78,0x30,0xe8,0x80]
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# CHECK: bmnzi.b $w6, $w22, 126 # encoding: [0x78,0x7e,0xb1,0x81]
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# CHECK: bmzi.b $w27, $w1, 88 # encoding: [0x79,0x58,0x0e,0xc1]
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# CHECK: bseli.b $w29, $w3, 189 # encoding: [0x7a,0xbd,0x1f,0x41]
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# CHECK: nori.b $w1, $w17, 56 # encoding: [0x7a,0x38,0x88,0x40]
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# CHECK: ori.b $w26, $w20, 135 # encoding: [0x79,0x87,0xa6,0x80]
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# CHECK: shf.b $w19, $w30, 105 # encoding: [0x78,0x69,0xf4,0xc2]
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# CHECK: shf.h $w17, $w8, 76 # encoding: [0x79,0x4c,0x44,0x42]
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# CHECK: shf.w $w14, $w3, 93 # encoding: [0x7a,0x5d,0x1b,0x82]
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# CHECK: xori.b $w16, $w10, 20 # encoding: [0x7b,0x14,0x54,0x00]
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# CHECKOBJDUMP: andi.b $w2, $w29, 48
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# CHECKOBJDUMP: bmnzi.b $w6, $w22, 126
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# CHECKOBJDUMP: bmzi.b $w27, $w1, 88
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# CHECKOBJDUMP: bseli.b $w29, $w3, 189
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# CHECKOBJDUMP: nori.b $w1, $w17, 56
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# CHECKOBJDUMP: ori.b $w26, $w20, 135
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# CHECKOBJDUMP: shf.b $w19, $w30, 105
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# CHECKOBJDUMP: shf.h $w17, $w8, 76
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# CHECKOBJDUMP: shf.w $w14, $w3, 93
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# CHECKOBJDUMP: xori.b $w16, $w10, 20
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andi.b $w2, $w29, 48
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bmnzi.b $w6, $w22, 126
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bmzi.b $w27, $w1, 88
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bseli.b $w29, $w3, 189
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nori.b $w1, $w17, 56
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ori.b $w26, $w20, 135
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shf.b $w19, $w30, 105
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shf.h $w17, $w8, 76
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shf.w $w14, $w3, 93
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xori.b $w16, $w10, 20
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