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[PowerPC][NFC] Added test for sext/shl combination after isel. 

llvm-svn: 363118
This commit is contained in:
Kai Luo 2019-06-12 02:45:27 +00:00
parent 14d4869209
commit 8faff5606e
1 changed files with 76 additions and 0 deletions
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llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown \
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-BE
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-P9
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-P9-BE
define dso_local i32 @poc(i32* %base, i32 %index, i1 %flag, i32 %default) {
; CHECK-LABEL: poc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi. r5, r5, 1
; CHECK-NEXT: bc 4, gt, .LBB0_2
; CHECK-NEXT: # %bb.1: # %true
; CHECK-NEXT: extsw r4, r4
; CHECK-NEXT: sldi r4, r4, 2
; CHECK-NEXT: lwzx r3, r3, r4
; CHECK-NEXT: blr
; CHECK-NEXT: .LBB0_2: # %false
; CHECK-NEXT: mr r3, r6
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: poc:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: andi. r5, r5, 1
; CHECK-BE-NEXT: bc 4, gt, .LBB0_2
; CHECK-BE-NEXT: # %bb.1: # %true
; CHECK-BE-NEXT: extsw r4, r4
; CHECK-BE-NEXT: sldi r4, r4, 2
; CHECK-BE-NEXT: lwzx r3, r3, r4
; CHECK-BE-NEXT: blr
; CHECK-BE-NEXT: .LBB0_2: # %false
; CHECK-BE-NEXT: mr r3, r6
; CHECK-BE-NEXT: blr
;
; CHECK-P9-LABEL: poc:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: andi. r5, r5, 1
; CHECK-P9-NEXT: bc 4, gt, .LBB0_2
; CHECK-P9-NEXT: # %bb.1: # %true
; CHECK-P9-NEXT: extsw r4, r4
; CHECK-P9-NEXT: sldi r4, r4, 2
; CHECK-P9-NEXT: lwzx r3, r3, r4
; CHECK-P9-NEXT: blr
; CHECK-P9-NEXT: .LBB0_2: # %false
; CHECK-P9-NEXT: mr r3, r6
; CHECK-P9-NEXT: blr
;
; CHECK-P9-BE-LABEL: poc:
; CHECK-P9-BE: # %bb.0: # %entry
; CHECK-P9-BE-NEXT: andi. r5, r5, 1
; CHECK-P9-BE-NEXT: bc 4, gt, .LBB0_2
; CHECK-P9-BE-NEXT: # %bb.1: # %true
; CHECK-P9-BE-NEXT: extsw r4, r4
; CHECK-P9-BE-NEXT: sldi r4, r4, 2
; CHECK-P9-BE-NEXT: lwzx r3, r3, r4
; CHECK-P9-BE-NEXT: blr
; CHECK-P9-BE-NEXT: .LBB0_2: # %false
; CHECK-P9-BE-NEXT: mr r3, r6
; CHECK-P9-BE-NEXT: blr
entry:
%iconv = sext i32 %index to i64
br i1 %flag, label %true, label %false
true:
%ptr = getelementptr inbounds i32, i32* %base, i64 %iconv
%value = load i32, i32* %ptr, align 4
ret i32 %value
false:
ret i32 %default
}