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enable PPC register scavenging by default (update tests and remove some FIXMEs) 

llvm-svn: 145819
This commit is contained in:
Hal Finkel 2011-12-05 17:55:17 +00:00
parent 72a26e8b8d
commit 8f6834dfa5
9 changed files with 33 additions and 37 deletions
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2
llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
View File

@ -772,7 +772,7 @@ PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// FIXME: doesn't detect whether or not we need to spill vXX, which requires
// r0 for now.
if (RegInfo->requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable.
if (RegInfo->requiresRegisterScavenging(MF))
if (needsFP(MF) || spillsCR(MF)) {
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;

10
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -33,8 +33,8 @@
#include "PPCGenInstrInfo.inc"
namespace llvm {
extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
extern cl::opt<bool> DisablePPC32RS;
extern cl::opt<bool> DisablePPC64RS;
}
using namespace llvm;
@ -345,6 +345,7 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
}
// This function returns true if a CR spill is necessary and false otherwise.
bool
PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
unsigned SrcReg, bool isKill,
@ -395,9 +396,8 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
getKillRegState(isKill)),
FrameIdx));
} else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) {
if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
(EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
// FIXME (64-bit): Enable
if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
(!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
.addReg(SrcReg,
getKillRegState(isKill)),

18
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -46,15 +46,14 @@
#define GET_REGINFO_TARGET_DESC
#include "PPCGenRegisterInfo.inc"
// FIXME (64-bit): Eventually enable by default.
namespace llvm {
cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
cl::opt<bool> DisablePPC32RS("disable-ppc32-regscavenger",
cl::init(false),
cl::desc("Enable PPC32 register scavenger"),
cl::desc("Disable PPC32 register scavenger"),
cl::Hidden);
cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
cl::opt<bool> DisablePPC64RS("disable-ppc64-regscavenger",
cl::init(false),
cl::desc("Enable PPC64 register scavenger"),
cl::desc("Disable PPC64 register scavenger"),
cl::Hidden);
}
@ -63,8 +62,8 @@ using namespace llvm;
// FIXME (64-bit): Should be inlined.
bool
PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
return ((EnablePPC32RS && !Subtarget.isPPC64()) ||
(EnablePPC64RS && Subtarget.isPPC64()));
return ((!DisablePPC32RS && !Subtarget.isPPC64()) ||
(!DisablePPC64RS && Subtarget.isPPC64()));
}
PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
@ -231,9 +230,6 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
Reserved.set(PPC::R13);
Reserved.set(PPC::R31);
if (!requiresRegisterScavenging(MF))
Reserved.set(PPC::R0); // FIXME (64-bit): Remove
Reserved.set(PPC::X0);
Reserved.set(PPC::X1);
Reserved.set(PPC::X13);
@ -544,7 +540,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
}
// Special case for pseudo-op SPILL_CR.
if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable by default.
if (requiresRegisterScavenging(MF))
if (OpC == PPC::SPILL_CR) {
lowerCRSpilling(II, FrameIndex, SPAdj, RS);
return;

2
llvm/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=powerpc-apple-darwin -enable-ppc32-regscavenger
; RUN: llc < %s -mtriple=powerpc-apple-darwin
declare i8* @bar(i32)

2
llvm/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=ppc32 -enable-ppc32-regscavenger
; RUN: llc < %s -march=ppc32
%struct._cpp_strbuf = type { i8*, i32, i32 }
%struct.cpp_string = type { i32, i8* }

2
llvm/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=ppc64 -enable-ppc64-regscavenger
; RUN: llc < %s -march=ppc64
define i16 @test(i8* %d1, i16* %d2) {
%tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 )

16
llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
View File

@ -6,11 +6,11 @@ target triple = "powerpc-apple-darwin9.6"
define void @foo() nounwind {
entry:
;CHECK: mfcr r2
;CHECK: lis r0, 1
;CHECK: rlwinm r2, r2, 8, 0, 31
;CHECK: ori r0, r0, 34524
;CHECK: stwx r2, r1, r0
;CHECK: lis r4, 1
;CHECK: ori r4, r4, 34524
;CHECK: mfcr r3
;CHECK: rlwinm r3, r3, 8, 0, 31
;CHECK: stwx r3, r1, r4
%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1]
@ -19,9 +19,9 @@ entry:
br label %return
return: ; preds = %entry
;CHECK: lis r0, 1
;CHECK: ori r0, r0, 34524
;CHECK: lwzx r2, r1, r0
;CHECK: lis r3, 1
;CHECK: ori r3, r3, 34524
;CHECK: lwzx r2, r1, r3
;CHECK: rlwinm r2, r2, 24, 0, 31
;CHECK: mtcrf 32, r2
ret void

6
llvm/test/CodeGen/PowerPC/Frames-alloca.ll
View File

@ -2,9 +2,9 @@
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC64
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-NOFP
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-NOFP
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS-NOFP
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32-RS
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-RS-NOFP
; CHECK-PPC32: stw r31, -4(r1)
; CHECK-PPC32: lwz r1, 0(r1)

12
llvm/test/CodeGen/PowerPC/ppc32-vaarg.ll
View File

@ -37,8 +37,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
; CHECK-NEXT: stw 3, -24(1)
; CHECK-NEXT: stw 8, -28(1)
; CHECK-NEXT: stw 6, -32(1)
; CHECK-NEXT: mfcr 0 # cr0
; CHECK-NEXT: stw 0, -36(1)
; CHECK-NEXT: mfcr 3 # cr0
; CHECK-NEXT: stw 3, -36(1)
; CHECK-NEXT: blt 0, .LBB0_4
; CHECK-NEXT: # BB#3: # %entry
; CHECK-NEXT: lwz 3, -20(1)
@ -82,8 +82,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
; CHECK-NEXT: stw 4, -52(1)
; CHECK-NEXT: stw 6, -56(1)
; CHECK-NEXT: stw 8, -60(1)
; CHECK-NEXT: mfcr 0 # cr0
; CHECK-NEXT: stw 0, -64(1)
; CHECK-NEXT: mfcr 3 # cr0
; CHECK-NEXT: stw 3, -64(1)
; CHECK-NEXT: blt 0, .LBB0_8
; CHECK-NEXT: # BB#7: # %entry
; CHECK-NEXT: lwz 3, -48(1)
@ -122,8 +122,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
; CHECK-NEXT: mr 8, 5
; CHECK-NEXT: stw 4, -72(1)
; CHECK-NEXT: stw 6, -76(1)
; CHECK-NEXT: mfcr 0 # cr0
; CHECK-NEXT: stw 0, -80(1)
; CHECK-NEXT: mfcr 3 # cr0
; CHECK-NEXT: stw 3, -80(1)
; CHECK-NEXT: stw 5, -84(1)
; CHECK-NEXT: stw 8, -88(1)
; CHECK-NEXT: stw 7, -92(1)