From 8f6834dfa57b2c92004e095a68917e2be0026382 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Mon, 5 Dec 2011 17:55:17 +0000 Subject: [PATCH] enable PPC register scavenging by default (update tests and remove some FIXMEs) llvm-svn: 145819 --- llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 2 +- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 10 +++++----- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 18 +++++++----------- .../PowerPC/2008-03-05-RegScavengerAssert.ll | 2 +- .../PowerPC/2008-03-17-RegScavengerCrash.ll | 2 +- .../PowerPC/2008-03-18-RegScavengerAssert.ll | 2 +- llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll | 16 ++++++++-------- llvm/test/CodeGen/PowerPC/Frames-alloca.ll | 6 +++--- llvm/test/CodeGen/PowerPC/ppc32-vaarg.ll | 12 ++++++------ 9 files changed, 33 insertions(+), 37 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp index ec4231e6ff4d..e9a4290bae1e 100644 --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -772,7 +772,7 @@ PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, // FIXME: doesn't detect whether or not we need to spill vXX, which requires // r0 for now. - if (RegInfo->requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable. + if (RegInfo->requiresRegisterScavenging(MF)) if (needsFP(MF) || spillsCR(MF)) { const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index cdb15a175529..f28d07c8a610 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -33,8 +33,8 @@ #include "PPCGenInstrInfo.inc" namespace llvm { -extern cl::opt EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. -extern cl::opt EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. +extern cl::opt DisablePPC32RS; +extern cl::opt DisablePPC64RS; } using namespace llvm; @@ -345,6 +345,7 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); } +// This function returns true if a CR spill is necessary and false otherwise. bool PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, @@ -395,9 +396,8 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, getKillRegState(isKill)), FrameIdx)); } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { - if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || - (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { - // FIXME (64-bit): Enable + if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || + (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) .addReg(SrcReg, getKillRegState(isKill)), diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index 4cfa115fe162..5268133570f9 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -46,15 +46,14 @@ #define GET_REGINFO_TARGET_DESC #include "PPCGenRegisterInfo.inc" -// FIXME (64-bit): Eventually enable by default. namespace llvm { -cl::opt EnablePPC32RS("enable-ppc32-regscavenger", +cl::opt DisablePPC32RS("disable-ppc32-regscavenger", cl::init(false), - cl::desc("Enable PPC32 register scavenger"), + cl::desc("Disable PPC32 register scavenger"), cl::Hidden); -cl::opt EnablePPC64RS("enable-ppc64-regscavenger", +cl::opt DisablePPC64RS("disable-ppc64-regscavenger", cl::init(false), - cl::desc("Enable PPC64 register scavenger"), + cl::desc("Disable PPC64 register scavenger"), cl::Hidden); } @@ -63,8 +62,8 @@ using namespace llvm; // FIXME (64-bit): Should be inlined. bool PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { - return ((EnablePPC32RS && !Subtarget.isPPC64()) || - (EnablePPC64RS && Subtarget.isPPC64())); + return ((!DisablePPC32RS && !Subtarget.isPPC64()) || + (!DisablePPC64RS && Subtarget.isPPC64())); } PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, @@ -231,9 +230,6 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(PPC::R13); Reserved.set(PPC::R31); - if (!requiresRegisterScavenging(MF)) - Reserved.set(PPC::R0); // FIXME (64-bit): Remove - Reserved.set(PPC::X0); Reserved.set(PPC::X1); Reserved.set(PPC::X13); @@ -544,7 +540,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } // Special case for pseudo-op SPILL_CR. - if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable by default. + if (requiresRegisterScavenging(MF)) if (OpC == PPC::SPILL_CR) { lowerCRSpilling(II, FrameIndex, SPAdj, RS); return; diff --git a/llvm/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll b/llvm/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll index e50fac4472a9..d10291e190b9 100644 --- a/llvm/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=powerpc-apple-darwin -enable-ppc32-regscavenger +; RUN: llc < %s -mtriple=powerpc-apple-darwin declare i8* @bar(i32) diff --git a/llvm/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll b/llvm/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll index 9f35b8346c68..fb8cdcea63aa 100644 --- a/llvm/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll +++ b/llvm/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 -enable-ppc32-regscavenger +; RUN: llc < %s -march=ppc32 %struct._cpp_strbuf = type { i8*, i32, i32 } %struct.cpp_string = type { i32, i8* } diff --git a/llvm/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll b/llvm/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll index dd425f59822b..f256bca81885 100644 --- a/llvm/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc64 -enable-ppc64-regscavenger +; RUN: llc < %s -march=ppc64 define i16 @test(i8* %d1, i16* %d2) { %tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 ) diff --git a/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll index b2ed74fc80bf..3315750b7e18 100644 --- a/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll +++ b/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll @@ -6,11 +6,11 @@ target triple = "powerpc-apple-darwin9.6" define void @foo() nounwind { entry: -;CHECK: mfcr r2 -;CHECK: lis r0, 1 -;CHECK: rlwinm r2, r2, 8, 0, 31 -;CHECK: ori r0, r0, 34524 -;CHECK: stwx r2, r1, r0 +;CHECK: lis r4, 1 +;CHECK: ori r4, r4, 34524 +;CHECK: mfcr r3 +;CHECK: rlwinm r3, r3, 8, 0, 31 +;CHECK: stwx r3, r1, r4 %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %x1 = bitcast [100000 x i8]* %x to i8* ; [#uses=1] @@ -19,9 +19,9 @@ entry: br label %return return: ; preds = %entry -;CHECK: lis r0, 1 -;CHECK: ori r0, r0, 34524 -;CHECK: lwzx r2, r1, r0 +;CHECK: lis r3, 1 +;CHECK: ori r3, r3, 34524 +;CHECK: lwzx r2, r1, r3 ;CHECK: rlwinm r2, r2, 24, 0, 31 ;CHECK: mtcrf 32, r2 ret void diff --git a/llvm/test/CodeGen/PowerPC/Frames-alloca.ll b/llvm/test/CodeGen/PowerPC/Frames-alloca.ll index 466ae8034195..28dd08c7fed1 100644 --- a/llvm/test/CodeGen/PowerPC/Frames-alloca.ll +++ b/llvm/test/CodeGen/PowerPC/Frames-alloca.ll @@ -2,9 +2,9 @@ ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC64 ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-NOFP ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-NOFP -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32 -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS-NOFP +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32 +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32-RS +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-RS-NOFP ; CHECK-PPC32: stw r31, -4(r1) ; CHECK-PPC32: lwz r1, 0(r1) diff --git a/llvm/test/CodeGen/PowerPC/ppc32-vaarg.ll b/llvm/test/CodeGen/PowerPC/ppc32-vaarg.ll index 725c106dd6e4..c2680fbca3e1 100644 --- a/llvm/test/CodeGen/PowerPC/ppc32-vaarg.ll +++ b/llvm/test/CodeGen/PowerPC/ppc32-vaarg.ll @@ -37,8 +37,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind { ; CHECK-NEXT: stw 3, -24(1) ; CHECK-NEXT: stw 8, -28(1) ; CHECK-NEXT: stw 6, -32(1) -; CHECK-NEXT: mfcr 0 # cr0 -; CHECK-NEXT: stw 0, -36(1) +; CHECK-NEXT: mfcr 3 # cr0 +; CHECK-NEXT: stw 3, -36(1) ; CHECK-NEXT: blt 0, .LBB0_4 ; CHECK-NEXT: # BB#3: # %entry ; CHECK-NEXT: lwz 3, -20(1) @@ -82,8 +82,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind { ; CHECK-NEXT: stw 4, -52(1) ; CHECK-NEXT: stw 6, -56(1) ; CHECK-NEXT: stw 8, -60(1) -; CHECK-NEXT: mfcr 0 # cr0 -; CHECK-NEXT: stw 0, -64(1) +; CHECK-NEXT: mfcr 3 # cr0 +; CHECK-NEXT: stw 3, -64(1) ; CHECK-NEXT: blt 0, .LBB0_8 ; CHECK-NEXT: # BB#7: # %entry ; CHECK-NEXT: lwz 3, -48(1) @@ -122,8 +122,8 @@ define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind { ; CHECK-NEXT: mr 8, 5 ; CHECK-NEXT: stw 4, -72(1) ; CHECK-NEXT: stw 6, -76(1) -; CHECK-NEXT: mfcr 0 # cr0 -; CHECK-NEXT: stw 0, -80(1) +; CHECK-NEXT: mfcr 3 # cr0 +; CHECK-NEXT: stw 3, -80(1) ; CHECK-NEXT: stw 5, -84(1) ; CHECK-NEXT: stw 8, -88(1) ; CHECK-NEXT: stw 7, -92(1)