maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Revert "[AArch64] Fix data race on RegisterBank initialization." 

Buildbot failure, revert first while looking at the issue.

This reverts commit a5a4a47d69.
This commit is contained in:
Huihui Zhang 2020-01-29 11:17:19 -08:00
parent af620fc36a
commit 8f6761aa41
1 changed files with 81 additions and 84 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
View File

@ -38,14 +38,15 @@ using namespace llvm;
AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
: AArch64GenRegisterBankInfo() { : AArch64GenRegisterBankInfo() {
static llvm::once_flag InitializeRegisterBankFlag; static bool AlreadyInit = false;
static auto InitializeRegisterBankOnce = [this](const auto &TRI) {
// We have only one set of register banks, whatever the subtarget // We have only one set of register banks, whatever the subtarget
// is. Therefore, the initialization of the RegBanks table should be // is. Therefore, the initialization of the RegBanks table should be
// done only once. Indeed the table of all register banks // done only once. Indeed the table of all register banks
// (AArch64::RegBanks) is unique in the compiler. At some point, it // (AArch64::RegBanks) is unique in the compiler. At some point, it
// will get tablegen'ed and the whole constructor becomes empty. // will get tablegen'ed and the whole constructor becomes empty.
if (AlreadyInit)
return;
AlreadyInit = true;
const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
(void)RBGPR; (void)RBGPR;
@ -59,8 +60,7 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
(void)RBCCR; (void)RBCCR;
assert(&AArch64::CCRegBank == &RBCCR && assert(&AArch64::CCRegBank == &RBCCR && "The order in RegBanks is messed up");
"The order in RegBanks is messed up");
// The GPR register bank is fully defined by all the registers in // The GPR register bank is fully defined by all the registers in
// GR64all + its subclasses. // GR64all + its subclasses.
@ -199,9 +199,6 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
CHECK_VALUEMAP_FPEXT(128, 64); CHECK_VALUEMAP_FPEXT(128, 64);
assert(verify(TRI) && "Invalid register bank information"); assert(verify(TRI) && "Invalid register bank information");
};
llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce, TRI);
} }
unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A, unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A,