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Constify some things in preparation for CodeGenSubRegIndex to be stored by value in their container, removing the indirection 

llvm-svn: 222949
This commit is contained in:
David Blaikie 2014-11-29 07:04:49 +00:00
parent cdab2326b8
commit 8f25d3bc0f
3 changed files with 87 additions and 86 deletions
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43
llvm/utils/TableGen/CodeGenRegisters.cpp
View File

@ -82,7 +82,7 @@ void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
}
}
unsigned CodeGenSubRegIndex::computeLaneMask() {
unsigned CodeGenSubRegIndex::computeLaneMask() const {
// Already computed?
if (LaneMask)
return LaneMask;
@ -92,8 +92,8 @@ unsigned CodeGenSubRegIndex::computeLaneMask() {
// The lane mask is simply the union of all sub-indices.
unsigned M = 0;
for (CompMap::iterator I = Composed.begin(), E = Composed.end(); I != E; ++I)
M |= I->second->computeLaneMask();
for (const auto &C : Composed)
M |= C.second->computeLaneMask();
assert(M && "Missing lane mask, sub-register cycle?");
LaneMask = M;
return LaneMask;
@ -893,12 +893,9 @@ void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
RegClasses[rci]->inheritProperties(RegBank);
}
void
CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx,
BitVector &Out) const {
DenseMap<CodeGenSubRegIndex*,
SmallPtrSet<CodeGenRegisterClass*, 8> >::const_iterator
FindI = SuperRegClasses.find(SubIdx);
void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
BitVector &Out) const {
auto FindI = SuperRegClasses.find(SubIdx);
if (FindI == SuperRegClasses.end())
return;
for (CodeGenRegisterClass *RC : FindI->second)
@ -933,8 +930,8 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) {
for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
getSubRegIdx(SRIs[i]);
// Build composite maps from ComposedOf fields.
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
SubRegIndices[i]->updateComponents(*this);
for (auto &Idx : SubRegIndices)
Idx->updateComponents(*this);
// Read in the register definitions.
std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
@ -1013,7 +1010,6 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) {
}
CodeGenRegBank::~CodeGenRegBank() {
DeleteContainerPointers(SubRegIndices);
DeleteContainerPointers(Registers);
DeleteContainerPointers(RegClasses);
}
@ -1021,6 +1017,9 @@ CodeGenRegBank::~CodeGenRegBank() {
// Create a synthetic CodeGenSubRegIndex without a corresponding Record.
CodeGenSubRegIndex*
CodeGenRegBank::createSubRegIndex(StringRef Name, StringRef Namespace) {
//auto SubRegIndicesSize = std::distance(SubRegIndices.begin(), SubRegIndices.end());
//SubRegIndices.emplace_front(Name, Namespace, SubRegIndicesSize + 1);
//return &SubRegIndices.front();
CodeGenSubRegIndex *Idx = new CodeGenSubRegIndex(Name, Namespace,
SubRegIndices.size() + 1);
SubRegIndices.push_back(Idx);
@ -1033,6 +1032,9 @@ CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
return Idx;
Idx = new CodeGenSubRegIndex(Def, SubRegIndices.size() + 1);
SubRegIndices.push_back(Idx);
//auto SubRegIndicesSize = std::distance(SubRegIndices.begin(), SubRegIndices.end());
//SubRegIndices.emplace_front(Def, SubRegIndicesSize + 1);
//Idx = &SubRegIndices.front();
return Idx;
}
@ -1184,8 +1186,7 @@ void CodeGenRegBank::computeSubRegIndexLaneMasks() {
unsigned Bit = 0;
// Determine mask of lanes that cover their registers.
CoveringLanes = ~0u;
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
CodeGenSubRegIndex *Idx = SubRegIndices[i];
for (auto &Idx : SubRegIndices) {
if (Idx->getComposites().empty()) {
Idx->LaneMask = 1u << Bit;
// Share bit 31 in the unlikely case there are more than 32 leafs.
@ -1210,11 +1211,11 @@ void CodeGenRegBank::computeSubRegIndexLaneMasks() {
// by the sub-register graph? This doesn't occur in any known targets.
// Inherit lanes from composites.
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
unsigned Mask = SubRegIndices[i]->computeLaneMask();
for (const auto &Idx : SubRegIndices) {
unsigned Mask = Idx->computeLaneMask();
// If some super-registers without CoveredBySubRegs use this index, we can
// no longer assume that the lanes are covering their registers.
if (!SubRegIndices[i]->AllSuperRegsCovered)
if (!Idx->AllSuperRegsCovered)
CoveringLanes &= ~Mask;
}
}
@ -1787,7 +1788,7 @@ void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
//
void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
// Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
typedef std::map<CodeGenSubRegIndex*, CodeGenRegister::Set,
typedef std::map<const CodeGenSubRegIndex *, CodeGenRegister::Set,
CodeGenSubRegIndex::Less> SubReg2SetMap;
// Compute the set of registers supporting each SubRegIndex.
@ -1802,8 +1803,7 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
// Find matching classes for all SRSets entries. Iterate in SubRegIndex
// numerical order to visit synthetic indices last.
for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
CodeGenSubRegIndex *SubIdx = SubRegIndices[sri];
for (const auto &SubIdx : SubRegIndices) {
SubReg2SetMap::const_iterator I = SRSets.find(SubIdx);
// Unsupported SubRegIndex. Skip it.
if (I == SRSets.end())
@ -1835,8 +1835,7 @@ void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
BitVector TopoSigs(getNumTopoSigs());
// Iterate in SubRegIndex numerical order to visit synthetic indices last.
for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
CodeGenSubRegIndex *SubIdx = SubRegIndices[sri];
for (auto &SubIdx : SubRegIndices) {
// Skip indexes that aren't fully supported by RC's registers. This was
// computed by inferSubClassWithSubReg() above which should have been
// called first.

25
llvm/utils/TableGen/CodeGenRegisters.h
View File

@ -28,6 +28,7 @@
#include <set>
#include <string>
#include <vector>
#include <forward_list>
namespace llvm {
class CodeGenRegBank;
@ -42,7 +43,7 @@ namespace llvm {
uint16_t Size;
uint16_t Offset;
const unsigned EnumValue;
unsigned LaneMask;
mutable unsigned LaneMask;
// Are all super-registers containing this SubRegIndex covered by their
// sub-registers?
@ -101,7 +102,7 @@ namespace llvm {
const CompMap &getComposites() const { return Composed; }
// Compute LaneMask from Composed. Return LaneMask.
unsigned computeLaneMask();
unsigned computeLaneMask() const;
private:
CompMap Composed;
@ -257,15 +258,16 @@ namespace llvm {
// Map SubRegIndex -> sub-class. This is the largest sub-class where all
// registers have a SubRegIndex sub-register.
DenseMap<CodeGenSubRegIndex*, CodeGenRegisterClass*> SubClassWithSubReg;
DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
SubClassWithSubReg;
// Map SubRegIndex -> set of super-reg classes. This is all register
// classes SuperRC such that:
//
// R:SubRegIndex in this RC for all R in SuperRC.
//
DenseMap<CodeGenSubRegIndex*,
SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses;
DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
SuperRegClasses;
// Bit vector of TopoSigs for the registers in this class. This will be
// very sparse on regular architectures.
@ -314,19 +316,20 @@ namespace llvm {
// getSubClassWithSubReg - Returns the largest sub-class where all
// registers have a SubIdx sub-register.
CodeGenRegisterClass*
getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
CodeGenRegisterClass *
getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
return SubClassWithSubReg.lookup(SubIdx);
}
void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx,
void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
CodeGenRegisterClass *SubRC) {
SubClassWithSubReg[SubIdx] = SubRC;
}
// getSuperRegClasses - Returns a bit vector of all register classes
// containing only SubIdx super-registers of this class.
void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
BitVector &Out) const;
// addSuperRegClass - Add a class containing only SudIdx super-registers.
void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
@ -446,7 +449,7 @@ namespace llvm {
class CodeGenRegBank {
SetTheory Sets;
// SubRegIndices.
//std::forward_list<CodeGenSubRegIndex> SubRegIndices;
std::vector<CodeGenSubRegIndex*> SubRegIndices;
DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
@ -528,7 +531,7 @@ namespace llvm {
// Sub-register indices. The first NumNamedIndices are defined by the user
// in the .td files. The rest are synthesized such that all sub-registers
// have a unique name.
ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; }
std::vector<CodeGenSubRegIndex*> &getSubRegIndices() { return SubRegIndices; }
// Find a SubRegIndex form its Record def.
CodeGenSubRegIndex *getSubRegIdx(Record*);

105
llvm/utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -137,16 +137,16 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS,
OS << "}\n";
}
ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
auto &SubRegIndices = Bank.getSubRegIndices();
if (!SubRegIndices.empty()) {
OS << "\n// Subregister indices\n";
std::string Namespace =
SubRegIndices[0]->getNamespace();
std::string Namespace = SubRegIndices.front()->getNamespace();
if (!Namespace.empty())
OS << "namespace " << Namespace << " {\n";
OS << "enum {\n NoSubRegister,\n";
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
unsigned i = 0;
for (const auto &Idx : SubRegIndices)
OS << " " << Idx->getName() << ",\t// " << ++i << "\n";
OS << " NUM_TARGET_SUBREGS\n};\n";
if (!Namespace.empty())
OS << "}\n";
@ -628,7 +628,7 @@ void
RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
CodeGenRegBank &RegBank,
const std::string &ClName) {
ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
const auto &SubRegIndices = RegBank.getSubRegIndices();
OS << "unsigned " << ClName
<< "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";
@ -643,10 +643,12 @@ RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
SmallVector<unsigned, 4> RowMap;
SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows;
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
auto SubRegIndicesSize =
std::distance(SubRegIndices.begin(), SubRegIndices.end());
for (const auto &Idx : SubRegIndices) {
unsigned Found = ~0u;
for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
if (combine(SubRegIndices[i], Rows[r])) {
if (combine(Idx, Rows[r])) {
Found = r;
break;
}
@ -654,27 +656,27 @@ RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
if (Found == ~0u) {
Found = Rows.size();
Rows.resize(Found + 1);
Rows.back().resize(SubRegIndices.size());
combine(SubRegIndices[i], Rows.back());
Rows.back().resize(SubRegIndicesSize);
combine(Idx, Rows.back());
}
RowMap.push_back(Found);
}
// Output the row map if there is multiple rows.
if (Rows.size() > 1) {
OS << " static const " << getMinimalTypeForRange(Rows.size())
<< " RowMap[" << SubRegIndices.size() << "] = {\n ";
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
OS << " static const " << getMinimalTypeForRange(Rows.size()) << " RowMap["
<< SubRegIndicesSize << "] = {\n ";
for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
OS << RowMap[i] << ", ";
OS << "\n };\n";
}
// Output the rows.
OS << " static const " << getMinimalTypeForRange(SubRegIndices.size()+1)
<< " Rows[" << Rows.size() << "][" << SubRegIndices.size() << "] = {\n";
OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1)
<< " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n";
for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
OS << " { ";
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
if (Rows[r][i])
OS << Rows[r][i]->EnumValue << ", ";
else
@ -683,8 +685,8 @@ RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
}
OS << " };\n\n";
OS << " --IdxA; assert(IdxA < " << SubRegIndices.size() << ");\n"
<< " --IdxB; assert(IdxB < " << SubRegIndices.size() << ");\n";
OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n"
<< " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";
if (Rows.size() > 1)
OS << " return Rows[RowMap[IdxA]][IdxB];\n";
else
@ -705,7 +707,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
auto &SubRegIndices = RegBank.getSubRegIndices();
// The lists of sub-registers and super-registers go in the same array. That
// allows us to share suffixes.
typedef std::vector<const CodeGenRegister*> RegVec;
@ -797,12 +799,10 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << "extern const MCRegisterInfo::SubRegCoveredBits "
<< TargetName << "SubRegIdxRanges[] = {\n";
OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
for (ArrayRef<CodeGenSubRegIndex*>::const_iterator
SRI = SubRegIndices.begin(), SRE = SubRegIndices.end();
SRI != SRE; ++SRI) {
OS << " { " << (*SRI)->Offset << ", "
<< (*SRI)->Size
<< " },\t// " << (*SRI)->getName() << "\n";
for (const auto &Idx : SubRegIndices) {
OS << " { " << Idx->Offset << ", "
<< Idx->Size
<< " },\t// " << Idx->getName() << "\n";
}
OS << "};\n\n";
@ -933,19 +933,17 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
// MCRegisterInfo initialization routine.
OS << "static inline void Init" << TargetName
<< "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
<< "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {\n"
<< "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) "
"{\n"
<< " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
<< Regs.size()+1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
<< RegisterClasses.size() << ", "
<< TargetName << "RegUnitRoots, "
<< RegBank.getNumNativeRegUnits() << ", "
<< TargetName << "RegDiffLists, "
<< TargetName << "RegStrings, "
<< TargetName << "RegClassStrings, "
<< Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
<< RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "
<< RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
<< TargetName << "RegStrings, " << TargetName << "RegClassStrings, "
<< TargetName << "SubRegIdxLists, "
<< (SubRegIndices.size() + 1) << ",\n"
<< TargetName << "SubRegIdxRanges, "
<< TargetName << "RegEncodingTable);\n\n";
<< (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n"
<< TargetName << "SubRegIdxRanges, " << TargetName
<< "RegEncodingTable);\n\n";
EmitRegMapping(OS, Regs, false);
@ -1031,7 +1029,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Start out by emitting each of the register classes.
ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
const auto &SubRegIndices = RegBank.getSubRegIndices();
// Collect all registers belonging to any allocatable class.
std::set<Record*> AllocatableRegs;
@ -1056,18 +1054,18 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit SubRegIndex names, skipping 0.
OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
OS << SubRegIndices[i]->getName();
if (i + 1 != e)
OS << "\", \"";
for (const auto &Idx : SubRegIndices) {
OS << Idx->getName();
OS << "\", \"";
}
OS << "\" };\n\n";
// Emit SubRegIndex lane masks, including 0.
OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n";
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
OS << format(" 0x%08x, // ", SubRegIndices[i]->LaneMask)
<< SubRegIndices[i]->getName() << '\n';
for (const auto &Idx : SubRegIndices) {
OS << format(" 0x%08x, // ", Idx->LaneMask)
<< Idx->getName() << '\n';
}
OS << " };\n\n";
@ -1110,8 +1108,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit super-reg class masks for any relevant SubRegIndices that can
// project into RC.
IdxList &SRIList = SuperRegIdxLists[rc];
for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
CodeGenSubRegIndex *Idx = SubRegIndices[sri];
for (auto &Idx : SubRegIndices) {
MaskBV.reset();
RC.getSuperRegClasses(Idx, MaskBV);
if (MaskBV.none())
@ -1232,6 +1229,9 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
std::string ClassName = Target.getName() + "GenRegisterInfo";
auto SubRegIndicesSize =
std::distance(SubRegIndices.begin(), SubRegIndices.end());
if (!SubRegIndices.empty())
emitComposeSubRegIndices(OS, RegBank, ClassName);
@ -1248,12 +1248,11 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << " static const uint16_t Table[";
else
PrintFatalError("Too many register classes.");
OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
const CodeGenRegisterClass &RC = *RegisterClasses[rci];
OS << " {\t// " << RC.getName() << "\n";
for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
CodeGenSubRegIndex *Idx = SubRegIndices[sri];
for (auto &Idx : SubRegIndices) {
if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
<< " -> " << SRC->getName() << "\n";
@ -1264,7 +1263,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
}
OS << " };\n assert(RC && \"Missing regclass\");\n"
<< " if (!Idx) return RC;\n --Idx;\n"
<< " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
<< " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n"
<< " unsigned TV = Table[RC->getID()][Idx];\n"
<< " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
}
@ -1291,8 +1290,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x";
OS.write_hex(RegBank.CoveringLanes);
OS << ") {\n"
<< " InitMCRegisterInfo(" << TargetName << "RegDesc, "
<< Regs.size()+1 << ", RA, PC,\n " << TargetName
<< " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
<< ", RA, PC,\n " << TargetName
<< "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
<< " " << TargetName << "RegUnitRoots,\n"
<< " " << RegBank.getNumNativeRegUnits() << ",\n"
@ -1300,7 +1299,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< " " << TargetName << "RegStrings,\n"
<< " " << TargetName << "RegClassStrings,\n"
<< " " << TargetName << "SubRegIdxLists,\n"
<< " " << SubRegIndices.size() + 1 << ",\n"
<< " " << SubRegIndicesSize + 1 << ",\n"
<< " " << TargetName << "SubRegIdxRanges,\n"
<< " " << TargetName << "RegEncodingTable);\n\n";