forked from OSchip/llvm-project
[x86] make some of the tests 256-bit for testing diversity
llvm-svn: 275070
This commit is contained in:
Sanjay Patel
parent
57033c6336
commit
8f1d408c74
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@ -290,22 +290,35 @@ define <16 x i8> @cmpeq_zext_v16i8(<16 x i8> %a, <16 x i8> %b) {
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ret <16 x i8> %zext
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}
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define <8 x i16> @cmpeq_zext_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; SSE-LABEL: cmpeq_zext_v8i16:
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define <16 x i16> @cmpeq_zext_v16i16(<16 x i16> %a, <16 x i16> %b) {
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; SSE-LABEL: cmpeq_zext_v16i16:
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; SSE: # BB#0:
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; SSE-NEXT: pcmpeqw %xmm1, %xmm0
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: pcmpeqw %xmm2, %xmm0
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; SSE-NEXT: movdqa {{.*#+}} xmm2 = [1,1,1,1,1,1,1,1]
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: pcmpeqw %xmm3, %xmm1
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; SSE-NEXT: pand %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: cmpeq_zext_v8i16:
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; AVX: # BB#0:
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; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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; AVX1-LABEL: cmpeq_zext_v16i16:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
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; AVX1-NEXT: vpcmpeqw %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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%cmp = icmp eq <8 x i16> %a, %b
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%zext = zext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %zext
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; AVX2-LABEL: cmpeq_zext_v16i16:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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%cmp = icmp eq <16 x i16> %a, %b
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%zext = zext <16 x i1> %cmp to <16 x i16>
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ret <16 x i16> %zext
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}
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define <4 x i32> @cmpeq_zext_v4i32(<4 x i32> %a, <4 x i32> %b) {
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@ -333,48 +346,80 @@ define <4 x i32> @cmpeq_zext_v4i32(<4 x i32> %a, <4 x i32> %b) {
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ret <4 x i32> %zext
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}
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define <2 x i64> @cmpeq_zext_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; SSE2-LABEL: cmpeq_zext_v2i64:
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define <4 x i64> @cmpeq_zext_v4i64(<4 x i64> %a, <4 x i64> %b) {
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; SSE2-LABEL: cmpeq_zext_v4i64:
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; SSE2: # BB#0:
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; SSE2-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,3,2]
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; SSE2-NEXT: pand %xmm1, %xmm0
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; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE2-NEXT: pcmpeqd %xmm2, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,0,3,2]
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; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [1,1]
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; SSE2-NEXT: pand %xmm4, %xmm2
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; SSE2-NEXT: pand %xmm2, %xmm0
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; SSE2-NEXT: pcmpeqd %xmm3, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,0,3,2]
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; SSE2-NEXT: pand %xmm4, %xmm2
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; SSE2-NEXT: pand %xmm2, %xmm1
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; SSE2-NEXT: retq
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;
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; SSE42-LABEL: cmpeq_zext_v2i64:
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; SSE42-LABEL: cmpeq_zext_v4i64:
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; SSE42: # BB#0:
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; SSE42-NEXT: pcmpeqq %xmm1, %xmm0
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; SSE42-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE42-NEXT: pcmpeqq %xmm2, %xmm0
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; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [1,1]
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; SSE42-NEXT: pand %xmm2, %xmm0
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; SSE42-NEXT: pcmpeqq %xmm3, %xmm1
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; SSE42-NEXT: pand %xmm2, %xmm1
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; SSE42-NEXT: retq
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;
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; AVX-LABEL: cmpeq_zext_v2i64:
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; AVX: # BB#0:
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; AVX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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; AVX1-LABEL: cmpeq_zext_v4i64:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
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; AVX1-NEXT: vpcmpeqq %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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%cmp = icmp eq <2 x i64> %a, %b
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%zext = zext <2 x i1> %cmp to <2 x i64>
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ret <2 x i64> %zext
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; AVX2-LABEL: cmpeq_zext_v4i64:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vpbroadcastq {{.*}}(%rip), %ymm1
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; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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%cmp = icmp eq <4 x i64> %a, %b
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%zext = zext <4 x i1> %cmp to <4 x i64>
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ret <4 x i64> %zext
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}
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define <16 x i8> @cmpgt_zext_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; SSE-LABEL: cmpgt_zext_v16i8:
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define <32 x i8> @cmpgt_zext_v32i8(<32 x i8> %a, <32 x i8> %b) {
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; SSE-LABEL: cmpgt_zext_v32i8:
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; SSE: # BB#0:
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; SSE-NEXT: pcmpgtb %xmm1, %xmm0
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: pcmpgtb %xmm2, %xmm0
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; SSE-NEXT: movdqa {{.*#+}} xmm2 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: pcmpgtb %xmm3, %xmm1
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; SSE-NEXT: pand %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: cmpgt_zext_v16i8:
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; AVX: # BB#0:
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; AVX-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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; AVX1-LABEL: cmpgt_zext_v32i8:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
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; AVX1-NEXT: vpcmpgtb %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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%cmp = icmp sgt <16 x i8> %a, %b
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%zext = zext <16 x i1> %cmp to <16 x i8>
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ret <16 x i8> %zext
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; AVX2-LABEL: cmpgt_zext_v32i8:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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%cmp = icmp sgt <32 x i8> %a, %b
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%zext = zext <32 x i1> %cmp to <32 x i8>
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ret <32 x i8> %zext
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}
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define <8 x i16> @cmpgt_zext_v8i16(<8 x i16> %a, <8 x i16> %b) {
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@ -395,29 +440,36 @@ define <8 x i16> @cmpgt_zext_v8i16(<8 x i16> %a, <8 x i16> %b) {
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ret <8 x i16> %zext
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}
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define <4 x i32> @cmpgt_zext_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; SSE-LABEL: cmpgt_zext_v4i32:
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define <8 x i32> @cmpgt_zext_v8i32(<8 x i32> %a, <8 x i32> %b) {
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; SSE-LABEL: cmpgt_zext_v8i32:
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; SSE: # BB#0:
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; SSE-NEXT: pcmpgtd %xmm1, %xmm0
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: pcmpgtd %xmm2, %xmm0
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; SSE-NEXT: movdqa {{.*#+}} xmm2 = [1,1,1,1]
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: pcmpgtd %xmm3, %xmm1
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; SSE-NEXT: pand %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: cmpgt_zext_v4i32:
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; AVX1-LABEL: cmpgt_zext_v8i32:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
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; AVX1-NEXT: vpcmpgtd %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: cmpgt_zext_v4i32:
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; AVX2-LABEL: cmpgt_zext_v8i32:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
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; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %ymm1
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; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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%cmp = icmp sgt <4 x i32> %a, %b
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%zext = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %zext
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%cmp = icmp sgt <8 x i32> %a, %b
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%zext = zext <8 x i1> %cmp to <8 x i32>
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ret <8 x i32> %zext
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}
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define <2 x i64> @cmpgt_zext_v2i64(<2 x i64> %a, <2 x i64> %b) {
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