forked from OSchip/llvm-project
AMDGPU: Stop reserving v[254:255]
This wasn't doing anything useful. They weren't explicitly used anywhere, and the RegScavenger ignores reserved registers. This for some reason caused a random scheduling change in the test. Getting the check lines to pass is too frustrating, and there's probably not too much value in checking the vector case's operands N times. llvm-svn: 250794
This commit is contained in:
Matt Arsenault
parent
c8f89e86d5
commit
8f18917a90
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@ -41,10 +41,6 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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reserveRegisterTuples(Reserved, AMDGPU::EXEC);
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reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
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// Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
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reserveRegisterTuples(Reserved, AMDGPU::VGPR254);
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reserveRegisterTuples(Reserved, AMDGPU::VGPR255);
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// Tonga and Iceland can only allocate a fixed number of SGPRs due
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// to a hw bug.
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if (MF.getSubtarget<AMDGPUSubtarget>().hasSGPRInitBug()) {
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@ -257,83 +257,83 @@ define void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i3
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; SI-DAG: v_rcp_iflag_f32_e32 [[FIRST_RCP:v[0-9]+]]
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; SI-DAG: v_mul_hi_u32 [[FIRST_RCP_HI:v[0-9]+]], [[FIRST_RCP]]
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; SI-DAG: v_mul_lo_i32 [[FIRST_RCP_LO:v[0-9]+]], [[FIRST_RCP]]
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; SI-DAG: v_sub_i32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], vcc, 0, [[FIRST_RCP_LO]]
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; SI-DAG: v_rcp_iflag_f32_e32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_sub_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[FIRST_E:v[0-9]+]], {{v[0-9]+}}, [[FIRST_RCP]]
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; SI-DAG: v_add_i32_e32 [[FIRST_RCP_A_E:v[0-9]+]], vcc, [[FIRST_E]], [[FIRST_RCP]]
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; SI-DAG: v_subrev_i32_e32 [[FIRST_RCP_S_E:v[0-9]+]], vcc, [[FIRST_E]], [[FIRST_RCP]]
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_add_i32_e32
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; SI-DAG: v_subrev_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[FIRST_Quotient:v[0-9]+]]
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; SI-DAG: v_mul_lo_i32 [[FIRST_Num_S_Remainder:v[0-9]+]]
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; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder:v[l0-9]+]], vcc, [[FIRST_Num_S_Remainder]], v{{[0-9]+}}
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_subrev_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_and_b32_e32 [[FIRST_Tmp1:v[0-9]+]]
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; SI-DAG: v_add_i32_e32 [[FIRST_Quotient_A_One:v[0-9]+]], {{.*}}, [[FIRST_Quotient]]
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; SI-DAG: v_subrev_i32_e32 [[FIRST_Quotient_S_One:v[0-9]+]],
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; SI-DAG: v_and_b32_e32
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; SI-DAG: v_add_i32_e32
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; SI-DAG: v_subrev_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_i32_e32 [[FIRST_Remainder_A_Den:v[0-9]+]],
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; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder_S_Den:v[0-9]+]],
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; SI-DAG: v_add_i32_e32
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; SI-DAG: v_subrev_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_rcp_iflag_f32_e32 [[SECOND_RCP:v[0-9]+]]
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; SI-DAG: v_mul_hi_u32 [[SECOND_RCP_HI:v[0-9]+]], [[SECOND_RCP]]
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; SI-DAG: v_mul_lo_i32 [[SECOND_RCP_LO:v[0-9]+]], [[SECOND_RCP]]
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; SI-DAG: v_sub_i32_e32 [[SECOND_NEG_RCP_LO:v[0-9]+]], vcc, 0, [[SECOND_RCP_LO]]
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; SI-DAG: v_rcp_iflag_f32_e32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_sub_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[SECOND_E:v[0-9]+]], {{v[0-9]+}}, [[SECOND_RCP]]
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; SI-DAG: v_add_i32_e32 [[SECOND_RCP_A_E:v[0-9]+]], vcc, [[SECOND_E]], [[SECOND_RCP]]
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; SI-DAG: v_subrev_i32_e32 [[SECOND_RCP_S_E:v[0-9]+]], vcc, [[SECOND_E]], [[SECOND_RCP]]
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_add_i32_e32
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; SI-DAG: v_subrev_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[SECOND_Quotient:v[0-9]+]]
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; SI-DAG: v_mul_lo_i32 [[SECOND_Num_S_Remainder:v[0-9]+]]
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; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder:v[0-9]+]], vcc, [[SECOND_Num_S_Remainder]], v{{[0-9]+}}
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_subrev_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_and_b32_e32 [[SECOND_Tmp1:v[0-9]+]]
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; SI-DAG: v_add_i32_e32 [[SECOND_Quotient_A_One:v[0-9]+]], {{.*}}, [[SECOND_Quotient]]
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; SI-DAG: v_subrev_i32_e32 [[SECOND_Quotient_S_One:v[0-9]+]],
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; SI-DAG: v_and_b32_e32
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; SI-DAG: v_add_i32_e32
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; SI-DAG: v_subrev_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_i32_e32 [[SECOND_Remainder_A_Den:v[0-9]+]],
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; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder_S_Den:v[0-9]+]],
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; SI-DAG: v_add_i32_e32
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; SI-DAG: v_subrev_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_rcp_iflag_f32_e32 [[THIRD_RCP:v[0-9]+]]
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; SI-DAG: v_mul_hi_u32 [[THIRD_RCP_HI:v[0-9]+]], [[THIRD_RCP]]
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; SI-DAG: v_mul_lo_i32 [[THIRD_RCP_LO:v[0-9]+]], [[THIRD_RCP]]
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; SI-DAG: v_sub_i32_e32 [[THIRD_NEG_RCP_LO:v[0-9]+]], vcc, 0, [[THIRD_RCP_LO]]
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; SI-DAG: v_rcp_iflag_f32_e32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_sub_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[THIRD_E:v[0-9]+]], {{v[0-9]+}}, [[THIRD_RCP]]
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; SI-DAG: v_add_i32_e32 [[THIRD_RCP_A_E:v[0-9]+]], vcc, [[THIRD_E]], [[THIRD_RCP]]
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; SI-DAG: v_subrev_i32_e32 [[THIRD_RCP_S_E:v[0-9]+]], vcc, [[THIRD_E]], [[THIRD_RCP]]
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_add_i32_e32
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; SI-DAG: v_subrev_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[THIRD_Quotient:v[0-9]+]]
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; SI-DAG: v_mul_lo_i32 [[THIRD_Num_S_Remainder:v[0-9]+]]
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; SI-DAG: v_subrev_i32_e32 [[THIRD_Remainder:v[0-9]+]], vcc, [[THIRD_Num_S_Remainder]], {{v[0-9]+}}
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_subrev_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_and_b32_e32 [[THIRD_Tmp1:v[0-9]+]]
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; SI-DAG: v_add_i32_e32 [[THIRD_Quotient_A_One:v[0-9]+]], {{.*}}, [[THIRD_Quotient]]
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; SI-DAG: v_subrev_i32_e32 [[THIRD_Quotient_S_One:v[0-9]+]],
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; SI-DAG: v_and_b32_e32
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; SI-DAG: v_add_i32_e32
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; SI-DAG: v_subrev_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_i32_e32 [[THIRD_Remainder_A_Den:v[0-9]+]],
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; SI-DAG: v_subrev_i32_e32 [[THIRD_Remainder_S_Den:v[0-9]+]],
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; SI-DAG: v_add_i32_e32
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; SI-DAG: v_subrev_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_rcp_iflag_f32_e32 [[FOURTH_RCP:v[0-9]+]]
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; SI-DAG: v_mul_hi_u32 [[FOURTH_RCP_HI:v[0-9]+]], [[FOURTH_RCP]]
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; SI-DAG: v_mul_lo_i32 [[FOURTH_RCP_LO:v[0-9]+]], [[FOURTH_RCP]]
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; SI-DAG: v_sub_i32_e32 [[FOURTH_NEG_RCP_LO:v[0-9]+]], vcc, 0, [[FOURTH_RCP_LO]]
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; SI-DAG: v_rcp_iflag_f32_e32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_sub_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32 [[FOURTH_E:v[0-9]+]], {{v[0-9]+}}, [[FOURTH_RCP]]
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; SI-DAG: v_add_i32_e32 [[FOURTH_RCP_A_E:v[0-9]+]], vcc, [[FOURTH_E]], [[FOURTH_RCP]]
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; SI-DAG: v_subrev_i32_e32 [[FOURTH_RCP_S_E:v[0-9]+]], vcc, [[FOURTH_E]], [[FOURTH_RCP]]
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_add_i32_e32
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; SI-DAG: v_subrev_i32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI: s_endpgm
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define void @test_udivrem_v4(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
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