From 8f1646b579c4ab68c663c92e480b4a10d9c4d70e Mon Sep 17 00:00:00 2001 From: Gabor Buella Date: Mon, 16 Apr 2018 07:47:35 +0000 Subject: [PATCH] [X86] Introduce archs: goldmont-plus & tremont Using Goldmont's cost tables for these two upcoming atom archs. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45612 llvm-svn: 330109 --- llvm/include/llvm/Support/X86TargetParser.def | 2 + llvm/lib/Support/Host.cpp | 4 +- llvm/lib/Target/X86/X86.td | 48 ++++++++++++++----- llvm/lib/Target/X86/X86Subtarget.h | 8 +++- llvm/test/CodeGen/X86/cpus.ll | 2 + 5 files changed, 50 insertions(+), 14 deletions(-) diff --git a/llvm/include/llvm/Support/X86TargetParser.def b/llvm/include/llvm/Support/X86TargetParser.def index 5c8c576b1027..e4af0657a350 100644 --- a/llvm/include/llvm/Support/X86TargetParser.def +++ b/llvm/include/llvm/Support/X86TargetParser.def @@ -65,6 +65,8 @@ X86_CPU_TYPE ("athlon-xp", AMD_ATHLON_XP) X86_CPU_TYPE ("k8", AMD_K8) X86_CPU_TYPE ("k8-sse3", AMD_K8SSE3) X86_CPU_TYPE ("goldmont", INTEL_GOLDMONT) +X86_CPU_TYPE ("goldmont-plus", INTEL_GOLDMONT_PLUS) +X86_CPU_TYPE ("tremont", INTEL_TREMONT) #undef X86_CPU_TYPE_COMPAT_WITH_ALIAS #undef X86_CPU_TYPE_COMPAT #undef X86_CPU_TYPE diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp index 4df1102cf265..3337d8adb37b 100644 --- a/llvm/lib/Support/Host.cpp +++ b/llvm/lib/Support/Host.cpp @@ -651,9 +651,11 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, // Goldmont: case 0x5c: // Apollo Lake case 0x5f: // Denverton - case 0x7a: // Gemini Lake *Type = X86::INTEL_GOLDMONT; break; // "goldmont" + case 0x7a: + *Type = X86::INTEL_GOLDMONT_PLUS; + break; case 0x57: *Type = X86::INTEL_KNL; // knl break; diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 10e8e1362707..aa1470ebf51e 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -413,6 +413,10 @@ def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM", "Intel Silvermont processors">; def ProcIntelGLM : SubtargetFeature<"glm", "X86ProcFamily", "IntelGLM", "Intel Goldmont processors">; +def ProcIntelGLP : SubtargetFeature<"glp", "X86ProcFamily", "IntelGLP", + "Intel Goldmont Plus processors">; +def ProcIntelTRM : SubtargetFeature<"tremont", "X86ProcFamily", "IntelTRM", + "Intel Tremont processors">; def ProcIntelHSW : SubtargetFeature<"haswell", "X86ProcFamily", "IntelHaswell", "Intel Haswell processors">; def ProcIntelBDW : SubtargetFeature<"broadwell", "X86ProcFamily", @@ -564,8 +568,17 @@ class SilvermontProc : ProcessorModel; def : SilvermontProc<"slm">; // Legacy alias. -class GoldmontProc : ProcessorModel Inherited, + list NewFeatures> { + list Value = !listconcat(Inherited, NewFeatures); +} + +class ProcModel ProcFeatures, + list OtherFeatures> : + ProcessorModel; + +def GLMFeatures : ProcessorFeatures<[], [ FeatureX87, FeatureMMX, FeatureSSE42, @@ -592,8 +605,29 @@ class GoldmontProc : ProcessorModel; + +class GoldmontProc : ProcModel; def : GoldmontProc<"goldmont">; +class GoldmontPlusProc : ProcModel; +def : GoldmontPlusProc<"goldmont-plus">; + +class TremontProc : ProcModel; +def : TremontProc<"tremont">; + // "Arrandale" along with corei3 and corei5 class NehalemProc : ProcessorModel : ProcessorModel; def : WestmereProc<"westmere">; -class ProcessorFeatures Inherited, - list NewFeatures> { - list Value = !listconcat(Inherited, NewFeatures); -} - -class ProcModel ProcFeatures, - list OtherFeatures> : - ProcessorModel; - // SSE is not listed here since llvm treats AVX as a reimplementation of SSE, // rather than a superset. def SNBFeatures : ProcessorFeatures<[], [ diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h index 894aef20e0eb..4665e2ddf184 100644 --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -56,6 +56,8 @@ public: IntelAtom, IntelSLM, IntelGLM, + IntelGLP, + IntelTRM, IntelHaswell, IntelBroadwell, IntelSkylake, @@ -660,7 +662,11 @@ public: /// TODO: to be removed later and replaced with suitable properties bool isAtom() const { return X86ProcFamily == IntelAtom; } bool isSLM() const { return X86ProcFamily == IntelSLM; } - bool isGLM() const { return X86ProcFamily == IntelGLM; } + bool isGLM() const { + return X86ProcFamily == IntelGLM || + X86ProcFamily == IntelGLP || + X86ProcFamily == IntelTRM; + } bool useSoftFloat() const { return UseSoftFloat; } /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for diff --git a/llvm/test/CodeGen/X86/cpus.ll b/llvm/test/CodeGen/X86/cpus.ll index c01868a937bb..c1e783a00198 100644 --- a/llvm/test/CodeGen/X86/cpus.ll +++ b/llvm/test/CodeGen/X86/cpus.ll @@ -53,6 +53,8 @@ ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=silvermont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=slm 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=goldmont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=goldmont-plus 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tremont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=knl 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=knm 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty