forked from OSchip/llvm-project
[Hexagon] Add a target feature to disable compound instructions
This affects the following instructions: Tag: M4_mpyrr_addr Syntax: Ry32 = add(Ru32,mpyi(Ry32,Rs32)) Tag: M4_mpyri_addr_u2 Syntax: Rd32 = add(Ru32,mpyi(#u6:2,Rs32)) Tag: M4_mpyri_addr Syntax: Rd32 = add(Ru32,mpyi(Rs32,#u6)) Tag: M4_mpyri_addi Syntax: Rd32 = add(#u6,mpyi(Rs32,#U6)) Tag: M4_mpyrr_addi Syntax: Rd32 = add(#u6,mpyi(Rs32,Rt32)) Tag: S4_addaddi Syntax: Rd32 = add(Rs32,add(Ru32,#s6)) Tag: S4_subaddi Syntax: Rd32 = add(Rs32,sub(#s6,Ru32)) Tag: S4_or_andix Syntax: Rx32 = or(Ru32,and(Rx32,#s10)) Tag: S4_andi_asl_ri Syntax: Rx32 = and(#u8,asl(Rx32,#U5)) Tag: S4_ori_asl_ri Syntax: Rx32 = or(#u8,asl(Rx32,#U5)) Tag: S4_addi_asl_ri Syntax: Rx32 = add(#u8,asl(Rx32,#U5)) Tag: S4_subi_asl_ri Syntax: Rx32 = sub(#u8,asl(Rx32,#U5)) Tag: S4_andi_lsr_ri Syntax: Rx32 = and(#u8,lsr(Rx32,#U5)) Tag: S4_ori_lsr_ri Syntax: Rx32 = or(#u8,lsr(Rx32,#U5)) Tag: S4_addi_lsr_ri Syntax: Rx32 = add(#u8,lsr(Rx32,#U5)) Tag: S4_subi_lsr_ri Syntax: Rx32 = sub(#u8,lsr(Rx32,#U5))
This commit is contained in:
Krzysztof Parzyszek
parent
870094decf
commit
8ee2d16896
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@ -48,6 +48,8 @@ def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
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def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps",
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"true", "Hexagon HVX 128B instructions", [ExtensionHVX]>;
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def FeatureCompound: SubtargetFeature<"compound", "UseCompound", "true",
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"Use compound instructions">;
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def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true",
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"Support for instruction packets">;
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def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
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@ -91,6 +93,7 @@ def UseHVXV66 : Predicate<"HST->useHVXOps()">,
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AssemblerPredicate<"ExtensionHVXV66">;
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def UseZReg : Predicate<"HST->useZRegOps()">,
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AssemblerPredicate<"ExtensionZReg">;
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def UseCompound : Predicate<"HST->useCompound()">;
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def Hvx64: HwMode<"+hvx-length64b">;
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def Hvx128: HwMode<"+hvx-length128b">;
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@ -335,32 +338,32 @@ class Proc<string Name, SchedMachineModel Model,
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def : Proc<"generic", HexagonModelV60,
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[ArchV5, ArchV55, ArchV60,
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FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
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FeaturePackets, FeatureSmallData]>;
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FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
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FeatureNVS, FeaturePackets, FeatureSmallData]>;
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def : Proc<"hexagonv5", HexagonModelV5,
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[ArchV5,
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FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
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FeaturePackets, FeatureSmallData]>;
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FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
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FeatureNVS, FeaturePackets, FeatureSmallData]>;
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def : Proc<"hexagonv55", HexagonModelV55,
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[ArchV5, ArchV55,
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FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
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FeaturePackets, FeatureSmallData]>;
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FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
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FeatureNVS, FeaturePackets, FeatureSmallData]>;
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def : Proc<"hexagonv60", HexagonModelV60,
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[ArchV5, ArchV55, ArchV60,
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FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
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FeaturePackets, FeatureSmallData]>;
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FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
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FeatureNVS, FeaturePackets, FeatureSmallData]>;
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def : Proc<"hexagonv62", HexagonModelV62,
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[ArchV5, ArchV55, ArchV60, ArchV62,
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FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
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FeaturePackets, FeatureSmallData]>;
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FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
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FeatureNVS, FeaturePackets, FeatureSmallData]>;
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def : Proc<"hexagonv65", HexagonModelV65,
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[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
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FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
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FeatureNVS, FeaturePackets, FeatureSmallData]>;
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FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
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FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
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def : Proc<"hexagonv66", HexagonModelV66,
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[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66,
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FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
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FeatureNVS, FeaturePackets, FeatureSmallData]>;
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FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
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FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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@ -379,6 +379,7 @@ namespace {
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using AssignmentMap = std::map<ExtenderInit, IndexList>;
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using LocDefList = std::vector<std::pair<Loc, IndexList>>;
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const HexagonSubtarget *HST = nullptr;
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const HexagonInstrInfo *HII = nullptr;
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const HexagonRegisterInfo *HRI = nullptr;
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MachineDominatorTree *MDT = nullptr;
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@ -1562,13 +1563,31 @@ HCE::Register HCE::insertInitializer(Loc DefL, const ExtenderInit &ExtI) {
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.add(ExtOp);
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}
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} else {
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unsigned NewOpc = Ex.Neg ? Hexagon::S4_subi_asl_ri
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: Hexagon::S4_addi_asl_ri;
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// DefR = add(##EV,asl(Rb,S))
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InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR)
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.add(ExtOp)
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.add(MachineOperand(Ex.Rs))
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.addImm(Ex.S);
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if (HST->useCompound()) {
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unsigned NewOpc = Ex.Neg ? Hexagon::S4_subi_asl_ri
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: Hexagon::S4_addi_asl_ri;
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// DefR = add(##EV,asl(Rb,S))
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InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR)
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.add(ExtOp)
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.add(MachineOperand(Ex.Rs))
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.addImm(Ex.S);
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} else {
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// No compounds are available. It is not clear whether we should
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// even process such extenders where the initializer cannot be
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// a single instruction, but do it for now.
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unsigned TmpR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
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BuildMI(MBB, At, dl, HII->get(Hexagon::S2_asl_i_r), TmpR)
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.add(MachineOperand(Ex.Rs))
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.addImm(Ex.S);
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if (Ex.Neg)
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InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR)
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.add(ExtOp)
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.add(MachineOperand(Register(TmpR, 0)));
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else
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InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR)
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.add(MachineOperand(Register(TmpR, 0)))
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.add(ExtOp);
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}
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}
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}
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@ -1952,8 +1971,9 @@ bool HCE::runOnMachineFunction(MachineFunction &MF) {
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}
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LLVM_DEBUG(MF.print(dbgs() << "Before " << getPassName() << '\n', nullptr));
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HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
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HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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HST = &MF.getSubtarget<HexagonSubtarget>();
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HII = HST->getInstrInfo();
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HRI = HST->getRegisterInfo();
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MDT = &getAnalysis<MachineDominatorTree>();
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MRI = &MF.getRegInfo();
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AssignmentMap IMap;
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@ -17106,7 +17106,7 @@ def M4_mpyri_addi : HInst<
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(outs IntRegs:$Rd32),
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(ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II),
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"$Rd32 = add(#$Ii,mpyi($Rs32,#$II))",
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tc_05d3a09b, TypeALU64>, Enc_322e1b, ImmRegRel {
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tc_05d3a09b, TypeALU64>, Enc_322e1b, Requires<[UseCompound]>, ImmRegRel {
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let Inst{31-24} = 0b11011000;
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let hasNewValue = 1;
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let opNewValue = 0;
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@ -17122,7 +17122,7 @@ def M4_mpyri_addr : HInst<
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(outs IntRegs:$Rd32),
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(ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii),
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"$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))",
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tc_05d3a09b, TypeALU64>, Enc_420cf3, ImmRegRel {
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tc_05d3a09b, TypeALU64>, Enc_420cf3, Requires<[UseCompound]>, ImmRegRel {
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let Inst{31-23} = 0b110111111;
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let hasNewValue = 1;
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let opNewValue = 0;
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@ -17139,7 +17139,7 @@ def M4_mpyri_addr_u2 : HInst<
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(outs IntRegs:$Rd32),
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(ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32),
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"$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))",
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tc_1a2fd869, TypeALU64>, Enc_277737 {
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tc_1a2fd869, TypeALU64>, Enc_277737, Requires<[UseCompound]> {
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let Inst{31-23} = 0b110111110;
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let hasNewValue = 1;
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let opNewValue = 0;
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@ -17149,7 +17149,7 @@ def M4_mpyrr_addi : HInst<
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(outs IntRegs:$Rd32),
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(ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32),
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"$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))",
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tc_d773585a, TypeALU64>, Enc_a7b8e8, ImmRegRel {
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tc_d773585a, TypeALU64>, Enc_a7b8e8, Requires<[UseCompound]>, ImmRegRel {
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let Inst{31-23} = 0b110101110;
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let hasNewValue = 1;
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let opNewValue = 0;
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@ -17166,7 +17166,7 @@ def M4_mpyrr_addr : HInst<
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(outs IntRegs:$Ry32),
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(ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32),
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"$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))",
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tc_d773585a, TypeM>, Enc_7f1a05, ImmRegRel {
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tc_d773585a, TypeM>, Enc_7f1a05, Requires<[UseCompound]>, ImmRegRel {
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let Inst{7-5} = 0b000;
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let Inst{13-13} = 0b0;
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let Inst{31-21} = 0b11100011000;
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@ -22001,7 +22001,7 @@ def S4_addaddi : HInst<
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(outs IntRegs:$Rd32),
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(ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii),
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"$Rd32 = add($Rs32,add($Ru32,#$Ii))",
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tc_f675fee8, TypeALU64>, Enc_8b8d61 {
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tc_f675fee8, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
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let Inst{31-23} = 0b110110110;
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let hasNewValue = 1;
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let opNewValue = 0;
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@ -22016,7 +22016,7 @@ def S4_addi_asl_ri : HInst<
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(outs IntRegs:$Rx32),
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(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
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"$Rx32 = add(#$Ii,asl($Rx32in,#$II))",
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tc_f675fee8, TypeALU64>, Enc_c31910 {
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tc_f675fee8, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
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let Inst{2-0} = 0b100;
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let Inst{4-4} = 0b0;
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let Inst{31-24} = 0b11011110;
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@ -22034,7 +22034,7 @@ def S4_addi_lsr_ri : HInst<
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(outs IntRegs:$Rx32),
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(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
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"$Rx32 = add(#$Ii,lsr($Rx32in,#$II))",
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tc_f675fee8, TypeALU64>, Enc_c31910 {
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tc_f675fee8, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
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let Inst{2-0} = 0b100;
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let Inst{4-4} = 0b1;
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let Inst{31-24} = 0b11011110;
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@ -22052,7 +22052,7 @@ def S4_andi_asl_ri : HInst<
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(outs IntRegs:$Rx32),
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(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
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"$Rx32 = and(#$Ii,asl($Rx32in,#$II))",
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tc_f429765c, TypeALU64>, Enc_c31910 {
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tc_f429765c, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
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let Inst{2-0} = 0b000;
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let Inst{4-4} = 0b0;
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let Inst{31-24} = 0b11011110;
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@ -22070,7 +22070,7 @@ def S4_andi_lsr_ri : HInst<
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(outs IntRegs:$Rx32),
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(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
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"$Rx32 = and(#$Ii,lsr($Rx32in,#$II))",
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tc_f429765c, TypeALU64>, Enc_c31910 {
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tc_f429765c, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
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let Inst{2-0} = 0b000;
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let Inst{4-4} = 0b1;
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let Inst{31-24} = 0b11011110;
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@ -22208,7 +22208,7 @@ def S4_or_andix : HInst<
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(outs IntRegs:$Rx32),
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(ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii),
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"$Rx32 = or($Ru32,and($Rx32in,#$Ii))",
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tc_f429765c, TypeALU64>, Enc_b4e6cf {
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tc_f429765c, TypeALU64>, Enc_b4e6cf, Requires<[UseCompound]> {
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let Inst{31-22} = 0b1101101001;
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let hasNewValue = 1;
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let opNewValue = 0;
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@ -22241,7 +22241,7 @@ def S4_ori_asl_ri : HInst<
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(outs IntRegs:$Rx32),
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(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
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"$Rx32 = or(#$Ii,asl($Rx32in,#$II))",
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tc_f429765c, TypeALU64>, Enc_c31910 {
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tc_f429765c, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
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let Inst{2-0} = 0b010;
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let Inst{4-4} = 0b0;
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let Inst{31-24} = 0b11011110;
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@ -22259,7 +22259,7 @@ def S4_ori_lsr_ri : HInst<
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(outs IntRegs:$Rx32),
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(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
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"$Rx32 = or(#$Ii,lsr($Rx32in,#$II))",
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tc_f429765c, TypeALU64>, Enc_c31910 {
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tc_f429765c, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
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let Inst{2-0} = 0b010;
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let Inst{4-4} = 0b1;
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let Inst{31-24} = 0b11011110;
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@ -25106,7 +25106,7 @@ def S4_subaddi : HInst<
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(outs IntRegs:$Rd32),
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(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32),
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"$Rd32 = add($Rs32,sub(#$Ii,$Ru32))",
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tc_f675fee8, TypeALU64>, Enc_8b8d61 {
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tc_f675fee8, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
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let Inst{31-23} = 0b110110111;
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let hasNewValue = 1;
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let opNewValue = 0;
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@ -25121,7 +25121,7 @@ def S4_subi_asl_ri : HInst<
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(outs IntRegs:$Rx32),
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(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
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"$Rx32 = sub(#$Ii,asl($Rx32in,#$II))",
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tc_f675fee8, TypeALU64>, Enc_c31910 {
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tc_f675fee8, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
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let Inst{2-0} = 0b110;
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let Inst{4-4} = 0b0;
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let Inst{31-24} = 0b11011110;
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@ -25139,7 +25139,7 @@ def S4_subi_lsr_ri : HInst<
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(outs IntRegs:$Rx32),
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(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
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"$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))",
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tc_f675fee8, TypeALU64>, Enc_c31910 {
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tc_f675fee8, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
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let Inst{2-0} = 0b110;
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let Inst{4-4} = 0b1;
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let Inst{31-24} = 0b11011110;
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@ -228,7 +228,7 @@ def: Pat<(int_hexagon_A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2),
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def: Pat<(int_hexagon_S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),
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(S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
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def: Pat<(int_hexagon_S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),
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(S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
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(S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;
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def: Pat<(int_hexagon_S2_vzxthw IntRegs:$src1),
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(S2_vzxthw IntRegs:$src1)>, Requires<[HasV5]>;
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def: Pat<(int_hexagon_F2_sfadd IntRegs:$src1, IntRegs:$src2),
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@ -382,7 +382,7 @@ def: Pat<(int_hexagon_M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3
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def: Pat<(int_hexagon_M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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(M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
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def: Pat<(int_hexagon_M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
(M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
|
||||
(M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),
|
||||
(S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mpy_sat_hl_s0 IntRegs:$src1, IntRegs:$src2),
|
||||
|
|
@ -390,7 +390,7 @@ def: Pat<(int_hexagon_M2_mpy_sat_hl_s0 IntRegs:$src1, IntRegs:$src2),
|
|||
def: Pat<(int_hexagon_M2_mpy_sat_hl_s1 IntRegs:$src1, IntRegs:$src2),
|
||||
(M2_mpy_sat_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
(M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
|
||||
(M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
|
||||
(M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mmachs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
|
||||
|
|
@ -558,7 +558,7 @@ def: Pat<(int_hexagon_M2_cnacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src
|
|||
def: Pat<(int_hexagon_M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
(M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3),
|
||||
(S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
|
||||
(S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
(M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mpyud_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
|
|
@ -670,7 +670,7 @@ def: Pat<(int_hexagon_C2_andn PredRegs:$src1, PredRegs:$src2),
|
|||
def: Pat<(int_hexagon_M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2),
|
||||
(M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),
|
||||
(S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
(S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
(M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
|
|
@ -722,7 +722,7 @@ def: Pat<(int_hexagon_M2_cmpyi_s0 IntRegs:$src1, IntRegs:$src2),
|
|||
def: Pat<(int_hexagon_S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
|
||||
(S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),
|
||||
(S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
(S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_C4_nbitsset IntRegs:$src1, IntRegs:$src2),
|
||||
(C4_nbitsset IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
|
|
@ -784,7 +784,7 @@ def: Pat<(int_hexagon_M4_or_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
|||
def: Pat<(int_hexagon_A2_minp DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(A2_minp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3),
|
||||
(S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
(S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2),
|
||||
(M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2),
|
||||
|
|
@ -820,7 +820,7 @@ def: Pat<(int_hexagon_S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)
|
|||
def: Pat<(int_hexagon_C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2),
|
||||
(C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),
|
||||
(S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
(S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_A4_tfrcpp CtrRegs64:$src1),
|
||||
(A4_tfrcpp CtrRegs64:$src1)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred_timm:$src2),
|
||||
|
|
@ -838,7 +838,7 @@ def: Pat<(int_hexagon_S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRe
|
|||
def: Pat<(int_hexagon_A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),
|
||||
(S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
(S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2),
|
||||
(S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2),
|
||||
|
|
@ -958,9 +958,9 @@ def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs
|
|||
def: Pat<(int_hexagon_C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3),
|
||||
(M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
(M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),
|
||||
(S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
(S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3),
|
||||
(M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_A2_tfrcrr CtrRegs:$src1),
|
||||
|
|
@ -1018,7 +1018,7 @@ def: Pat<(int_hexagon_A2_vmaxh DoubleRegs:$src1, DoubleRegs:$src2),
|
|||
def: Pat<(int_hexagon_S2_vsxthw IntRegs:$src1),
|
||||
(S2_vsxthw IntRegs:$src1)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),
|
||||
(S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
(S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3),
|
||||
(S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
|
||||
|
|
@ -1196,7 +1196,7 @@ def: Pat<(int_hexagon_M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntReg
|
|||
def: Pat<(int_hexagon_M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3),
|
||||
(M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
|
||||
(M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
(M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
|
||||
|
|
@ -1260,7 +1260,7 @@ def: Pat<(int_hexagon_A2_tfrih IntRegs:$src1, u16_0ImmPred_timm:$src2),
|
|||
def: Pat<(int_hexagon_A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2),
|
||||
(A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3),
|
||||
(M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
(M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_S2_vtrunehb DoubleRegs:$src1),
|
||||
(S2_vtrunehb DoubleRegs:$src1)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_A2_vabsw DoubleRegs:$src1),
|
||||
|
|
@ -1478,7 +1478,7 @@ def: Pat<(int_hexagon_A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2),
|
|||
def: Pat<(int_hexagon_A2_svaddhs IntRegs:$src1, IntRegs:$src2),
|
||||
(A2_svaddhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),
|
||||
(S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
(S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2),
|
||||
(M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2),
|
||||
|
|
@ -1590,7 +1590,7 @@ def: Pat<(int_hexagon_M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$sr
|
|||
def: Pat<(int_hexagon_M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
(M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3),
|
||||
(S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>;
|
||||
(S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
(M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
|
||||
def: Pat<(int_hexagon_M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
|
|
|
|||
|
|
@ -787,10 +787,18 @@ void HexagonDAGToDAGISel::SelectVAlign(SDNode *N) {
|
|||
MVT::i64, Ops);
|
||||
|
||||
// Shift right by "(Addr & 0x3) * 8" bytes.
|
||||
SDNode *C;
|
||||
SDValue M0 = CurDAG->getTargetConstant(0x18, dl, MVT::i32);
|
||||
SDValue M1 = CurDAG->getTargetConstant(0x03, dl, MVT::i32);
|
||||
SDNode *C = CurDAG->getMachineNode(Hexagon::S4_andi_asl_ri, dl, MVT::i32,
|
||||
M0, N->getOperand(2), M1);
|
||||
if (HST->useCompound()) {
|
||||
C = CurDAG->getMachineNode(Hexagon::S4_andi_asl_ri, dl, MVT::i32,
|
||||
M0, N->getOperand(2), M1);
|
||||
} else {
|
||||
SDNode *T = CurDAG->getMachineNode(Hexagon::S2_asl_i_r, dl, MVT::i32,
|
||||
N->getOperand(2), M1);
|
||||
C = CurDAG->getMachineNode(Hexagon::A2_andir, dl, MVT::i32,
|
||||
SDValue(T, 0), M0);
|
||||
}
|
||||
SDNode *S = CurDAG->getMachineNode(Hexagon::S2_lsr_r_p, dl, MVT::i64,
|
||||
SDValue(R, 0), SDValue(C, 0));
|
||||
SDValue E = CurDAG->getTargetExtractSubreg(Hexagon::isub_lo, dl, ResTy,
|
||||
|
|
|
|||
|
|
@ -1231,7 +1231,7 @@ class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp,
|
|||
: Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)),
|
||||
(MI anyimm:$u8, RegPred:$Rs, imm:$U5)>;
|
||||
|
||||
let AddedComplexity = 200 in {
|
||||
let AddedComplexity = 200, Predicates = [UseCompound] in {
|
||||
def: OpshIRI_pat<S4_addi_asl_ri, Add, Su<Shl>, I32, u5_0ImmPred>;
|
||||
def: OpshIRI_pat<S4_addi_lsr_ri, Add, Su<Srl>, I32, u5_0ImmPred>;
|
||||
def: OpshIRI_pat<S4_subi_asl_ri, Sub, Su<Shl>, I32, u5_0ImmPred>;
|
||||
|
|
@ -1510,7 +1510,7 @@ let AddedComplexity = 110 in { // greater than S2_asl_r_r_and/or/xor.
|
|||
|
||||
// S4_addaddi and S4_subaddi don't have tied operands, so give them
|
||||
// a bit of preference.
|
||||
let AddedComplexity = 30 in {
|
||||
let AddedComplexity = 30, Predicates = [UseCompound] in {
|
||||
def: Pat<(add I32:$Rs, (Su<Add> I32:$Ru, anyimm:$s6)),
|
||||
(S4_addaddi IntRegs:$Rs, IntRegs:$Ru, imm:$s6)>;
|
||||
def: Pat<(add anyimm:$s6, (Su<Add> I32:$Rs, I32:$Ru)),
|
||||
|
|
@ -1523,8 +1523,10 @@ let AddedComplexity = 30 in {
|
|||
(S4_subaddi IntRegs:$Rs, imm:$s6, IntRegs:$Ru)>;
|
||||
}
|
||||
|
||||
let Predicates = [UseCompound] in
|
||||
def: Pat<(or I32:$Ru, (Su<And> I32:$Rx, anyimm:$s10)),
|
||||
(S4_or_andix IntRegs:$Ru, IntRegs:$Rx, imm:$s10)>;
|
||||
|
||||
def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)),
|
||||
(S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>;
|
||||
def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)),
|
||||
|
|
@ -1625,21 +1627,22 @@ def : Pat <(mulhs I64:$Rss, I64:$Rtt),
|
|||
// will put the immediate addend into a register, while these instructions will
|
||||
// use it directly. Such a construct does not appear in the middle of a gep,
|
||||
// where M2_macsip would be preferable.
|
||||
let AddedComplexity = 20 in {
|
||||
let AddedComplexity = 20, Predicates = [UseCompound] in {
|
||||
def: Pat<(add (Su<Mul> I32:$Rs, u6_0ImmPred:$U6), anyimm:$u6),
|
||||
(M4_mpyri_addi imm:$u6, IntRegs:$Rs, imm:$U6)>;
|
||||
def: Pat<(add (Su<Mul> I32:$Rs, I32:$Rt), anyimm:$u6),
|
||||
(M4_mpyrr_addi imm:$u6, IntRegs:$Rs, IntRegs:$Rt)>;
|
||||
}
|
||||
|
||||
// Keep these instructions less preferable to M2_macsip/M2_macsin.
|
||||
def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)),
|
||||
(M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>;
|
||||
def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)),
|
||||
(M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>;
|
||||
def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)),
|
||||
(M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>;
|
||||
|
||||
let Predicates = [UseCompound] in {
|
||||
// Keep these instructions less preferable to M2_macsip/M2_macsin.
|
||||
def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, u6_2ImmPred:$u6_2)),
|
||||
(M4_mpyri_addr_u2 IntRegs:$Ru, imm:$u6_2, IntRegs:$Rs)>;
|
||||
def: Pat<(add I32:$Ru, (Su<Mul> I32:$Rs, anyimm:$u6)),
|
||||
(M4_mpyri_addr IntRegs:$Ru, IntRegs:$Rs, imm:$u6)>;
|
||||
def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)),
|
||||
(M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>;
|
||||
}
|
||||
|
||||
def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx),
|
||||
(F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>;
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo {
|
|||
bool UseHVX64BOps = false;
|
||||
bool UseHVX128BOps = false;
|
||||
|
||||
bool UseCompound = false;
|
||||
bool UseLongCalls = false;
|
||||
bool UseMemops = false;
|
||||
bool UsePackets = false;
|
||||
|
|
@ -158,6 +159,7 @@ public:
|
|||
return getHexagonArchVersion() == Hexagon::ArchEnum::V66;
|
||||
}
|
||||
|
||||
bool useCompound() const { return UseCompound; }
|
||||
bool useLongCalls() const { return UseLongCalls; }
|
||||
bool useMemops() const { return UseMemops; }
|
||||
bool usePackets() const { return UsePackets; }
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: t0
|
||||
; CHECK: r0 = add(r1,add(r0,#23))
|
||||
define i32 @t0(i32 %a0, i32 %a1) #0 {
|
||||
%v0 = add i32 %a1, 23
|
||||
%v1 = add i32 %a0, %v0
|
||||
ret i32 %v1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: t1
|
||||
; CHECK: r[[R:[0-9]+]] = add(r1,r0)
|
||||
; CHECK: r0 = add(r[[R]],#23)
|
||||
define i32 @t1(i32 %a0, i32 %a1) #1 {
|
||||
%v0 = add i32 %a1, 23
|
||||
%v1 = add i32 %a0, %v0
|
||||
ret i32 %v1
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone "target-cpu"="hexagonv62" "target-features"="+compound" }
|
||||
attributes #1 = { nounwind readnone "target-cpu"="hexagonv62" "target-features"="-compound" }
|
||||
Loading…
Reference in New Issue