forked from OSchip/llvm-project
Revert "[InstCombinePHI] Partial simplification of identity operations."
This reverts commit r244887, it caused PR24470. llvm-svn: 245194
This commit is contained in:
David Majnemer
parent
2f1fd1658f
commit
8ed559ad22
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@ -781,106 +781,6 @@ Instruction *InstCombiner::SliceUpIllegalIntegerPHI(PHINode &FirstPhi) {
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return ReplaceInstUsesWith(FirstPhi, Undef);
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}
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// If a PHI node has two edges and the PHI node is used in instructions like
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// add, sub, mul, div, shifts; if one of incoming values is a constant
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// that makes the instruction and identity operation, we can hoist this
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// instruction into one of the basic blocks.
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// Because of such a transformation, the identity operation won't be
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// executed, since it doesn't contribute to the result.
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//
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static Instruction *PartiallySimplifyIdentityOps(PHINode &PN, const Constant &C,
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Value &IncomingVal,
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Instruction &PNUser,
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InstCombiner &IC) {
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if (!PNUser.isBinaryOp())
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return nullptr;
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if (PN.getParent() != PNUser.getParent())
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return nullptr;
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// C IncomingVal
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// \ /
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// \ 0 1 / -- (IncomingValIdx)
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// \ /
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// PN = phi [C , ...] [ IncomingVal, BB ]
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// ...
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// 0 1 -- (OpOperandIdx)
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// PNUser = op PN, x
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const unsigned IncomingValIdx =
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(&IncomingVal == PN.getIncomingValue(0)) ? 0 : 1;
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const unsigned OpOperandIdx = (&PN == PNUser.getOperand(0)) ? 1 : 0;
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// Exit if not an identity operation.
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// For everything except add Add and Mul constant must be on the RHS.
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switch (PNUser.getOpcode()) {
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default:
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return nullptr;
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case Instruction::Add:
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if (!C.isZeroValue())
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return nullptr;
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break;
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case Instruction::Sub:
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case Instruction::Shl:
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case Instruction::LShr:
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case Instruction::AShr:
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if (!C.isZeroValue() || OpOperandIdx == 1)
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return nullptr;
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break;
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case Instruction::Mul:
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if (!C.isOneValue())
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return nullptr;
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break;
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case Instruction::UDiv:
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case Instruction::SDiv:
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if (!C.isOneValue() || OpOperandIdx == 1)
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return nullptr;
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break;
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}
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BasicBlock *BB = PN.getIncomingBlock(IncomingValIdx);
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auto *Terminator = BB->getTerminator();
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if (const auto *Incoming = dyn_cast<Instruction>(&IncomingVal))
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if (!IC.getDominatorTree()->dominates(Incoming, Terminator))
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return nullptr;
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// Operand must be available in newly generated instruction and
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// as an incoming value of the PHI node.
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if (const auto *Operand =
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dyn_cast<Instruction>(PNUser.getOperand(OpOperandIdx)))
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if (!IC.getDominatorTree()->dominates(Operand, Terminator) ||
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!IC.getDominatorTree()->dominates(Operand, &PN))
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return nullptr;
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// Ensure that the non-constant value in the PHI node doesn't come
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// from the same BasicBlock as the PHI node. This prevents errors
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// that could appear with loops (loop backedge could have this
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// problem).
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if (PN.getIncomingBlock(IncomingValIdx) == PN.getParent())
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return nullptr;
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Value *LHS = &IncomingVal, *RHS = PNUser.getOperand(OpOperandIdx);
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if (OpOperandIdx == 0)
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std::swap(LHS, RHS);
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// Add new instruction to one of the edges.
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IRBuilder<> Builder(Terminator);
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auto *NewInst =
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Builder.CreateBinOp(cast<BinaryOperator>(PNUser).getOpcode(), LHS, RHS);
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cast<BinaryOperator>(NewInst)->copyIRFlags(&PNUser);
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// The new incoming values are:
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// - result of the newly emmited instruction
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// - operand of the instruction
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PN.setIncomingValue(IncomingValIdx, NewInst);
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PN.setIncomingValue(IncomingValIdx == 0 ? 1 : 0,
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PNUser.getOperand(OpOperandIdx));
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IC.ReplaceInstUsesWith(PNUser, &PN);
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return &PN;
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}
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// PHINode simplification
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//
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Instruction *InstCombiner::visitPHINode(PHINode &PN) {
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@ -922,21 +822,6 @@ Instruction *InstCombiner::visitPHINode(PHINode &PN) {
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PHIUser->user_back() == &PN) {
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return ReplaceInstUsesWith(PN, UndefValue::get(PN.getType()));
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}
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// If this phi has one use, exactly 2 edges and one is a constant, we
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// may be able to apply the PartiallySimplifyIdentityOps optimization.
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if (PN.getNumIncomingValues() == 2) {
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const Constant *C = dyn_cast<Constant>(PN.getIncomingValue(0));
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Value *Val = PN.getIncomingValue(1);
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if (!C) {
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C = dyn_cast<Constant>(PN.getIncomingValue(1));
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Val = PN.getIncomingValue(0);
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}
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if (C && !isa<Constant>(Val))
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if (auto *I =
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PartiallySimplifyIdentityOps(PN, *C, *Val, *PHIUser, *this))
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return I;
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}
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}
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// We sometimes end up with phi cycles that non-obviously end up being the
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@ -247,9 +247,8 @@ end:
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ret i64 %tmp2
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; CHECK-LABEL: @test12(
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; CHECK-NOT: zext
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; CHECK: %[[X:.*]] = add i64 %{{.*}}, %Val
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; CHECK: end:
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; CHECK-NEXT: phi i64 [ %tmp41, %entry ], [ %[[X]], %two ]
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; CHECK-NEXT: phi i64 [ 0, %entry ], [ %Val, %two ]
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; CHECK-NOT: phi
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; CHECK: ret i64
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}
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@ -631,124 +630,3 @@ done:
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%y = phi i32 [ undef, %entry ]
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ret i32 %y
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}
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; CHECK-LABEL: @test28(
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; CHECK add nsw i32 %x, %dfd
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; CHECK: if.end:
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; CHECK-NEXT: phi i32 [ %{{.*}}, %if.else ], [ %x, %entry ]
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; CHECK-NEXT: ret
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define i32 @test28(i1* nocapture readonly %cond, i32* nocapture readonly %a, i32 %x, i32 %v) {
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entry:
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%0 = load volatile i1, i1* %cond, align 1
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br i1 %0, label %if.else, label %if.end
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if.else:
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%1 = load volatile i32, i32* %a, align 4
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br label %if.end
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if.end:
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%v.addr.0 = phi i32 [ %1, %if.else ], [ 0, %entry ]
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%div = add nsw i32 %x, %v.addr.0
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ret i32 %div
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}
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; CHECK-LABEL: @test29(
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; CHECK: ashr i32 %x, %1
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; CHECK: if.end:
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; CHECK-NEXT: phi i32 [ %{{.*}}, %if.else ], [ %x, %entry ]
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; CHECK-NEXT: ret
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define i32 @test29(i1* nocapture readonly %cond, i32* nocapture readonly %a, i32 %x, i32 %v) {
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entry:
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%0 = load volatile i1, i1* %cond, align 1
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br i1 %0, label %if.else, label %if.end
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if.else:
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%1 = load volatile i32, i32* %a, align 4
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br label %if.end
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if.end:
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%v.addr.0 = phi i32 [ %1, %if.else ], [ 0, %entry ]
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%div = ashr i32 %x, %v.addr.0
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ret i32 %div
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}
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; CHECK-LABEL: @test30(
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; CHECK: sdiv i32 %x, %1
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; CHECK: if.end:
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; CHECK-NEXT: phi i32 [ %{{.*}}, %if.else ], [ %x, %entry ]
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; CHECK-NEXT: ret
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define i32 @test30(i1* nocapture readonly %cond, i32* nocapture readonly %a, i32 %x, i32 %v) {
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entry:
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%0 = load volatile i1, i1* %cond, align 1
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br i1 %0, label %if.else, label %if.end
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if.else:
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%1 = load volatile i32, i32* %a, align 4
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br label %if.end
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if.end:
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%v.addr.0 = phi i32 [ %1, %if.else ], [ 1, %entry ]
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%div = sdiv i32 %x, %v.addr.0
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ret i32 %div
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}
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; CHECK-LABEL: @test31(
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; CHECK: mul i32
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; CHECK: if.end:
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; CHECK-NEXT: phi i32 [ %{{.*}}, %if.else ], [ %x, %entry ]
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; CHECK-NEXT: ret
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define i32 @test31(i1* nocapture readonly %cond, i32* nocapture readonly %a, i32 %x, i32 %v) {
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entry:
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%0 = load volatile i1, i1* %cond, align 1
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br i1 %0, label %if.else, label %if.end
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if.else:
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%1 = load volatile i32, i32* %a, align 4
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br label %if.end
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if.end:
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%v.addr.0 = phi i32 [ %1, %if.else ], [ 1, %entry ]
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%div = mul i32 %x, %v.addr.0
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ret i32 %div
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}
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; CHECK-LABEL: @test32(
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; CHECK: sdiv i32 %x, %1
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; CHECK: if.end:
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; CHECK-NEXT: phi i32 [ %x, %entry ], [ %{{.*}}, %if.else ]
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; CHECK-NEXT: ret
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define i32 @test32(i1* nocapture readonly %cond, i32* nocapture readonly %a, i32 %x, i32 %v) {
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entry:
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%0 = load volatile i1, i1* %cond, align 1
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br i1 %0, label %if.else, label %if.end
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if.else:
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%1 = load volatile i32, i32* %a, align 4
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br label %if.end
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if.end:
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%v.addr.0 = phi i32 [ 1, %entry ], [ %1, %if.else ]
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%div = sdiv i32 %x, %v.addr.0
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ret i32 %div
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}
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; Constant (0) is on the LHS of shift - should not aplpy the transformation
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; CHECK-LABEL: @test33(
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; CHECK: if.end:
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; CHECK-NEXT: %v.addr.0 = phi i32 [ 0, %entry ], [ %1, %if.else ]
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; CHECK-NEXT: shl
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; CHECK-NEXT: ret
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define i32 @test33(i1* nocapture readonly %cond, i32* nocapture readonly %a, i32 %x, i32 %v) {
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entry:
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%0 = load volatile i1, i1* %cond, align 1
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br i1 %0, label %if.else, label %if.end
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if.else:
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%1 = load volatile i32, i32* %a, align 4
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br label %if.end
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if.end:
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%v.addr.0 = phi i32 [ 0, %entry ], [ %1, %if.else ]
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%div = shl i32 %v.addr.0, %x
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ret i32 %div
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}
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