forked from OSchip/llvm-project
AMDGPU: Erase redundant redefs of m0 in SIFoldOperands
Only handle simple inter-block redefs of m0 to the same value. This avoids interference from redefs of m0 in SILoadStoreOptimzer. I was initially teaching that pass to ignore redefs of m0, but having them not exist beforehand is much simpler. This is in preparation for deleting the current special m0 handling in SIFixSGPRCopies to allow the register coalescer to handle the difficult cases. llvm-svn: 375449
This commit is contained in:
Matt Arsenault
parent
dd6cf159ba
commit
8ebbf25cb1
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@ -1349,6 +1349,8 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
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for (MachineBasicBlock *MBB : depth_first(&MF)) {
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MachineBasicBlock::iterator I, Next;
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MachineOperand *CurrentKnownM0Val = nullptr;
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for (I = MBB->begin(); I != MBB->end(); I = Next) {
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Next = std::next(I);
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MachineInstr &MI = *I;
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@ -1361,6 +1363,25 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
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if (IsIEEEMode || (!HasNSZ && !MI.getFlag(MachineInstr::FmNsz)) ||
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!tryFoldOMod(MI))
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tryFoldClamp(MI);
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// Saw an unknown clobber of m0, so we no longer know what it is.
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if (CurrentKnownM0Val && MI.modifiesRegister(AMDGPU::M0, TRI))
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CurrentKnownM0Val = nullptr;
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continue;
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}
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// Specially track simple redefs of m0 to the same value in a block, so we
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// can erase the later ones.
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if (MI.getOperand(0).getReg() == AMDGPU::M0) {
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MachineOperand &NewM0Val = MI.getOperand(1);
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if (CurrentKnownM0Val && CurrentKnownM0Val->isIdenticalTo(NewM0Val)) {
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MI.eraseFromParent();
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continue;
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}
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// We aren't tracking other physical registers
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CurrentKnownM0Val = (NewM0Val.isReg() && NewM0Val.getReg().isPhysical()) ?
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nullptr : &NewM0Val;
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continue;
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}
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@ -0,0 +1,366 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass=si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
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--- |
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define amdgpu_kernel void @redef_m0_same_copy() { ret void }
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define amdgpu_kernel void @multi_redef_m0_same_copy() { ret void }
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define amdgpu_kernel void @redef_m0_different_copy() { ret void }
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define amdgpu_kernel void @redef_m0_mixed_copy0() { ret void }
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define amdgpu_kernel void @redef_m0_mixed_copy1() { ret void }
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define amdgpu_kernel void @redef_m0_same_mov_imm() { ret void }
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define amdgpu_kernel void @redef_m0_different_inst0() { ret void }
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define amdgpu_kernel void @redef_m0_different_inst1() { ret void }
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define amdgpu_kernel void @redef_m0_mixed_read_m0() { ret void }
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define amdgpu_kernel void @redef_m0_same_copy_call() { ret void }
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define amdgpu_kernel void @redef_m0_same_copy_multi_block() { ret void }
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define amdgpu_kernel void @redef_m0_copy_self() { ret void }
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define amdgpu_kernel void @redef_m0_copy_physreg() { ret void }
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declare void @func()
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...
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---
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name: redef_m0_same_copy
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: redef_m0_same_copy
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = COPY %1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: multi_redef_m0_same_copy
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: multi_redef_m0_same_copy
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = COPY %1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %1
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_different_copy
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0, $sgpr1
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; GCN-LABEL: name: redef_m0_different_copy
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr1
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: $m0 = COPY [[COPY2]]
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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%2:sgpr_32 = COPY $sgpr1
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %2
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%4:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_mixed_copy0
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0, $sgpr1
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; GCN-LABEL: name: redef_m0_mixed_copy0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr1
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: $m0 = COPY [[COPY2]]
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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%2:sgpr_32 = COPY $sgpr1
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %1
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$m0 = COPY %2
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%4:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_mixed_copy1
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0, $sgpr1
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; GCN-LABEL: name: redef_m0_mixed_copy1
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr1
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: $m0 = COPY [[COPY2]]
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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%2:sgpr_32 = COPY $sgpr1
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %2
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$m0 = COPY %1
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%4:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_same_mov_imm
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: redef_m0_same_mov_imm
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = S_MOV_B32 -1
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = S_MOV_B32 -1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = S_MOV_B32 -1
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_different_inst0
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: redef_m0_different_inst0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: $m0 = IMPLICIT_DEF
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = COPY %1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = IMPLICIT_DEF
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_different_inst1
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: redef_m0_different_inst1
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: S_NOP 0, implicit-def $m0
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = COPY %1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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S_NOP 0, implicit-def $m0
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_mixed_read_m0
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0, $sgpr1
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; GCN-LABEL: name: redef_m0_mixed_read_m0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr1
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: $m0 = COPY [[COPY2]]
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: [[DS_READ_B32_2:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 128, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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%2:sgpr_32 = COPY $sgpr1
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %2
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%4:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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$m0 = COPY %2
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%5:vgpr_32 = DS_READ_B32 %0, 128, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_same_copy_call
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GCN-LABEL: name: redef_m0_same_copy_call
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: dead $sgpr30_sgpr31 = SI_CALL undef $sgpr6_sgpr7, @func, csr_amdgpu_highregs
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr0
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$m0 = COPY %1
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%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
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dead $sgpr30_sgpr31 = SI_CALL undef $sgpr6_sgpr7, @func, csr_amdgpu_highregs
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$m0 = COPY %1
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%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
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...
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---
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name: redef_m0_same_copy_multi_block
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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; GCN-LABEL: name: redef_m0_same_copy_multi_block
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
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; GCN: bb.1:
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; GCN: $m0 = COPY [[COPY1]]
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; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
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||||
bb.0:
|
||||
liveins: $vgpr0, $sgpr0
|
||||
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:sgpr_32 = COPY $sgpr0
|
||||
$m0 = COPY %1
|
||||
%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
|
||||
|
||||
bb.1:
|
||||
$m0 = COPY %1
|
||||
%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: redef_m0_copy_self
|
||||
tracksRegLiveness: true
|
||||
machineFunctionInfo:
|
||||
isEntryFunction: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $sgpr0
|
||||
|
||||
; GCN-LABEL: name: redef_m0_copy_self
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
|
||||
; GCN: $m0 = COPY [[COPY1]]
|
||||
; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
|
||||
; GCN: $m0 = COPY $m0
|
||||
; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:sgpr_32 = COPY $sgpr0
|
||||
$m0 = COPY %1
|
||||
%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
|
||||
$m0 = COPY $m0
|
||||
%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: redef_m0_copy_physreg
|
||||
tracksRegLiveness: true
|
||||
machineFunctionInfo:
|
||||
isEntryFunction: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $sgpr0
|
||||
|
||||
; GCN-LABEL: name: redef_m0_copy_physreg
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
|
||||
; GCN: $m0 = COPY $sgpr0
|
||||
; GCN: [[DS_READ_B32_:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 0, 0, implicit $m0, implicit $exec :: (load 4)
|
||||
; GCN: $sgpr0 = S_MOV_B32 0
|
||||
; GCN: $m0 = COPY $sgpr0
|
||||
; GCN: [[DS_READ_B32_1:%[0-9]+]]:vgpr_32 = DS_READ_B32 [[COPY]], 64, 0, implicit $m0, implicit $exec :: (load 4)
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:sgpr_32 = COPY $sgpr0
|
||||
$m0 = COPY $sgpr0
|
||||
%2:vgpr_32 = DS_READ_B32 %0, 0, 0, implicit $m0, implicit $exec :: (load 4)
|
||||
$sgpr0 = S_MOV_B32 0
|
||||
$m0 = COPY $sgpr0
|
||||
%3:vgpr_32 = DS_READ_B32 %0, 64, 0, implicit $m0, implicit $exec :: (load 4)
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue