forked from OSchip/llvm-project
Revert "[AMDGPU] SIFixSGPRCopies refactoring"
Breaks ASan tests.
This reverts commit 3f8ae7efa8.
This commit is contained in:
Evgenii Stepanov
parent
23ace05e0a
commit
8ea1cf3111
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@ -120,10 +120,6 @@ public:
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class SIFixSGPRCopies : public MachineFunctionPass {
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MachineDominatorTree *MDT;
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SmallVector<MachineInstr*, 4> SCCCopies;
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SmallVector<MachineInstr*, 4> RegSequences;
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SmallVector<MachineInstr*, 4> PHINodes;
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SmallVector<MachineInstr*, 4> S2VCopies;
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unsigned NextVGPRToSGPRCopyID;
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DenseMap<unsigned, V2SCopyInfo> V2SCopies;
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DenseMap<MachineInstr *, SetVector<unsigned>> SiblingPenalty;
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@ -138,11 +134,8 @@ public:
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SIFixSGPRCopies() : MachineFunctionPass(ID), NextVGPRToSGPRCopyID(0) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void fixSCCCopies(bool IsWave32);
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void prepareRegSequenceAndPHIs(MachineFunction &MF);
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unsigned getNextVGPRToSGPRCopyId() { return ++NextVGPRToSGPRCopyID; }
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bool needToBeConvertedToVALU(V2SCopyInfo *I);
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void analyzeVGPRToSGPRCopy(MachineInstr *MI);
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void analyzeVGPRToSGPRCopy(V2SCopyInfo& Info);
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void lowerVGPR2SGPRCopies(MachineFunction &MF);
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// Handles copies which source register is:
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// 1. Physical register
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@ -178,6 +171,19 @@ FunctionPass *llvm::createSIFixSGPRCopiesPass() {
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return new SIFixSGPRCopies();
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}
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static bool hasVectorOperands(const MachineInstr &MI,
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const SIRegisterInfo *TRI) {
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const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg() || !MO.getReg().isVirtual())
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continue;
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if (TRI->hasVectorRegisters(MRI.getRegClass(MO.getReg())))
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return true;
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}
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return false;
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}
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static std::pair<const TargetRegisterClass *, const TargetRegisterClass *>
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getCopyRegClasses(const MachineInstr &Copy,
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const SIRegisterInfo &TRI,
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@ -610,6 +616,14 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
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TII = ST.getInstrInfo();
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MDT = &getAnalysis<MachineDominatorTree>();
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// We have to lower VGPR to SGPR copies before the main loop
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// because the REG_SEQUENCE and PHI lowering in main loop
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// convert the def-use chains to VALU and close the opportunities
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// for keeping them scalar.
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// TODO: REG_SEQENCE and PHIs are semantically copies. The next patch
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// addresses their lowering and unify the processing in one main loop.
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lowerVGPR2SGPRCopies(MF);
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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BI != BE; ++BI) {
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MachineBasicBlock *MBB = &*BI;
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@ -625,66 +639,100 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
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case AMDGPU::STRICT_WQM:
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case AMDGPU::SOFT_WQM:
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case AMDGPU::STRICT_WWM: {
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Register SrcReg = MI.getOperand(1).getReg();
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Register DstReg = MI.getOperand(0).getReg();
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const TargetRegisterClass *SrcRC, *DstRC;
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std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, *MRI);
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if (MI.isCopy() && (SrcReg == AMDGPU::SCC || DstReg == AMDGPU::SCC))
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SCCCopies.push_back(&MI);
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if (isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) {
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// Since VGPR to SGPR copies affect VGPR to SGPR copy
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// score and, hence the lowering decision, let's try to get rid of
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// them as early as possible
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if (tryChangeVGPRtoSGPRinCopy(MI, TRI, TII))
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if (MI.isCopy()) {
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Register SrcReg = MI.getOperand(1).getReg();
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if (SrcReg == AMDGPU::SCC) {
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Register SCCCopy = MRI->createVirtualRegister(
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TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID));
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I = BuildMI(*MI.getParent(),
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std::next(MachineBasicBlock::iterator(MI)),
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MI.getDebugLoc(),
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TII->get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
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: AMDGPU::S_CSELECT_B64),
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SCCCopy)
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.addImm(-1)
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.addImm(0);
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I = BuildMI(*MI.getParent(), std::next(I), I->getDebugLoc(),
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TII->get(AMDGPU::COPY), DstReg)
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.addReg(SCCCopy);
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MI.eraseFromParent();
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continue;
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} else if (DstReg == AMDGPU::SCC) {
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unsigned Opcode =
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ST.isWave64() ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32;
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Register Exec = ST.isWave64() ? AMDGPU::EXEC : AMDGPU::EXEC_LO;
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Register Tmp = MRI->createVirtualRegister(TRI->getBoolRC());
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I = BuildMI(*MI.getParent(),
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std::next(MachineBasicBlock::iterator(MI)),
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MI.getDebugLoc(), TII->get(Opcode))
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.addReg(Tmp, getDefRegState(true))
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.addReg(SrcReg)
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.addReg(Exec);
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MI.eraseFromParent();
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continue;
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// Collect those not changed to try them after VGPR to SGPR copies
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// lowering as there will be more opportunities.
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S2VCopies.push_back(&MI);
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}
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if (!isVGPRToSGPRCopy(SrcRC, DstRC, *TRI))
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continue;
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if (lowerSpecialCase(MI))
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continue;
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analyzeVGPRToSGPRCopy(&MI);
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break;
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}
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case AMDGPU::INSERT_SUBREG:
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case AMDGPU::PHI:
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case AMDGPU::REG_SEQUENCE: {
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if (TRI->isSGPRClass(TII->getOpRegClass(MI, 0))) {
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for (MachineOperand &MO : MI.operands()) {
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if (!MO.isReg() || !MO.getReg().isVirtual())
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continue;
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const TargetRegisterClass *SrcRC = MRI->getRegClass(MO.getReg());
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if (TRI->hasVectorRegisters(SrcRC)) {
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const TargetRegisterClass *DestRC =
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TRI->getEquivalentSGPRClass(SrcRC);
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Register NewDst = MRI->createVirtualRegister(DestRC);
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MachineBasicBlock *BlockToInsertCopy =
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MI.isPHI() ? MI.getOperand(MI.getOperandNo(&MO) + 1).getMBB()
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: MBB;
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MachineBasicBlock::iterator PointToInsertCopy =
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MI.isPHI() ? BlockToInsertCopy->getFirstInstrTerminator() : I;
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MachineInstr *NewCopy =
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BuildMI(*BlockToInsertCopy, PointToInsertCopy,
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PointToInsertCopy->getDebugLoc(),
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TII->get(AMDGPU::COPY), NewDst)
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.addReg(MO.getReg());
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MO.setReg(NewDst);
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analyzeVGPRToSGPRCopy(NewCopy);
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}
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}
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}
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if (MI.isPHI())
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PHINodes.push_back(&MI);
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else if (MI.isRegSequence())
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RegSequences.push_back(&MI);
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if (!DstReg.isVirtual()) {
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// If the destination register is a physical register there isn't
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// really much we can do to fix this.
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// Some special instructions use M0 as an input. Some even only use
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// the first lane. Insert a readfirstlane and hope for the best.
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if (DstReg == AMDGPU::M0 && TRI->hasVectorRegisters(SrcRC)) {
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Register TmpReg
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= MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
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BuildMI(*MBB, MI, MI.getDebugLoc(),
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TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg)
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.add(MI.getOperand(1));
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MI.getOperand(1).setReg(TmpReg);
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}
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continue;
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}
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if (isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) {
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tryChangeVGPRtoSGPRinCopy(MI, TRI, TII);
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}
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break;
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}
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case AMDGPU::PHI: {
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processPHINode(MI);
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break;
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}
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case AMDGPU::REG_SEQUENCE: {
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if (TRI->hasVectorRegisters(TII->getOpRegClass(MI, 0)) ||
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!hasVectorOperands(MI, TRI)) {
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foldVGPRCopyIntoRegSequence(MI, TRI, TII, *MRI);
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continue;
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}
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break;
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}
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case AMDGPU::INSERT_SUBREG: {
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const TargetRegisterClass *DstRC, *Src0RC, *Src1RC;
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DstRC = MRI->getRegClass(MI.getOperand(0).getReg());
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Src0RC = MRI->getRegClass(MI.getOperand(1).getReg());
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Src1RC = MRI->getRegClass(MI.getOperand(2).getReg());
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if (TRI->isSGPRClass(DstRC) &&
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(TRI->hasVectorRegisters(Src0RC) ||
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TRI->hasVectorRegisters(Src1RC))) {
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LLVM_DEBUG(dbgs() << " Fixing INSERT_SUBREG: " << MI);
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MachineBasicBlock *NewBB = TII->moveToVALU(MI, MDT);
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if (NewBB && NewBB != MBB) {
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MBB = NewBB;
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E = MBB->end();
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BI = MachineFunction::iterator(MBB);
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BE = MF.end();
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}
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assert((!NewBB || NewBB == I->getParent()) &&
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"moveToVALU did not return the right basic block");
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}
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break;
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}
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case AMDGPU::V_WRITELANE_B32: {
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@ -752,41 +800,11 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
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}
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}
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lowerVGPR2SGPRCopies(MF);
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// Postprocessing
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fixSCCCopies(ST.isWave32());
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for (auto MI : S2VCopies) {
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// Check if it is still valid
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if (MI->getParent() && MI->isCopy()) {
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const TargetRegisterClass *SrcRC, *DstRC;
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std::tie(SrcRC, DstRC) = getCopyRegClasses(*MI, *TRI, *MRI);
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if (isSGPRToVGPRCopy(SrcRC, DstRC, *TRI))
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tryChangeVGPRtoSGPRinCopy(*MI, TRI, TII);
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}
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}
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for (auto MI : RegSequences) {
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// Check if it is still valid
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if (MI->getParent() && MI->isRegSequence())
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foldVGPRCopyIntoRegSequence(*MI, TRI, TII, *MRI);
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}
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for (auto MI : PHINodes) {
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processPHINode(*MI);
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}
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if (MF.getTarget().getOptLevel() > CodeGenOpt::None && EnableM0Merge)
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hoistAndMergeSGPRInits(AMDGPU::M0, *MRI, TRI, *MDT, TII);
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SiblingPenalty.clear();
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V2SCopies.clear();
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SCCCopies.clear();
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RegSequences.clear();
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PHINodes.clear();
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S2VCopies.clear();
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return true;
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}
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@ -843,29 +861,7 @@ void SIFixSGPRCopies::processPHINode(MachineInstr &MI) {
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}
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bool SIFixSGPRCopies::lowerSpecialCase(MachineInstr &MI) {
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Register DstReg = MI.getOperand(0).getReg();
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Register SrcReg = MI.getOperand(1).getReg();
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if (!DstReg.isVirtual()) {
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// If the destination register is a physical register there isn't
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// really much we can do to fix this.
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// Some special instructions use M0 as an input. Some even only use
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// the first lane. Insert a readfirstlane and hope for the best.
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if (DstReg == AMDGPU::M0 &&
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TRI->hasVectorRegisters(MRI->getRegClass(SrcReg))) {
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Register TmpReg =
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MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
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BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
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TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg)
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.add(MI.getOperand(1));
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MI.getOperand(1).setReg(TmpReg);
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}
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return true;
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}
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if (!SrcReg.isVirtual() || TRI->isAGPR(*MRI, SrcReg)) {
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TII->moveToVALU(MI, MDT);
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return true;
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@ -884,13 +880,9 @@ bool SIFixSGPRCopies::lowerSpecialCase(MachineInstr &MI) {
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return false;
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}
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void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
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Register DstReg = MI->getOperand(0).getReg();
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const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
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V2SCopyInfo Info(getNextVGPRToSGPRCopyId(), MI,
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TRI->getRegSizeInBits(*DstRC));
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void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(V2SCopyInfo& Info) {
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SmallVector<MachineInstr *, 8> AnalysisWorklist;
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// Needed because the SSA is not a tree but a graph and may have
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// forks and joins. We should not then go same way twice.
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@ -938,52 +930,143 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
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AnalysisWorklist.push_back(U);
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}
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}
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V2SCopies[Info.ID] = Info;
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}
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// The main function that computes the VGPR to SGPR copy score
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// and determines copy further lowering way: v_readfirstlane_b32 or moveToVALU
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bool SIFixSGPRCopies::needToBeConvertedToVALU(V2SCopyInfo *Info) {
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if (Info->SChain.empty()) {
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Info->Score = 0;
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return true;
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}
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Info->Siblings = SiblingPenalty[*std::max_element(
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Info->SChain.begin(), Info->SChain.end(),
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[&](MachineInstr *A, MachineInstr *B) -> bool {
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return SiblingPenalty[A].size() < SiblingPenalty[B].size();
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})];
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Info->Siblings.remove_if([&](unsigned ID) { return ID == Info->ID; });
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// The loop below computes the number of another VGPR to SGPR V2SCopies
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// which contribute to the current copy SALU chain. We assume that all the
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// V2SCopies with the same source virtual register will be squashed to one
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// by regalloc. Also we take care of the V2SCopies of the differnt subregs
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// of the same register.
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SmallSet<std::pair<Register, unsigned>, 4> SrcRegs;
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for (auto J : Info->Siblings) {
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auto InfoIt = V2SCopies.find(J);
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if (InfoIt != V2SCopies.end()) {
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MachineInstr *SiblingCopy = InfoIt->getSecond().Copy;
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if (SiblingCopy->isImplicitDef())
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// the COPY has already been MoveToVALUed
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continue;
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SrcRegs.insert(std::make_pair(SiblingCopy->getOperand(1).getReg(),
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SiblingCopy->getOperand(1).getSubReg()));
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}
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}
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Info->SiblingPenalty = SrcRegs.size();
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unsigned Penalty =
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Info->NumSVCopies + Info->SiblingPenalty + Info->NumReadfirstlanes;
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unsigned Profit = Info->SChain.size();
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Info->Score = Penalty > Profit ? 0 : Profit - Penalty;
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Info->NeedToBeConvertedToVALU = Info->Score < 3;
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return Info->NeedToBeConvertedToVALU;
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}
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void SIFixSGPRCopies::lowerVGPR2SGPRCopies(MachineFunction &MF) {
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// The main function that computes the VGPR to SGPR copy score
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// and determines copy further lowering way: v_readfirstlane_b32 or moveToVALU
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auto needToBeConvertedToVALU = [&](V2SCopyInfo *I) -> bool {
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if (I->SChain.empty()) {
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I->Score = 0;
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return true;
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}
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I->Siblings = SiblingPenalty[*std::max_element(
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I->SChain.begin(), I->SChain.end(),
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[&](MachineInstr *A, MachineInstr *B) -> bool {
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return SiblingPenalty[A].size() < SiblingPenalty[B].size();
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})];
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I->Siblings.remove_if([&](unsigned ID) { return ID == I->ID; });
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// The loop below computes the number of another VGPR to SGPR V2SCopies
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// which contribute to the current copy SALU chain. We assume that all the
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// V2SCopies with the same source virtual register will be squashed to one
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// by regalloc. Also we take care of the V2SCopies of the differnt subregs
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// of the same register.
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SmallSet<std::pair<Register, unsigned>, 4> SrcRegs;
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for (auto J : I->Siblings) {
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auto InfoIt = V2SCopies.find(J);
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if (InfoIt != V2SCopies.end()) {
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MachineInstr *SiblingCopy = InfoIt->getSecond().Copy;
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if (SiblingCopy->isImplicitDef())
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// the COPY has already been MoveToVALUed
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continue;
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SrcRegs.insert(std::make_pair(SiblingCopy->getOperand(1).getReg(),
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SiblingCopy->getOperand(1).getSubReg()));
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}
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}
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I->SiblingPenalty = SrcRegs.size();
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unsigned Penalty =
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I->NumSVCopies + I->SiblingPenalty + I->NumReadfirstlanes;
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unsigned Profit = I->SChain.size();
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I->Score = Penalty > Profit ? 0 : Profit - Penalty;
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I->NeedToBeConvertedToVALU = I->Score < 3;
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return I->NeedToBeConvertedToVALU;
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};
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auto needProcessing = [](MachineInstr &MI) -> bool {
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switch (MI.getOpcode()) {
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case AMDGPU::COPY:
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case AMDGPU::WQM:
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case AMDGPU::STRICT_WQM:
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case AMDGPU::SOFT_WQM:
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case AMDGPU::STRICT_WWM:
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case AMDGPU::REG_SEQUENCE:
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case AMDGPU::PHI:
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return true;
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default:
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return false;
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}
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};
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SmallSet<MachineInstr *, 4> OutOfOrderProcessedCopies;
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
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++BI) {
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MachineBasicBlock *MBB = &*BI;
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
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++I) {
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MachineInstr *MI = &*I;
|
||||
if (!needProcessing(*MI))
|
||||
continue;
|
||||
|
||||
if (MI->isRegSequence() || MI->isPHI()) {
|
||||
MachineBasicBlock::iterator J = I;
|
||||
if (TRI->isSGPRClass(TII->getOpRegClass(*MI, 0))) {
|
||||
for (MachineOperand &MO : MI->operands()) {
|
||||
if (!MO.isReg() || !MO.getReg().isVirtual())
|
||||
continue;
|
||||
const TargetRegisterClass *SrcRC = MRI->getRegClass(MO.getReg());
|
||||
if (TRI->hasVectorRegisters(SrcRC)) {
|
||||
const TargetRegisterClass *DestRC =
|
||||
TRI->getEquivalentSGPRClass(SrcRC);
|
||||
Register NewDst = MRI->createVirtualRegister(DestRC);
|
||||
MachineBasicBlock *BlockToInsertCopy = MBB;
|
||||
MachineBasicBlock::iterator PointToInsertCopy = I;
|
||||
if (MI->isPHI()) {
|
||||
BlockToInsertCopy =
|
||||
MI->getOperand(MI->getOperandNo(&MO) + 1).getMBB();
|
||||
PointToInsertCopy =
|
||||
BlockToInsertCopy->getFirstInstrTerminator();
|
||||
}
|
||||
MachineBasicBlock::iterator NewI =
|
||||
BuildMI(*BlockToInsertCopy, PointToInsertCopy,
|
||||
PointToInsertCopy->getDebugLoc(),
|
||||
TII->get(AMDGPU::COPY), NewDst)
|
||||
.addReg(MO.getReg());
|
||||
MO.setReg(NewDst);
|
||||
if (!MI->isPHI()) {
|
||||
I = NewI;
|
||||
MI = &*I;
|
||||
} else {
|
||||
// We insert the copy into the basic block that may have been
|
||||
// already processed. Pass it to the analysis explicitly.
|
||||
V2SCopyInfo In(getNextVGPRToSGPRCopyId(), MI,
|
||||
TRI->getRegSizeInBits(*DestRC));
|
||||
analyzeVGPRToSGPRCopy(In);
|
||||
V2SCopies[In.ID] = In;
|
||||
OutOfOrderProcessedCopies.insert(MI);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (J == I)
|
||||
continue;
|
||||
}
|
||||
|
||||
const TargetRegisterClass *SrcRC, *DstRC;
|
||||
std::tie(SrcRC, DstRC) = getCopyRegClasses(*MI, *TRI, *MRI);
|
||||
|
||||
if (!isVGPRToSGPRCopy(SrcRC, DstRC, *TRI))
|
||||
continue;
|
||||
|
||||
if (lowerSpecialCase(*MI))
|
||||
continue;
|
||||
|
||||
if (OutOfOrderProcessedCopies.contains(MI))
|
||||
continue;
|
||||
|
||||
V2SCopyInfo In(getNextVGPRToSGPRCopyId(), MI,
|
||||
TRI->getRegSizeInBits(*DstRC));
|
||||
|
||||
analyzeVGPRToSGPRCopy(In);
|
||||
|
||||
V2SCopies[In.ID] = In;
|
||||
}
|
||||
}
|
||||
|
||||
SmallVector<unsigned, 8> LoweringWorklist;
|
||||
for (auto &C : V2SCopies) {
|
||||
if (needToBeConvertedToVALU(&C.second))
|
||||
|
|
@ -1059,46 +1142,3 @@ void SIFixSGPRCopies::lowerVGPR2SGPRCopies(MachineFunction &MF) {
|
|||
MI->eraseFromParent();
|
||||
}
|
||||
}
|
||||
|
||||
void SIFixSGPRCopies::fixSCCCopies(bool IsWave32) {
|
||||
for (auto MI : SCCCopies) {
|
||||
// May be lowered out
|
||||
if (!MI->getParent())
|
||||
continue;
|
||||
// May already have been lowered.
|
||||
if (!MI->isCopy())
|
||||
continue;
|
||||
Register SrcReg = MI->getOperand(1).getReg();
|
||||
Register DstReg = MI->getOperand(0).getReg();
|
||||
if (SrcReg == AMDGPU::SCC) {
|
||||
Register SCCCopy = MRI->createVirtualRegister(
|
||||
TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID));
|
||||
MachineBasicBlock::iterator I =
|
||||
BuildMI(*MI->getParent(),
|
||||
std::next(MachineBasicBlock::iterator(MI)),
|
||||
MI->getDebugLoc(),
|
||||
TII->get(IsWave32 ? AMDGPU::S_CSELECT_B32
|
||||
: AMDGPU::S_CSELECT_B64),
|
||||
SCCCopy)
|
||||
.addImm(-1)
|
||||
.addImm(0);
|
||||
BuildMI(*MI->getParent(), std::next(I), I->getDebugLoc(),
|
||||
TII->get(AMDGPU::COPY), DstReg)
|
||||
.addReg(SCCCopy);
|
||||
MI->eraseFromParent();
|
||||
continue;
|
||||
}
|
||||
|
||||
if (DstReg == AMDGPU::SCC) {
|
||||
unsigned Opcode = IsWave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
|
||||
Register Exec = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
|
||||
Register Tmp = MRI->createVirtualRegister(TRI->getBoolRC());
|
||||
BuildMI(*MI->getParent(), std::next(MachineBasicBlock::iterator(MI)),
|
||||
MI->getDebugLoc(), TII->get(Opcode))
|
||||
.addReg(Tmp, getDefRegState(true))
|
||||
.addReg(SrcReg)
|
||||
.addReg(Exec);
|
||||
MI->eraseFromParent();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -41,9 +41,9 @@ body: |
|
|||
; W64-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W64-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W64-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]], implicit $exec
|
||||
; W64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; W64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; W64-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY2]], implicit $exec
|
||||
; W64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, killed [[COPY7]], %subreg.sub1, [[COPY3]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1, killed [[COPY7]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W64-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; W64-NEXT: {{ $}}
|
||||
; W64-NEXT: .1:
|
||||
|
|
@ -88,9 +88,9 @@ body: |
|
|||
; W32-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W32-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W32-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]], implicit $exec
|
||||
; W32-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; W32-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; W32-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY2]], implicit $exec
|
||||
; W32-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, killed [[COPY7]], %subreg.sub1, [[COPY3]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W32-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1, killed [[COPY7]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W32-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
|
||||
; W32-NEXT: {{ $}}
|
||||
; W32-NEXT: .1:
|
||||
|
|
@ -160,10 +160,10 @@ body: |
|
|||
; W64-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W64-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W64-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W64-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; W64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; W64-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY2]], implicit $exec
|
||||
; W64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY5]], %subreg.sub0, killed [[COPY6]], %subreg.sub1, killed [[COPY7]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W64-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]], implicit $exec
|
||||
; W64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; W64-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; W64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, killed [[COPY7]], %subreg.sub1, killed [[COPY8]], %subreg.sub2, [[COPY2]], %subreg.sub3
|
||||
; W64-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; W64-NEXT: {{ $}}
|
||||
; W64-NEXT: .1:
|
||||
|
|
@ -207,10 +207,10 @@ body: |
|
|||
; W32-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W32-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W32-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W32-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; W32-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; W32-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY2]], implicit $exec
|
||||
; W32-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY5]], %subreg.sub0, killed [[COPY6]], %subreg.sub1, killed [[COPY7]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W32-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]], implicit $exec
|
||||
; W32-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; W32-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; W32-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, killed [[COPY7]], %subreg.sub1, killed [[COPY8]], %subreg.sub2, [[COPY2]], %subreg.sub3
|
||||
; W32-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
|
||||
; W32-NEXT: {{ $}}
|
||||
; W32-NEXT: .1:
|
||||
|
|
@ -280,10 +280,10 @@ body: |
|
|||
; W64-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W64-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W64-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W64-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]], implicit $exec
|
||||
; W64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; W64-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; W64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, killed [[COPY7]], %subreg.sub1, killed [[COPY8]], %subreg.sub2, [[COPY2]], %subreg.sub3
|
||||
; W64-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; W64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; W64-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY2]], implicit $exec
|
||||
; W64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY5]], %subreg.sub0, killed [[COPY6]], %subreg.sub1, killed [[COPY7]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W64-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; W64-NEXT: {{ $}}
|
||||
; W64-NEXT: .1:
|
||||
|
|
@ -327,10 +327,10 @@ body: |
|
|||
; W32-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W32-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W32-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W32-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]], implicit $exec
|
||||
; W32-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; W32-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; W32-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, killed [[COPY7]], %subreg.sub1, killed [[COPY8]], %subreg.sub2, [[COPY2]], %subreg.sub3
|
||||
; W32-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; W32-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; W32-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY2]], implicit $exec
|
||||
; W32-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY5]], %subreg.sub0, killed [[COPY6]], %subreg.sub1, killed [[COPY7]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W32-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
|
||||
; W32-NEXT: {{ $}}
|
||||
; W32-NEXT: .1:
|
||||
|
|
@ -400,9 +400,9 @@ body: |
|
|||
; ADDR64-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; ADDR64-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; ADDR64-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]], implicit $exec
|
||||
; ADDR64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; ADDR64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; ADDR64-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY2]], implicit $exec
|
||||
; ADDR64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, killed [[COPY7]], %subreg.sub1, [[COPY3]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; ADDR64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1, killed [[COPY7]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; ADDR64-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; ADDR64-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||
; ADDR64-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
|
||||
|
|
@ -429,9 +429,9 @@ body: |
|
|||
; W32-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W32-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W32-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]], implicit $exec
|
||||
; W32-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; W32-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; W32-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY2]], implicit $exec
|
||||
; W32-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, killed [[COPY7]], %subreg.sub1, [[COPY3]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W32-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1, killed [[COPY7]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W32-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; W32-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||
; W32-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
|
||||
|
|
@ -485,9 +485,9 @@ body: |
|
|||
; ADDR64-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; ADDR64-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; ADDR64-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]], implicit $exec
|
||||
; ADDR64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; ADDR64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; ADDR64-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY2]], implicit $exec
|
||||
; ADDR64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, killed [[COPY7]], %subreg.sub1, [[COPY3]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; ADDR64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1, killed [[COPY7]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; ADDR64-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; ADDR64-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||
; ADDR64-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
|
||||
|
|
@ -513,9 +513,9 @@ body: |
|
|||
; W64-NO-ADDR64-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W64-NO-ADDR64-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W64-NO-ADDR64-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]], implicit $exec
|
||||
; W64-NO-ADDR64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; W64-NO-ADDR64-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; W64-NO-ADDR64-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY2]], implicit $exec
|
||||
; W64-NO-ADDR64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, killed [[COPY7]], %subreg.sub1, [[COPY3]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W64-NO-ADDR64-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1, killed [[COPY7]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W64-NO-ADDR64-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; W64-NO-ADDR64-NEXT: {{ $}}
|
||||
; W64-NO-ADDR64-NEXT: .1:
|
||||
|
|
@ -560,9 +560,9 @@ body: |
|
|||
; W32-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W32-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; W32-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]], implicit $exec
|
||||
; W32-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]], implicit $exec
|
||||
; W32-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]], implicit $exec
|
||||
; W32-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY2]], implicit $exec
|
||||
; W32-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, killed [[COPY7]], %subreg.sub1, [[COPY3]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W32-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE killed [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1, killed [[COPY7]], %subreg.sub2, killed [[COPY8]], %subreg.sub3
|
||||
; W32-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
|
||||
; W32-NEXT: {{ $}}
|
||||
; W32-NEXT: .1:
|
||||
|
|
|
|||
|
|
@ -433,7 +433,7 @@ define amdgpu_gfx i64 @strict_wwm_called_i64(i64 %a) noinline {
|
|||
; GFX9-O0-NEXT: v_mov_b32_e32 v2, v0
|
||||
; GFX9-O0-NEXT: ; implicit-def: $sgpr34
|
||||
; GFX9-O0-NEXT: ; implicit-def: $sgpr34
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $exec
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec
|
||||
; GFX9-O0-NEXT: v_mov_b32_e32 v3, v1
|
||||
; GFX9-O0-NEXT: ; implicit-def: $sgpr34_sgpr35
|
||||
|
|
@ -585,7 +585,7 @@ define amdgpu_gfx void @strict_wwm_call_i64(<4 x i32> inreg %tmp14, i64 inreg %a
|
|||
; GFX9-O0-NEXT: v_mov_b32_e32 v3, v1
|
||||
; GFX9-O0-NEXT: ; implicit-def: $sgpr40
|
||||
; GFX9-O0-NEXT: ; implicit-def: $sgpr40
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $exec
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $exec
|
||||
; GFX9-O0-NEXT: v_mov_b32_e32 v4, v8
|
||||
; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9
|
||||
; GFX9-O0-NEXT: v_add_co_u32_e64 v2, s[40:41], v2, v4
|
||||
|
|
@ -722,7 +722,7 @@ define amdgpu_gfx void @strict_wwm_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %in
|
|||
; GFX9-O0-NEXT: v_mov_b32_e32 v5, v10
|
||||
; GFX9-O0-NEXT: ; implicit-def: $sgpr35
|
||||
; GFX9-O0-NEXT: ; implicit-def: $sgpr35
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr7 killed $vgpr7 killed $exec
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 killed $exec
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec
|
||||
; GFX9-O0-NEXT: v_mov_b32_e32 v6, v7
|
||||
; GFX9-O0-NEXT: s_mov_b32 s35, 0x7fffffff
|
||||
|
|
@ -741,7 +741,7 @@ define amdgpu_gfx void @strict_wwm_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %in
|
|||
; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12
|
||||
; GFX9-O0-NEXT: ; implicit-def: $sgpr35
|
||||
; GFX9-O0-NEXT: ; implicit-def: $sgpr35
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr7 killed $vgpr7 killed $exec
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 killed $exec
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec
|
||||
; GFX9-O0-NEXT: v_mov_b32_e32 v6, v7
|
||||
; GFX9-O0-NEXT: v_mov_b32_e32 v1, v5
|
||||
|
|
@ -770,7 +770,7 @@ define amdgpu_gfx void @strict_wwm_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %in
|
|||
; GFX9-O0-NEXT: ; implicit-def: $sgpr35
|
||||
; GFX9-O0-NEXT: ; implicit-def: $sgpr35
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 killed $exec
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 killed $exec
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr10 killed $vgpr10 killed $exec
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr9 killed $vgpr9 killed $exec
|
||||
; GFX9-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6_vgpr7_vgpr8 killed $exec
|
||||
; GFX9-O0-NEXT: v_mov_b32_e32 v6, v11
|
||||
|
|
|
|||
Loading…
Reference in New Issue