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[Hexagon] Fix instruction selection for vselect v4i8 

llvm-svn: 369040
This commit is contained in:
Krzysztof Parzyszek 2019-08-15 19:20:09 +00:00
parent ef4ad1a8b6
commit 8e987702b1
3 changed files with 23 additions and 16 deletions
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22
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
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@ -870,15 +870,20 @@ SDValue
HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
SDValue PredOp = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
EVT OpVT = Op1.getValueType();
SDLoc DL(Op);
MVT OpTy = ty(Op1);
const SDLoc &dl(Op);
if (OpVT == MVT::v2i16) {
SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
return TR;
if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
MVT ElemTy = OpTy.getVectorElementType();
assert(ElemTy.isScalarInteger());
MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()),
OpTy.getVectorNumElements());
// Generate (trunc (select (_, sext, sext))).
return DAG.getSExtOrTrunc(
DAG.getSelect(dl, WideTy, PredOp,
DAG.getSExtOrTrunc(Op1, dl, WideTy),
DAG.getSExtOrTrunc(Op2, dl, WideTy)),
dl, OpTy);
}
return SDValue();
@ -1506,6 +1511,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
// Custom-lower bitcasts from i8 to v8i1.
setOperationAction(ISD::BITCAST, MVT::i8, Custom);
setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
setOperationAction(ISD::VSELECT, MVT::v4i8, Custom);
setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);

8
llvm/lib/Target/Hexagon/HexagonPatterns.td
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@ -816,14 +816,6 @@ def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs),
def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I),
(C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>;
def: Pat<(select I1:$Pu, V4I8:$Rs, V4I8:$Rt),
(LoReg (C2_vmux I1:$Pu, (ToAext64 $Rs), (ToAext64 $Rt)))>;
def: Pat<(select I1:$Pu, V2I16:$Rs, V2I16:$Rt),
(LoReg (C2_vmux I1:$Pu, (ToAext64 $Rs), (ToAext64 $Rt)))>;
def: Pat<(select I1:$Pu, V2I32:$Rs, V2I32:$Rt),
(Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
(C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>;
def: Pat<(vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt),
(C2_vmux V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)>;
def: Pat<(vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt),

9
llvm/test/CodeGen/Hexagon/isel-vselect-v4i8.ll Normal file
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@ -0,0 +1,9 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; This used to crash with "cannot select (v4i8 vselect ...)"
; CHECK: vmux
define <4 x i8> @f0(<4 x i8> %a0, <4 x i8> %a1) #0 {
%v0 = icmp slt <4 x i8> %a0, %a1
%v1 = select <4 x i1> %v0, <4 x i8> %a0, <4 x i8> %a1
ret <4 x i8> %v1
}