forked from OSchip/llvm-project
[SystemZ] Add FI[EDX]BRA
These are extensions of the existing FI[EDX]BR instructions, but use a spare bit to suppress inexact conditions. llvm-svn: 188894
This commit is contained in:
Richard Sandiford
parent
ec12322a28
commit
8e92c389e4
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@ -212,15 +212,20 @@ def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>;
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def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>;
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// Round to an integer, with the second operand (modifier M3) specifying
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// the rounding mode.
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//
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// These forms always check for inexact conditions. z196 added versions
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// that allow this to suppressed (as for fnearbyint), but we don't yet
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// support -march=z196.
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// the rounding mode. These forms always check for inexact conditions.
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def FIEBR : UnaryRRF<"fieb", 0xB357, FP32, FP32>;
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def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64, FP64>;
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def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>;
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// Extended forms of the previous three instructions. M4 can be set to 4
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// to suppress detection of inexact conditions.
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def FIEBRA : UnaryRRF4<"fiebra", 0xB357, FP32, FP32>,
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Requires<[FeatureFPExtension]>;
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def FIDBRA : UnaryRRF4<"fidbra", 0xB35F, FP64, FP64>,
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Requires<[FeatureFPExtension]>;
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def FIXBRA : UnaryRRF4<"fixbra", 0xB347, FP128, FP128>,
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Requires<[FeatureFPExtension]>;
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// frint rounds according to the current mode (modifier 0) and detects
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// inexact conditions.
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def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>;
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@ -308,10 +308,11 @@ class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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bits<4> R1;
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bits<4> R2;
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bits<4> R3;
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bits<4> R4;
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let Inst{31-16} = op;
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let Inst{15-12} = R3;
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let Inst{11-8} = 0;
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let Inst{11-8} = R4;
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let Inst{7-4} = R1;
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let Inst{3-0} = R2;
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}
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@ -719,8 +720,14 @@ class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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mnemonic#"r\t$R1, $R3, $R2", []> {
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let OpKey = mnemonic ## cls1;
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let OpType = "reg";
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let R4 = 0;
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}
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class UnaryRRF4<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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RegisterOperand cls2>
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: InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2, uimm8zx4:$R4),
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mnemonic#"\t$R1, $R3, $R2, $R4", []>;
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// These instructions are generated by if conversion. The old value of R1
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// is added as an implicit use.
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class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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@ -729,6 +736,7 @@ class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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mnemonic#"r$R3\t$R1, $R2", []>,
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Requires<[FeatureLoadStoreOnCond]> {
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let CCMaskLast = 1;
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let R4 = 0;
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}
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// Like CondUnaryRRF, but used for the raw assembly form. The condition-code
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@ -740,6 +748,7 @@ class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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Requires<[FeatureLoadStoreOnCond]> {
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let Constraints = "$R1 = $R1src";
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let DisableEncoding = "$R1src";
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let R4 = 0;
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}
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// Like CondUnaryRRF, but with a fixed CC mask.
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@ -751,6 +760,7 @@ class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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let Constraints = "$R1 = $R1src";
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let DisableEncoding = "$R1src";
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let R3 = ccmask;
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let R4 = 0;
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}
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class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
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@ -898,13 +908,16 @@ class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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[(set cls1:$R1, (operator cls1:$R3, cls2:$R2))]> {
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let OpKey = mnemonic ## cls1;
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let OpType = "reg";
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let R4 = 0;
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}
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class BinaryRRFK<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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RegisterOperand cls1, RegisterOperand cls2>
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: InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
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mnemonic#"rk\t$R1, $R2, $R3",
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[(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]>;
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[(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
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let R4 = 0;
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}
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multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
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SDPatternOperator operator, RegisterOperand cls1,
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@ -31,8 +31,15 @@ def FeatureHighWord : SystemZFeature<
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"Assume that the high-word facility is installed"
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>;
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def FeatureFPExtension : SystemZFeature<
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"fp-extension", "FPExtension",
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"Assume that the floating-point extension facility is installed"
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>;
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def : Processor<"z10", NoItineraries, []>;
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def : Processor<"z196", NoItineraries,
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[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord]>;
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[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
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FeatureFPExtension]>;
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def : Processor<"zEC12", NoItineraries,
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[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord]>;
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[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
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FeatureFPExtension]>;
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@ -21,7 +21,8 @@ SystemZSubtarget::SystemZSubtarget(const std::string &TT,
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const std::string &CPU,
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const std::string &FS)
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: SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
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HasLoadStoreOnCond(false), HasHighWord(false), TargetTriple(TT) {
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HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
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TargetTriple(TT) {
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = "z10";
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@ -30,6 +30,7 @@ protected:
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bool HasDistinctOps;
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bool HasLoadStoreOnCond;
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bool HasHighWord;
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bool HasFPExtension;
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private:
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Triple TargetTriple;
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@ -50,6 +51,9 @@ public:
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// Return true if the target has the high-word facility.
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bool hasHighWord() const { return HasHighWord; }
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// Return true if the target has the floating-point extension facility.
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bool hasFPExtension() const { return HasFPExtension; }
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// Return true if GV can be accessed using LARL for reloc model RM
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// and code model CM.
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bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,
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@ -2149,6 +2149,24 @@
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# CHECK: fidbr %f15, 0, %f0
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0xb3 0x5f 0x00 0xf0
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# CHECK: fidbra %f0, 0, %f0, 1
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0xb3 0x5f 0x01 0x00
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# CHECK: fidbra %f0, 0, %f0, 15
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0xb3 0x5f 0x0f 0x00
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# CHECK: fidbra %f0, 0, %f15, 1
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0xb3 0x5f 0x01 0x0f
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# CHECK: fidbra %f0, 15, %f0, 1
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0xb3 0x5f 0xf1 0x00
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# CHECK: fidbra %f4, 5, %f6, 7
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0xb3 0x5f 0x57 0x46
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# CHECK: fidbra %f15, 0, %f0, 1
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0xb3 0x5f 0x01 0xf0
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# CHECK: fiebr %f0, 0, %f0
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0xb3 0x57 0x00 0x00
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@ -2164,6 +2182,24 @@
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# CHECK: fiebr %f15, 0, %f0
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0xb3 0x57 0x00 0xf0
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# CHECK: fiebra %f0, 0, %f0, 1
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0xb3 0x57 0x01 0x00
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# CHECK: fiebra %f0, 0, %f0, 15
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0xb3 0x57 0x0f 0x00
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# CHECK: fiebra %f0, 0, %f15, 1
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0xb3 0x57 0x01 0x0f
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# CHECK: fiebra %f0, 15, %f0, 1
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0xb3 0x57 0xf1 0x00
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# CHECK: fiebra %f4, 5, %f6, 7
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0xb3 0x57 0x57 0x46
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# CHECK: fiebra %f15, 0, %f0, 1
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0xb3 0x57 0x01 0xf0
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# CHECK: fixbr %f0, 0, %f0
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0xb3 0x47 0x00 0x00
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@ -2179,6 +2215,24 @@
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# CHECK: fixbr %f13, 0, %f0
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0xb3 0x47 0x00 0xd0
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# CHECK: fixbra %f0, 0, %f0, 1
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0xb3 0x47 0x01 0x00
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# CHECK: fixbra %f0, 0, %f0, 15
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0xb3 0x47 0x0f 0x00
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# CHECK: fixbra %f0, 0, %f13, 1
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0xb3 0x47 0x01 0x0d
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# CHECK: fixbra %f0, 15, %f0, 1
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0xb3 0x47 0xf1 0x00
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# CHECK: fixbra %f4, 5, %f8, 9
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0xb3 0x47 0x59 0x48
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# CHECK: fixbra %f13, 0, %f0, 1
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0xb3 0x47 0x01 0xd0
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# CHECK: flogr %r0, %r0
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0xb9 0x83 0x00 0x00
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@ -24,6 +24,54 @@
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ahik %r0, %r1, 32768
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ahik %r0, %r1, foo
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#CHECK: error: invalid operand
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#CHECK: fidbra %f0, 0, %f0, -1
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#CHECK: error: invalid operand
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#CHECK: fidbra %f0, 0, %f0, 16
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#CHECK: error: invalid operand
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#CHECK: fidbra %f0, -1, %f0, 0
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#CHECK: error: invalid operand
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#CHECK: fidbra %f0, 16, %f0, 0
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fidbra %f0, 0, %f0, -1
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fidbra %f0, 0, %f0, 16
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fidbra %f0, -1, %f0, 0
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fidbra %f0, 16, %f0, 0
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#CHECK: error: invalid operand
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#CHECK: fiebra %f0, 0, %f0, -1
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#CHECK: error: invalid operand
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#CHECK: fiebra %f0, 0, %f0, 16
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#CHECK: error: invalid operand
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#CHECK: fiebra %f0, -1, %f0, 0
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#CHECK: error: invalid operand
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#CHECK: fiebra %f0, 16, %f0, 0
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fiebra %f0, 0, %f0, -1
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fiebra %f0, 0, %f0, 16
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fiebra %f0, -1, %f0, 0
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fiebra %f0, 16, %f0, 0
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#CHECK: error: invalid operand
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#CHECK: fixbra %f0, 0, %f0, -1
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#CHECK: error: invalid operand
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#CHECK: fixbra %f0, 0, %f0, 16
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#CHECK: error: invalid operand
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#CHECK: fixbra %f0, -1, %f0, 0
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#CHECK: error: invalid operand
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#CHECK: fixbra %f0, 16, %f0, 0
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#CHECK: error: invalid register pair
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#CHECK: fixbra %f0, 0, %f2, 0
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#CHECK: error: invalid register pair
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#CHECK: fixbra %f2, 0, %f0, 0
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fixbra %f0, 0, %f0, -1
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fixbra %f0, 0, %f0, 16
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fixbra %f0, -1, %f0, 0
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fixbra %f0, 16, %f0, 0
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fixbra %f0, 0, %f2, 0
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fixbra %f2, 0, %f0, 0
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#CHECK: error: invalid operand
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#CHECK: loc %r0,0,-1
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#CHECK: error: invalid operand
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@ -1142,6 +1142,11 @@
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fidbr %f0, -1, %f0
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fidbr %f0, 16, %f0
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#CHECK: error: {{(instruction requires: fp-extension)?}}
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#CHECK: fidbra %f0, 0, %f0, 0
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fidbra %f0, 0, %f0, 0
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#CHECK: error: invalid operand
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#CHECK: fiebr %f0, -1, %f0
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#CHECK: error: invalid operand
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@ -1150,6 +1155,11 @@
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fiebr %f0, -1, %f0
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fiebr %f0, 16, %f0
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#CHECK: error: {{(instruction requires: fp-extension)?}}
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#CHECK: fiebra %f0, 0, %f0, 0
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fiebra %f0, 0, %f0, 0
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#CHECK: error: invalid operand
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#CHECK: fixbr %f0, -1, %f0
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#CHECK: error: invalid operand
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@ -1164,6 +1174,11 @@
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fixbr %f0, 0, %f2
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fixbr %f2, 0, %f0
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#CHECK: error: {{(instruction requires: fp-extension)?}}
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#CHECK: fixbra %f0, 0, %f0, 0
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fixbra %f0, 0, %f0, 0
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#CHECK: error: invalid register pair
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#CHECK: flogr %r1, %r0
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@ -121,6 +121,48 @@
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ark %r15,%r0,%r0
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ark %r7,%r8,%r9
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#CHECK: fidbra %f0, 0, %f0, 0 # encoding: [0xb3,0x5f,0x00,0x00]
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#CHECK: fidbra %f0, 0, %f0, 15 # encoding: [0xb3,0x5f,0x0f,0x00]
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#CHECK: fidbra %f0, 0, %f15, 0 # encoding: [0xb3,0x5f,0x00,0x0f]
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#CHECK: fidbra %f0, 15, %f0, 0 # encoding: [0xb3,0x5f,0xf0,0x00]
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#CHECK: fidbra %f4, 5, %f6, 7 # encoding: [0xb3,0x5f,0x57,0x46]
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#CHECK: fidbra %f15, 0, %f0, 0 # encoding: [0xb3,0x5f,0x00,0xf0]
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fidbra %f0, 0, %f0, 0
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fidbra %f0, 0, %f0, 15
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fidbra %f0, 0, %f15, 0
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fidbra %f0, 15, %f0, 0
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fidbra %f4, 5, %f6, 7
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fidbra %f15, 0, %f0, 0
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#CHECK: fiebra %f0, 0, %f0, 0 # encoding: [0xb3,0x57,0x00,0x00]
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#CHECK: fiebra %f0, 0, %f0, 15 # encoding: [0xb3,0x57,0x0f,0x00]
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#CHECK: fiebra %f0, 0, %f15, 0 # encoding: [0xb3,0x57,0x00,0x0f]
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#CHECK: fiebra %f0, 15, %f0, 0 # encoding: [0xb3,0x57,0xf0,0x00]
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#CHECK: fiebra %f4, 5, %f6, 7 # encoding: [0xb3,0x57,0x57,0x46]
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#CHECK: fiebra %f15, 0, %f0, 0 # encoding: [0xb3,0x57,0x00,0xf0]
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fiebra %f0, 0, %f0, 0
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fiebra %f0, 0, %f0, 15
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fiebra %f0, 0, %f15, 0
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fiebra %f0, 15, %f0, 0
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fiebra %f4, 5, %f6, 7
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fiebra %f15, 0, %f0, 0
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#CHECK: fixbra %f0, 0, %f0, 0 # encoding: [0xb3,0x47,0x00,0x00]
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#CHECK: fixbra %f0, 0, %f0, 15 # encoding: [0xb3,0x47,0x0f,0x00]
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#CHECK: fixbra %f0, 0, %f13, 0 # encoding: [0xb3,0x47,0x00,0x0d]
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#CHECK: fixbra %f0, 15, %f0, 0 # encoding: [0xb3,0x47,0xf0,0x00]
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#CHECK: fixbra %f4, 5, %f8, 9 # encoding: [0xb3,0x47,0x59,0x48]
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#CHECK: fixbra %f13, 0, %f0, 0 # encoding: [0xb3,0x47,0x00,0xd0]
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fixbra %f0, 0, %f0, 0
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fixbra %f0, 0, %f0, 15
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fixbra %f0, 0, %f13, 0
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fixbra %f0, 15, %f0, 0
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fixbra %f4, 5, %f8, 9
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fixbra %f13, 0, %f0, 0
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#CHECK: loc %r0, 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xf2]
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#CHECK: loc %r0, 0, 15 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0xf2]
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#CHECK: loc %r0, -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0xf2]
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