forked from OSchip/llvm-project
Use SDValue helper instead of explicitly going via SDValue::getNode(). NFCI
llvm-svn: 287940
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88071b37ab
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@ -15319,7 +15319,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, const SDLoc &dl,
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goto default_case;
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if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
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dyn_cast<ConstantSDNode>(ArithOp.getOperand(1))) {
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// An add of one will be selected as an INC.
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if (C->isOne() && !Subtarget.slowIncDec()) {
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Opcode = X86ISD::INC;
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@ -16322,7 +16322,7 @@ SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
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/// Return true if opcode is a X86 logical comparison.
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static bool isX86LogicalCmp(SDValue Op) {
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unsigned Opc = Op.getNode()->getOpcode();
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unsigned Opc = Op.getOpcode();
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if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
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Opc == X86ISD::SAHF)
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return true;
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@ -17243,7 +17243,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
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case X86::COND_B:
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// These can only come from an arithmetic instruction with overflow,
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// e.g. SADDO, UADDO.
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Cond = Cond.getNode()->getOperand(1);
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Cond = Cond.getOperand(1);
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addTest = false;
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break;
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}
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@ -17600,7 +17600,7 @@ SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
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SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
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assert(Subtarget.is64Bit() &&
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"LowerVAARG only handles 64-bit va_arg!");
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assert(Op.getNode()->getNumOperands() == 4);
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assert(Op.getNumOperands() == 4);
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MachineFunction &MF = DAG.getMachineFunction();
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if (Subtarget.isCallingConvWin64(MF.getFunction()->getCallingConv()))
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@ -27520,7 +27520,7 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
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InputVector.getValueType() == MVT::v2i32 &&
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isa<ConstantSDNode>(N->getOperand(1)) &&
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N->getConstantOperandVal(1) == 0) {
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SDValue MMXSrc = InputVector.getNode()->getOperand(0);
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SDValue MMXSrc = InputVector.getOperand(0);
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// The bitcast source is a direct mmx result.
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if (MMXSrc.getValueType() == MVT::x86mmx)
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