forked from OSchip/llvm-project
[X86] ABI compat bugfix for MSVC vectorcall
Summary:
Before this change, X86_32ABIInfo::classifyArgument would be called
twice on vector arguments to vectorcall functions. This function has
side effects to track GPR register usage, and this would lead to
incorrect GPR usage in some cases. The specific case I noticed is from
running out of XMM registers with mixed FP and vector arguments and no
aggregates of any kind. Consider this prototype:
void __vectorcall vectorcall_indirect_vec(
double xmm0, double xmm1, double xmm2, double xmm3, double xmm4,
__m128 xmm5,
__m128 ecx,
int edx,
__m128 mem);
classifyArgument has no effects when called on a plain FP type, but when
called on a vector type, it modifies FreeRegs to model GPR consumption.
However, this should not happen during the vector call first pass.
I refactored the code to unify vectorcall HVA logic with regcall HVA
logic. The conventions pass HVAs in registers differently (expanded vs.
not expanded), but if they do not fit in registers, they both pass them
indirectly by address.
Reviewers: erichkeane, craig.topper
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72110
This commit is contained in:
Reid Kleckner
parent
0f9cf42fac
commit
8e780252a7
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@ -563,12 +563,11 @@ public:
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typedef const ArgInfo *const_arg_iterator;
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typedef ArgInfo *arg_iterator;
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typedef llvm::iterator_range<arg_iterator> arg_range;
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typedef llvm::iterator_range<const_arg_iterator> const_arg_range;
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arg_range arguments() { return arg_range(arg_begin(), arg_end()); }
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const_arg_range arguments() const {
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return const_arg_range(arg_begin(), arg_end());
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MutableArrayRef<ArgInfo> arguments() {
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return MutableArrayRef<ArgInfo>(arg_begin(), NumArgs);
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}
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ArrayRef<ArgInfo> arguments() const {
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return ArrayRef<ArgInfo>(arg_begin(), NumArgs);
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}
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const_arg_iterator arg_begin() const { return getArgsBuffer() + 1; }
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@ -22,6 +22,7 @@
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#include "clang/Basic/CodeGenOptions.h"
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#include "clang/CodeGen/CGFunctionInfo.h"
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#include "clang/CodeGen/SwiftCallingConv.h"
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#include "llvm/ADT/SmallBitVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Triple.h"
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@ -996,11 +997,13 @@ static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
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/// Similar to llvm::CCState, but for Clang.
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struct CCState {
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CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
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CCState(CGFunctionInfo &FI)
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: IsPreassigned(FI.arg_size()), CC(FI.getCallingConvention()) {}
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unsigned CC;
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unsigned FreeRegs;
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unsigned FreeSSERegs;
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llvm::SmallBitVector IsPreassigned;
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unsigned CC = CallingConv::CC_C;
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unsigned FreeRegs = 0;
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unsigned FreeSSERegs = 0;
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};
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enum {
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@ -1071,8 +1074,7 @@ class X86_32ABIInfo : public SwiftABIInfo {
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void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
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CharUnits &StackOffset, ABIArgInfo &Info,
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QualType Type) const;
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void computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
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bool &UsedInAlloca) const;
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void runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const;
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public:
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@ -1640,9 +1642,38 @@ bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
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return true;
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}
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void X86_32ABIInfo::runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const {
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// Vectorcall x86 works subtly different than in x64, so the format is
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// a bit different than the x64 version. First, all vector types (not HVAs)
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// are assigned, with the first 6 ending up in the [XYZ]MM0-5 registers.
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// This differs from the x64 implementation, where the first 6 by INDEX get
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// registers.
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// In the second pass over the arguments, HVAs are passed in the remaining
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// vector registers if possible, or indirectly by address. The address will be
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// passed in ECX/EDX if available. Any other arguments are passed according to
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// the usual fastcall rules.
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MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments();
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for (int I = 0, E = Args.size(); I < E; ++I) {
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const Type *Base = nullptr;
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uint64_t NumElts = 0;
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const QualType &Ty = Args[I].type;
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if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
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isHomogeneousAggregate(Ty, Base, NumElts)) {
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if (State.FreeSSERegs >= NumElts) {
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State.FreeSSERegs -= NumElts;
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Args[I].info = ABIArgInfo::getDirect();
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State.IsPreassigned.set(I);
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}
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}
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}
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}
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ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
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CCState &State) const {
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// FIXME: Set alignment on indirect arguments.
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bool IsFastCall = State.CC == llvm::CallingConv::X86_FastCall;
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bool IsRegCall = State.CC == llvm::CallingConv::X86_RegCall;
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bool IsVectorCall = State.CC == llvm::CallingConv::X86_VectorCall;
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Ty = useFirstFieldIfTransparentUnion(Ty);
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@ -1662,11 +1693,16 @@ ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
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// to other targets.
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const Type *Base = nullptr;
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uint64_t NumElts = 0;
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if (State.CC == llvm::CallingConv::X86_RegCall &&
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if ((IsRegCall || IsVectorCall) &&
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isHomogeneousAggregate(Ty, Base, NumElts)) {
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if (State.FreeSSERegs >= NumElts) {
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State.FreeSSERegs -= NumElts;
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// Vectorcall passes HVAs directly and does not flatten them, but regcall
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// does.
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if (IsVectorCall)
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return getDirectX86Hva();
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if (Ty->isBuiltinType() || Ty->isVectorType())
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return ABIArgInfo::getDirect();
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return ABIArgInfo::getExpand();
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@ -1708,10 +1744,7 @@ ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
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if (getContext().getTypeSize(Ty) <= 4 * 32 &&
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(!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty))
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return ABIArgInfo::getExpandWithPadding(
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State.CC == llvm::CallingConv::X86_FastCall ||
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State.CC == llvm::CallingConv::X86_VectorCall ||
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State.CC == llvm::CallingConv::X86_RegCall,
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PaddingType);
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IsFastCall || IsVectorCall || IsRegCall, PaddingType);
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return getIndirectResult(Ty, true, State);
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}
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@ -1750,60 +1783,8 @@ ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
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return ABIArgInfo::getDirect();
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}
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void X86_32ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
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bool &UsedInAlloca) const {
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// Vectorcall x86 works subtly different than in x64, so the format is
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// a bit different than the x64 version. First, all vector types (not HVAs)
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// are assigned, with the first 6 ending up in the YMM0-5 or XMM0-5 registers.
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// This differs from the x64 implementation, where the first 6 by INDEX get
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// registers.
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// After that, integers AND HVAs are assigned Left to Right in the same pass.
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// Integers are passed as ECX/EDX if one is available (in order). HVAs will
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// first take up the remaining YMM/XMM registers. If insufficient registers
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// remain but an integer register (ECX/EDX) is available, it will be passed
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// in that, else, on the stack.
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for (auto &I : FI.arguments()) {
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// First pass do all the vector types.
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const Type *Base = nullptr;
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uint64_t NumElts = 0;
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const QualType& Ty = I.type;
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if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
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isHomogeneousAggregate(Ty, Base, NumElts)) {
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if (State.FreeSSERegs >= NumElts) {
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State.FreeSSERegs -= NumElts;
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I.info = ABIArgInfo::getDirect();
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} else {
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I.info = classifyArgumentType(Ty, State);
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}
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UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
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}
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}
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for (auto &I : FI.arguments()) {
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// Second pass, do the rest!
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const Type *Base = nullptr;
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uint64_t NumElts = 0;
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const QualType& Ty = I.type;
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bool IsHva = isHomogeneousAggregate(Ty, Base, NumElts);
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if (IsHva && !Ty->isVectorType() && !Ty->isBuiltinType()) {
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// Assign true HVAs (non vector/native FP types).
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if (State.FreeSSERegs >= NumElts) {
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State.FreeSSERegs -= NumElts;
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I.info = getDirectX86Hva();
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} else {
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I.info = getIndirectResult(Ty, /*ByVal=*/false, State);
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}
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} else if (!IsHva) {
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// Assign all Non-HVAs, so this will exclude Vector/FP args.
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I.info = classifyArgumentType(Ty, State);
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UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
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}
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}
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}
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void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
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CCState State(FI.getCallingConvention());
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CCState State(FI);
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if (IsMCUABI)
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State.FreeRegs = 3;
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else if (State.CC == llvm::CallingConv::X86_FastCall)
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@ -1835,15 +1816,20 @@ void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
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if (FI.isChainCall())
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++State.FreeRegs;
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// For vectorcall, do a first pass over the arguments, assigning FP and vector
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// arguments to XMM registers as available.
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if (State.CC == llvm::CallingConv::X86_VectorCall)
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runVectorCallFirstPass(FI, State);
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bool UsedInAlloca = false;
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if (State.CC == llvm::CallingConv::X86_VectorCall) {
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computeVectorCallArgs(FI, State, UsedInAlloca);
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} else {
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// If not vectorcall, revert to normal behavior.
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for (auto &I : FI.arguments()) {
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I.info = classifyArgumentType(I.type, State);
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UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
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}
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MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments();
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for (int I = 0, E = Args.size(); I < E; ++I) {
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// Skip arguments that have already been assigned.
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if (State.IsPreassigned.test(I))
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continue;
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Args[I].info = classifyArgumentType(Args[I].type, State);
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UsedInAlloca |= (Args[I].info.getKind() == ABIArgInfo::InAlloca);
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}
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// If we needed to use inalloca for any argument, do a second pass and rewrite
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@ -7594,7 +7580,7 @@ public:
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bool shouldUseInReg(QualType Ty, CCState &State) const;
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void computeInfo(CGFunctionInfo &FI) const override {
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CCState State(FI.getCallingConvention());
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CCState State(FI);
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// Lanai uses 4 registers to pass arguments unless the function has the
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// regparm attribute set.
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if (FI.getHasRegParm()) {
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@ -8570,7 +8556,7 @@ private:
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}
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void computeInfo(CGFunctionInfo &FI) const override {
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CCState State(FI.getCallingConvention());
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CCState State(FI);
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// ARC uses 8 registers to pass arguments.
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State.FreeRegs = 8;
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@ -116,3 +116,24 @@ void __vectorcall HVAAnywhere(struct HFA2 p1, int p2, int p3, float p4, int p5,
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// X32: define dso_local x86_vectorcallcc void @"\01HVAAnywhere@@88"(%struct.HFA2 inreg %p1.coerce, i32 inreg %p2, i32 inreg %p3, float %p4, i32 %p5, i32 %p6, %struct.HFA4* %p7, %struct.HFA2 inreg %p8.coerce, float %p9)
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// X64: define dso_local x86_vectorcallcc void @"\01HVAAnywhere@@112"(%struct.HFA2 inreg %p1.coerce, i32 %p2, i32 %p3, float %p4, i32 %p5, i32 %p6, %struct.HFA4* %p7, %struct.HFA2 inreg %p8.coerce, float %p9)
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#ifndef __x86_64__
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// This covers the three ways XMM values can be passed on 32-bit x86:
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// - directly in XMM register (xmm5)
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// - indirectly by address, address in GPR (ecx)
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// - indirectly by address, address on stack
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void __vectorcall vectorcall_indirect_vec(
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double xmm0, double xmm1, double xmm2, double xmm3, double xmm4,
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v4f32 xmm5, v4f32 ecx, int edx, v4f32 mem) {
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}
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// X32: define dso_local x86_vectorcallcc void @"\01vectorcall_indirect_vec@@{{[0-9]+}}"
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// X32-SAME: (double %xmm0,
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// X32-SAME: double %xmm1,
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// X32-SAME: double %xmm2,
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// X32-SAME: double %xmm3,
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// X32-SAME: double %xmm4,
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// X32-SAME: <4 x float> %xmm5,
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// X32-SAME: <4 x float>* inreg %0,
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// X32-SAME: i32 inreg %edx,
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// X32-SAME: <4 x float>* %1)
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#endif
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