forked from OSchip/llvm-project
[x86] avoid crashing when splitting AVX stores with non-simple type (PR43916)
The store splitting transform was assuming a simple type (MVT), but that's not necessarily the case as shown in the test.
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@ -21776,12 +21776,14 @@ static SDValue splitVectorStore(StoreSDNode *Store, SelectionDAG &DAG) {
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"Expecting 256/512-bit op");
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// Splitting volatile memory ops is not allowed unless the operation was not
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// legal to begin with. We are assuming the input op is legal (this transform
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// is only used for targets with AVX).
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// legal to begin with. Assume the input store is legal (this transform is
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// only used for targets with AVX). Note: It is possible that we have an
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// illegal type like v2i128, and so we could allow splitting a volatile store
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// in that case if that is important.
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if (!Store->isSimple())
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return SDValue();
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MVT StoreVT = StoredVal.getSimpleValueType();
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EVT StoreVT = StoredVal.getValueType();
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unsigned NumElems = StoreVT.getVectorNumElements();
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unsigned HalfSize = StoredVal.getValueSizeInBits() / 2;
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unsigned HalfAlign = (128 == HalfSize ? 16 : 32);
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@ -333,3 +333,26 @@ define void @add4i64a16(<4 x i64>* %ret, <4 x i64>* %bp) nounwind {
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ret void
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}
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; This used to crash.
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; v2i128 may not be a "simple" (MVT) type, but we can split that.
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; This example gets split further in legalization.
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define void @PR43916(<2 x i128> %y, <2 x i128>* %z) {
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; CHECK-LABEL: PR43916:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rcx, 24(%r8)
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; CHECK-NEXT: movq %rdx, 16(%r8)
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; CHECK-NEXT: movq %rsi, 8(%r8)
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; CHECK-NEXT: movq %rdi, (%r8)
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; CHECK-NEXT: retq
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;
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; CHECK_O0-LABEL: PR43916:
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; CHECK_O0: # %bb.0:
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; CHECK_O0-NEXT: movq %rdi, (%r8)
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; CHECK_O0-NEXT: movq %rsi, 8(%r8)
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; CHECK_O0-NEXT: movq %rdx, 16(%r8)
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; CHECK_O0-NEXT: movq %rcx, 24(%r8)
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; CHECK_O0-NEXT: retq
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store <2 x i128> %y, <2 x i128>* %z, align 16
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ret void
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}
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