From 8e086cedfa36cd3badb6cfcb1b19811dcdc4c3b3 Mon Sep 17 00:00:00 2001 From: Jozef Kolek Date: Tue, 21 Apr 2015 11:17:25 +0000 Subject: [PATCH] [mips][microMIPSr6] Implement CACHE and PREF instructions Implement CACHE and PREF instructions using mapping. Differential Revision: http://reviews.llvm.org/D8893 llvm-svn: 235379 --- .../lib/Target/Mips/MicroMips32r6InstrFormats.td | 13 +++++++++++++ llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td | 16 ++++++++++++++++ llvm/lib/Target/Mips/Mips32r6InstrInfo.td | 6 +++--- llvm/test/MC/Disassembler/Mips/micromips32r6.txt | 6 ++++++ llvm/test/MC/Mips/micromips32r6/valid.s | 2 ++ 5 files changed, 40 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td b/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td index 1b2acc1f6ab3..3e20fe51b081 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -29,3 +29,16 @@ class POOL32A_BITSWAP_FM_MMR6 funct> : MipsR6Inst { let Inst{11-6} = funct; let Inst{5-0} = 0b111100; } + +class CACHE_PREF_FM_MMR6 opgroup, bits<4> funct> : MipsR6Inst { + bits<21> addr; + bits<5> hint; + + bits<32> Inst; + + let Inst{31-26} = opgroup; + let Inst{25-21} = hint; + let Inst{20-16} = addr{20-16}; + let Inst{15-12} = funct; + let Inst{11-0} = addr{11-0}; +} diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td index acc7ba7f37e6..c27b6dd38f36 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -20,6 +20,8 @@ class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>; class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>; class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>; +class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>; +class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>; //===----------------------------------------------------------------------===// // @@ -51,6 +53,18 @@ class BITSWAP_MMR6_DESC_BASE class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>; +class CACHE_HINT_MMR6_DESC : MMR6Arch { + dag OutOperandList = (outs); + dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); + string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); + list Pattern = []; + string DecoderMethod = "DecodeCacheOpMM"; +} + +class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>; +class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>; + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -62,4 +76,6 @@ def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6; def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6; def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC, ISA_MICROMIPS32R6; +def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6; +def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6; } diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td index 8651a83eaad8..e80d9f44772c 100644 --- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td @@ -546,7 +546,7 @@ class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>; class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>; class CACHE_HINT_DESC { + RegisterOperand GPROpnd> : MipsR6Arch { dag OutOperandList = (outs); dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); @@ -677,7 +677,7 @@ def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6; def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6; def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6; def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6; -def CACHE_R6 : CACHE_ENC, CACHE_DESC, ISA_MIPS32R6; +def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6; def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6; def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6; def CLO_R6 : CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6; @@ -714,7 +714,7 @@ def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6; def NAL; // BAL with rd=0 -def PREF_R6 : PREF_ENC, PREF_DESC, ISA_MIPS32R6; +def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6; def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6; def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6; def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r6.txt b/llvm/test/MC/Disassembler/Mips/micromips32r6.txt index cbd7680962ea..b612634e4882 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r6.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r6.txt @@ -8,3 +8,9 @@ # CHECK: bitswap $4, $2 0x00 0x44 0x0b 0x3c + +# CHECK: cache 1, 8($5) +0x20 0x25 0x60 0x08 + +# CHECK: pref 1, 8($5) +0x60 0x25 0x20 0x08 diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s index 2ffa6a9607a4..b08dcafa0517 100644 --- a/llvm/test/MC/Mips/micromips32r6/valid.s +++ b/llvm/test/MC/Mips/micromips32r6/valid.s @@ -4,3 +4,5 @@ balc 14572256 # CHECK: balc 14572256 # encoding: [0xb4,0x37,0x96,0xb8] bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8] bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08] + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08]