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[RISCV] Set CostPerUse to 1 iff RVC is enabled 

After D86836, we can define multiple cost values for
different cost models. So here we set CostPerUse to
1 iff RVC is enabled to avoid potential impact on RA.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117741
This commit is contained in:
wangpc 2022-01-21 13:54:09 +08:00
parent 82bb8a588d
commit 8def89b5dc
66 changed files with 6895 additions and 7022 deletions
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5
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
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@ -347,3 +347,8 @@ void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
Ops.push_back(dwarf::DW_OP_minus);
}
}
unsigned
RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
return MF.getSubtarget<RISCVSubtarget>().hasStdExtC() ? 1 : 0;
}

2
llvm/lib/Target/RISCV/RISCVRegisterInfo.h
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@ -66,6 +66,8 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
void getOffsetOpcodes(const StackOffset &Offset,
SmallVectorImpl<uint64_t> &Ops) const override;
unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override;
};
}

7
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
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@ -73,12 +73,11 @@ def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>;
// are not part of GPRC, the most restrictive register class used by the
// compressed instruction set. This will influence the greedy register
// allocator to reduce the use of registers that can't be encoded in 16 bit
// instructions. This affects register allocation even when compressed
// instruction isn't targeted, we see no major negative codegen impact.
// instructions.
let RegAltNameIndices = [ABIRegAltName] in {
def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
let CostPerUse = [1] in {
let CostPerUse = [0, 1] in {
def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
@ -95,7 +94,7 @@ let RegAltNameIndices = [ABIRegAltName] in {
def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>;
def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>;
def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>;
let CostPerUse = [1] in {
let CostPerUse = [0, 1] in {
def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>;
def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>;
def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>;

20
llvm/test/CodeGen/RISCV/add-before-shl.ll
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@ -163,23 +163,23 @@ define i128 @add_wide_operand(i128 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: lw a6, 12(a1)
; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: lw a1, 8(a1)
; RV32I-NEXT: srli a5, a2, 29
; RV32I-NEXT: slli a4, a3, 3
; RV32I-NEXT: or a4, a4, a5
; RV32I-NEXT: slli a6, a3, 3
; RV32I-NEXT: or a5, a6, a5
; RV32I-NEXT: srli a3, a3, 29
; RV32I-NEXT: slli a5, a1, 3
; RV32I-NEXT: or a3, a5, a3
; RV32I-NEXT: slli a6, a1, 3
; RV32I-NEXT: or a3, a6, a3
; RV32I-NEXT: srli a1, a1, 29
; RV32I-NEXT: slli a5, a6, 3
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: slli a4, a4, 3
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: slli a2, a2, 3
; RV32I-NEXT: lui a5, 128
; RV32I-NEXT: add a1, a1, a5
; RV32I-NEXT: lui a4, 128
; RV32I-NEXT: add a1, a1, a4
; RV32I-NEXT: sw a2, 0(a0)
; RV32I-NEXT: sw a3, 8(a0)
; RV32I-NEXT: sw a4, 4(a0)
; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: jalr zero, 0(ra)
;

30
llvm/test/CodeGen/RISCV/addcarry.ll
View File

@ -10,19 +10,19 @@ define i64 @addcarry(i64 %x, i64 %y) nounwind {
; RISCV32-LABEL: addcarry:
; RISCV32: # %bb.0:
; RISCV32-NEXT: mul a4, a0, a3
; RISCV32-NEXT: mulhu a7, a0, a2
; RISCV32-NEXT: add a4, a7, a4
; RISCV32-NEXT: mul a5, a1, a2
; RISCV32-NEXT: add a6, a4, a5
; RISCV32-NEXT: sltu t0, a6, a4
; RISCV32-NEXT: sltu a4, a4, a7
; RISCV32-NEXT: mulhu a5, a0, a3
; RISCV32-NEXT: add a4, a5, a4
; RISCV32-NEXT: mulhu a5, a1, a2
; RISCV32-NEXT: add a4, a4, a5
; RISCV32-NEXT: add a4, a4, t0
; RISCV32-NEXT: mul a5, a1, a3
; RISCV32-NEXT: add a5, a4, a5
; RISCV32-NEXT: mulhu a5, a0, a2
; RISCV32-NEXT: add a6, a5, a4
; RISCV32-NEXT: mul a4, a1, a2
; RISCV32-NEXT: add a4, a6, a4
; RISCV32-NEXT: sltu a7, a4, a6
; RISCV32-NEXT: sltu a5, a6, a5
; RISCV32-NEXT: mulhu a6, a0, a3
; RISCV32-NEXT: add a5, a6, a5
; RISCV32-NEXT: mulhu a6, a1, a2
; RISCV32-NEXT: add a5, a5, a6
; RISCV32-NEXT: add a5, a5, a7
; RISCV32-NEXT: mul a6, a1, a3
; RISCV32-NEXT: add a5, a5, a6
; RISCV32-NEXT: bgez a1, .LBB0_2
; RISCV32-NEXT: # %bb.1:
; RISCV32-NEXT: sub a5, a5, a2
@ -32,9 +32,9 @@ define i64 @addcarry(i64 %x, i64 %y) nounwind {
; RISCV32-NEXT: sub a5, a5, a0
; RISCV32-NEXT: .LBB0_4:
; RISCV32-NEXT: slli a1, a5, 30
; RISCV32-NEXT: srli a3, a6, 2
; RISCV32-NEXT: srli a3, a4, 2
; RISCV32-NEXT: or a1, a1, a3
; RISCV32-NEXT: slli a3, a6, 30
; RISCV32-NEXT: slli a3, a4, 30
; RISCV32-NEXT: mul a0, a0, a2
; RISCV32-NEXT: srli a0, a0, 2
; RISCV32-NEXT: or a0, a3, a0

2400
llvm/test/CodeGen/RISCV/atomic-rmw.ll
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File diff suppressed because it is too large Load Diff

480
llvm/test/CodeGen/RISCV/atomic-signext.ll
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File diff suppressed because it is too large Load Diff

98
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
View File

@ -437,21 +437,21 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s4
; RV32I-NEXT: not a1, s2
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: addi s4, a2, 1365
; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: addi s5, a1, 819
; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
@ -459,32 +459,32 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: addi s3, a1, 257
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, s3, -1
; RV32I-NEXT: not a1, s3
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a0, s1, -1
; RV32I-NEXT: not a1, s1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s4, .LBB7_2
; RV32I-NEXT: bnez s2, .LBB7_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB7_3
; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: srli a0, s0, 24
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
@ -711,21 +711,21 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s4
; RV32I-NEXT: not a1, s2
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: addi s4, a2, 1365
; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: addi s5, a1, 819
; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
@ -733,32 +733,32 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: addi s3, a1, 257
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, s3, -1
; RV32I-NEXT: not a1, s3
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a0, s1, -1
; RV32I-NEXT: not a1, s1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s4, .LBB11_2
; RV32I-NEXT: bnez s2, .LBB11_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB11_3
; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: srli a0, s0, 24
; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
@ -877,17 +877,17 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: srli a0, a1, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s3, a2, 1365
; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: addi s2, a2, 1365
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: addi s3, a1, 819
; RV32I-NEXT: and a1, a0, s3
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
@ -899,12 +899,12 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli s5, a0, 24
; RV32I-NEXT: srli a0, s2, 1
; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: sub a0, s2, a0
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, s0, 1
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: sub a0, s0, a0
; RV32I-NEXT: and a1, a0, s3
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1

796
llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
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File diff suppressed because it is too large Load Diff

76
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
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@ -190,21 +190,21 @@ define i32 @caller_many_scalars() nounwind {
define i32 @callee_large_scalars(i128 %a, fp128 %b) nounwind {
; RV32I-FPELIM-LABEL: callee_large_scalars:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a6, 0(a1)
; RV32I-FPELIM-NEXT: lw a7, 0(a0)
; RV32I-FPELIM-NEXT: lw a2, 0(a1)
; RV32I-FPELIM-NEXT: lw a3, 0(a0)
; RV32I-FPELIM-NEXT: lw a4, 4(a1)
; RV32I-FPELIM-NEXT: lw a5, 12(a1)
; RV32I-FPELIM-NEXT: lw a2, 12(a0)
; RV32I-FPELIM-NEXT: lw a3, 4(a0)
; RV32I-FPELIM-NEXT: lw a6, 12(a0)
; RV32I-FPELIM-NEXT: lw a7, 4(a0)
; RV32I-FPELIM-NEXT: lw a1, 8(a1)
; RV32I-FPELIM-NEXT: lw a0, 8(a0)
; RV32I-FPELIM-NEXT: xor a2, a2, a5
; RV32I-FPELIM-NEXT: xor a3, a3, a4
; RV32I-FPELIM-NEXT: or a2, a3, a2
; RV32I-FPELIM-NEXT: xor a5, a6, a5
; RV32I-FPELIM-NEXT: xor a4, a7, a4
; RV32I-FPELIM-NEXT: or a4, a4, a5
; RV32I-FPELIM-NEXT: xor a0, a0, a1
; RV32I-FPELIM-NEXT: xor a1, a7, a6
; RV32I-FPELIM-NEXT: xor a1, a3, a2
; RV32I-FPELIM-NEXT: or a0, a1, a0
; RV32I-FPELIM-NEXT: or a0, a0, a2
; RV32I-FPELIM-NEXT: or a0, a0, a4
; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret
;
@ -214,21 +214,21 @@ define i32 @callee_large_scalars(i128 %a, fp128 %b) nounwind {
; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a6, 0(a1)
; RV32I-WITHFP-NEXT: lw a7, 0(a0)
; RV32I-WITHFP-NEXT: lw a2, 0(a1)
; RV32I-WITHFP-NEXT: lw a3, 0(a0)
; RV32I-WITHFP-NEXT: lw a4, 4(a1)
; RV32I-WITHFP-NEXT: lw a5, 12(a1)
; RV32I-WITHFP-NEXT: lw a2, 12(a0)
; RV32I-WITHFP-NEXT: lw a3, 4(a0)
; RV32I-WITHFP-NEXT: lw a6, 12(a0)
; RV32I-WITHFP-NEXT: lw a7, 4(a0)
; RV32I-WITHFP-NEXT: lw a1, 8(a1)
; RV32I-WITHFP-NEXT: lw a0, 8(a0)
; RV32I-WITHFP-NEXT: xor a2, a2, a5
; RV32I-WITHFP-NEXT: xor a3, a3, a4
; RV32I-WITHFP-NEXT: or a2, a3, a2
; RV32I-WITHFP-NEXT: xor a5, a6, a5
; RV32I-WITHFP-NEXT: xor a4, a7, a4
; RV32I-WITHFP-NEXT: or a4, a4, a5
; RV32I-WITHFP-NEXT: xor a0, a0, a1
; RV32I-WITHFP-NEXT: xor a1, a7, a6
; RV32I-WITHFP-NEXT: xor a1, a3, a2
; RV32I-WITHFP-NEXT: or a0, a1, a0
; RV32I-WITHFP-NEXT: or a0, a0, a2
; RV32I-WITHFP-NEXT: or a0, a0, a4
; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@ -297,21 +297,21 @@ define i32 @callee_large_scalars_exhausted_regs(i32 %a, i32 %b, i32 %c, i32 %d,
; RV32I-FPELIM-LABEL: callee_large_scalars_exhausted_regs:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a0, 4(sp)
; RV32I-FPELIM-NEXT: lw a6, 0(a0)
; RV32I-FPELIM-NEXT: lw t0, 0(a7)
; RV32I-FPELIM-NEXT: lw a1, 0(a0)
; RV32I-FPELIM-NEXT: lw a2, 0(a7)
; RV32I-FPELIM-NEXT: lw a3, 4(a0)
; RV32I-FPELIM-NEXT: lw a4, 12(a0)
; RV32I-FPELIM-NEXT: lw a5, 12(a7)
; RV32I-FPELIM-NEXT: lw a1, 4(a7)
; RV32I-FPELIM-NEXT: lw a6, 4(a7)
; RV32I-FPELIM-NEXT: lw a0, 8(a0)
; RV32I-FPELIM-NEXT: lw a2, 8(a7)
; RV32I-FPELIM-NEXT: lw a7, 8(a7)
; RV32I-FPELIM-NEXT: xor a4, a5, a4
; RV32I-FPELIM-NEXT: xor a1, a1, a3
; RV32I-FPELIM-NEXT: or a1, a1, a4
; RV32I-FPELIM-NEXT: xor a0, a2, a0
; RV32I-FPELIM-NEXT: xor a2, t0, a6
; RV32I-FPELIM-NEXT: or a0, a2, a0
; RV32I-FPELIM-NEXT: or a0, a0, a1
; RV32I-FPELIM-NEXT: xor a3, a6, a3
; RV32I-FPELIM-NEXT: or a3, a3, a4
; RV32I-FPELIM-NEXT: xor a0, a7, a0
; RV32I-FPELIM-NEXT: xor a1, a2, a1
; RV32I-FPELIM-NEXT: or a0, a1, a0
; RV32I-FPELIM-NEXT: or a0, a0, a3
; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret
;
@ -322,21 +322,21 @@ define i32 @callee_large_scalars_exhausted_regs(i32 %a, i32 %b, i32 %c, i32 %d,
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a0, 4(s0)
; RV32I-WITHFP-NEXT: lw a6, 0(a0)
; RV32I-WITHFP-NEXT: lw t0, 0(a7)
; RV32I-WITHFP-NEXT: lw a1, 0(a0)
; RV32I-WITHFP-NEXT: lw a2, 0(a7)
; RV32I-WITHFP-NEXT: lw a3, 4(a0)
; RV32I-WITHFP-NEXT: lw a4, 12(a0)
; RV32I-WITHFP-NEXT: lw a5, 12(a7)
; RV32I-WITHFP-NEXT: lw a1, 4(a7)
; RV32I-WITHFP-NEXT: lw a6, 4(a7)
; RV32I-WITHFP-NEXT: lw a0, 8(a0)
; RV32I-WITHFP-NEXT: lw a2, 8(a7)
; RV32I-WITHFP-NEXT: lw a7, 8(a7)
; RV32I-WITHFP-NEXT: xor a4, a5, a4
; RV32I-WITHFP-NEXT: xor a1, a1, a3
; RV32I-WITHFP-NEXT: or a1, a1, a4
; RV32I-WITHFP-NEXT: xor a0, a2, a0
; RV32I-WITHFP-NEXT: xor a2, t0, a6
; RV32I-WITHFP-NEXT: or a0, a2, a0
; RV32I-WITHFP-NEXT: or a0, a0, a1
; RV32I-WITHFP-NEXT: xor a3, a6, a3
; RV32I-WITHFP-NEXT: or a3, a3, a4
; RV32I-WITHFP-NEXT: xor a0, a7, a0
; RV32I-WITHFP-NEXT: xor a1, a2, a1
; RV32I-WITHFP-NEXT: or a0, a1, a0
; RV32I-WITHFP-NEXT: or a0, a0, a3
; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload

38
llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
View File

@ -106,21 +106,21 @@ define i32 @caller_many_scalars() nounwind {
define i64 @callee_large_scalars(i256 %a, i256 %b) nounwind {
; RV64I-LABEL: callee_large_scalars:
; RV64I: # %bb.0:
; RV64I-NEXT: ld a6, 0(a1)
; RV64I-NEXT: ld a7, 0(a0)
; RV64I-NEXT: ld a2, 0(a1)
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a4, 8(a1)
; RV64I-NEXT: ld a5, 24(a1)
; RV64I-NEXT: ld a2, 24(a0)
; RV64I-NEXT: ld a3, 8(a0)
; RV64I-NEXT: ld a6, 24(a0)
; RV64I-NEXT: ld a7, 8(a0)
; RV64I-NEXT: ld a1, 16(a1)
; RV64I-NEXT: ld a0, 16(a0)
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: xor a3, a3, a4
; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: xor a5, a6, a5
; RV64I-NEXT: xor a4, a7, a4
; RV64I-NEXT: or a4, a4, a5
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: xor a1, a7, a6
; RV64I-NEXT: xor a1, a3, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a4
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp eq i256 %a, %b
@ -161,21 +161,21 @@ define i64 @callee_large_scalars_exhausted_regs(i64 %a, i64 %b, i64 %c, i64 %d,
; RV64I-LABEL: callee_large_scalars_exhausted_regs:
; RV64I: # %bb.0:
; RV64I-NEXT: ld a0, 8(sp)
; RV64I-NEXT: ld a6, 0(a0)
; RV64I-NEXT: ld t0, 0(a7)
; RV64I-NEXT: ld a1, 0(a0)
; RV64I-NEXT: ld a2, 0(a7)
; RV64I-NEXT: ld a3, 8(a0)
; RV64I-NEXT: ld a4, 24(a0)
; RV64I-NEXT: ld a5, 24(a7)
; RV64I-NEXT: ld a1, 8(a7)
; RV64I-NEXT: ld a6, 8(a7)
; RV64I-NEXT: ld a0, 16(a0)
; RV64I-NEXT: ld a2, 16(a7)
; RV64I-NEXT: ld a7, 16(a7)
; RV64I-NEXT: xor a4, a5, a4
; RV64I-NEXT: xor a1, a1, a3
; RV64I-NEXT: or a1, a1, a4
; RV64I-NEXT: xor a0, a2, a0
; RV64I-NEXT: xor a2, t0, a6
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: xor a3, a6, a3
; RV64I-NEXT: or a3, a3, a4
; RV64I-NEXT: xor a0, a7, a0
; RV64I-NEXT: xor a1, a2, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp eq i256 %h, %j

92
llvm/test/CodeGen/RISCV/double-arith-strict.ll
View File

@ -313,10 +313,10 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind strictfp {
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: li a2, 0
@ -325,10 +325,10 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind strictfp {
; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a5, a1, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@ -393,25 +393,25 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind strictfp {
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s4, a5
; RV32I-NEXT: mv s5, a4
; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv a0, s5
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a2, s1, a0
; RV32I-NEXT: xor a2, s5, a0
; RV32I-NEXT: xor a5, a1, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
@ -434,19 +434,19 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind strictfp {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a2, a1, 63
; RV64I-NEXT: xor a1, s1, a2
; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fma@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@ -489,7 +489,7 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind strictfp {
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s4, a5
; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
@ -498,20 +498,20 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind strictfp {
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a3, s0, a0
; RV32I-NEXT: xor a3, s5, a0
; RV32I-NEXT: xor a5, a1, a0
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s5
; RV32I-NEXT: mv a2, s4
; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@ -531,19 +531,19 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind strictfp {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a2, a1, 63
; RV64I-NEXT: xor a1, s1, a2
; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fma@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@ -582,19 +582,19 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind strictfp {
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a5
; RV32I-NEXT: mv s3, a4
; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: mv a4, s3
; RV32I-NEXT: mv a5, s2
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a4, s1
; RV32I-NEXT: mv a5, s0
; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@ -654,10 +654,10 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind strictfp {
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a5
; RV32I-NEXT: mv s3, a4
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: li a2, 0
@ -666,10 +666,10 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind strictfp {
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a3, a1, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a4, s3
; RV32I-NEXT: mv a5, s2
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, s1
; RV32I-NEXT: mv a5, s0
; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload

208
llvm/test/CodeGen/RISCV/double-arith.ll
View File

@ -479,10 +479,10 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: li a2, 0
@ -491,10 +491,10 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a5, a1, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@ -559,25 +559,25 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s4, a5
; RV32I-NEXT: mv s5, a4
; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv a0, s5
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a2, s1, a0
; RV32I-NEXT: xor a2, s5, a0
; RV32I-NEXT: xor a5, a1, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
@ -600,19 +600,19 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a2, a1, 63
; RV64I-NEXT: xor a1, s1, a2
; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fma@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@ -655,7 +655,7 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s4, a5
; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
@ -664,20 +664,20 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a3, s0, a0
; RV32I-NEXT: xor a3, s5, a0
; RV32I-NEXT: xor a5, a1, a0
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s5
; RV32I-NEXT: mv a2, s4
; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@ -697,19 +697,19 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a2, a1, 63
; RV64I-NEXT: xor a1, s1, a2
; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fma@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@ -748,19 +748,19 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a5
; RV32I-NEXT: mv s3, a4
; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: mv a4, s3
; RV32I-NEXT: mv a5, s2
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a4, s1
; RV32I-NEXT: mv a5, s0
; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@ -820,10 +820,10 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a5
; RV32I-NEXT: mv s3, a4
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: li a2, 0
@ -832,10 +832,10 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a3, a1, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a4, s3
; RV32I-NEXT: mv a5, s2
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, s1
; RV32I-NEXT: mv a5, s0
; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@ -945,10 +945,10 @@ define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: li a2, 0
@ -956,10 +956,10 @@ define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __muldf3@plt
; RV32I-NEXT: mv a2, s4
; RV32I-NEXT: mv a3, s5
@ -981,16 +981,16 @@ define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __muldf3@plt
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __muldf3@plt
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __subdf3@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@ -1033,22 +1033,15 @@ define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a5
; RV32I-NEXT: mv s3, a4
; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: li a2, 0
@ -1056,15 +1049,22 @@ define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s5
; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s3
; RV32I-NEXT: call __muldf3@plt
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s3
; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: call __subdf3@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@ -1078,26 +1078,25 @@ define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
;
; RV64I-LABEL: fnmadd_d_contract:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call __muldf3@plt
; RV64I-NEXT: li a1, -1
@ -1105,12 +1104,11 @@ define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __subdf3@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%a_ = fadd double 0.0, %a ; avoid negation using xor
%b_ = fadd double 0.0, %b ; avoid negation using xor
@ -1148,29 +1146,29 @@ define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a5
; RV32I-NEXT: mv s3, a4
; RV32I-NEXT: mv s4, a3
; RV32I-NEXT: mv s5, a2
; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv a0, s5
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s5
; RV32I-NEXT: call __muldf3@plt
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __subdf3@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@ -1189,19 +1187,19 @@ define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __muldf3@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __subdf3@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload

186
llvm/test/CodeGen/RISCV/double-convert.ll
View File

@ -137,15 +137,15 @@ define i32 @fcvt_w_d_sat(double %a) nounwind {
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 794112
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixdfsi@plt
; RV32I-NEXT: lui s5, 524288
; RV32I-NEXT: lui s4, 524288
@ -156,17 +156,17 @@ define i32 @fcvt_w_d_sat(double %a) nounwind {
; RV32I-NEXT: lui a0, 269824
; RV32I-NEXT: addi a3, a0, -1
; RV32I-NEXT: lui a2, 1047552
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: bge s0, a0, .LBB3_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: addi s4, s5, -1
; RV32I-NEXT: .LBB3_4: # %start
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: bne a0, s0, .LBB3_6
; RV32I-NEXT: # %bb.5: # %start
@ -363,20 +363,20 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a0, 270080
; RV32I-NEXT: addi a3, a0, -1
; RV32I-NEXT: lui a2, 1048064
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixunsdfsi@plt
; RV32I-NEXT: li a1, 0
@ -385,7 +385,7 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind {
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: .LBB6_2: # %start
; RV32I-NEXT: li a0, -1
; RV32I-NEXT: bgtz s2, .LBB6_4
; RV32I-NEXT: bgtz s0, .LBB6_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB6_4: # %start
@ -694,7 +694,7 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 278016
; RV32I-NEXT: addi s3, a0, -1
@ -704,67 +704,67 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: lui a3, 802304
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __fixdfdi@plt
; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: blt s6, s0, .LBB12_2
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: blt s6, s2, .LBB12_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: .LBB12_2: # %start
; RV32I-NEXT: li s6, -1
; RV32I-NEXT: blt s0, s4, .LBB12_4
; RV32I-NEXT: blt s2, s4, .LBB12_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s6, a1
; RV32I-NEXT: .LBB12_4: # %start
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: mv s4, s0
; RV32I-NEXT: bne a0, s0, .LBB12_6
; RV32I-NEXT: mv s4, s2
; RV32I-NEXT: bne a0, s2, .LBB12_6
; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s4, s6
; RV32I-NEXT: .LBB12_6: # %start
; RV32I-NEXT: lui a3, 802304
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: lui s7, 524288
; RV32I-NEXT: lui s6, 524288
; RV32I-NEXT: blt a0, s0, .LBB12_8
; RV32I-NEXT: blt a0, s2, .LBB12_8
; RV32I-NEXT: # %bb.7: # %start
; RV32I-NEXT: mv s6, s5
; RV32I-NEXT: .LBB12_8: # %start
; RV32I-NEXT: li a2, -1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a3, s3
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: bge s0, a0, .LBB12_10
; RV32I-NEXT: bge s2, a0, .LBB12_10
; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: addi s6, s7, -1
; RV32I-NEXT: .LBB12_10: # %start
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: bne a0, s0, .LBB12_12
; RV32I-NEXT: bne a0, s2, .LBB12_12
; RV32I-NEXT: # %bb.11: # %start
; RV32I-NEXT: mv s0, s6
; RV32I-NEXT: mv s2, s6
; RV32I-NEXT: .LBB12_12: # %start
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
@ -936,22 +936,22 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a0, 278272
; RV32I-NEXT: addi s3, a0, -1
; RV32I-NEXT: li a2, -1
; RV32I-NEXT: li s2, -1
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li s0, -1
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a3, s3
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixunsdfdi@plt
; RV32I-NEXT: mv s5, a1
@ -966,12 +966,12 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
; RV32I-NEXT: mv s4, a1
; RV32I-NEXT: .LBB14_4: # %start
; RV32I-NEXT: li a2, -1
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a3, s3
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
@ -983,10 +983,10 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
; RV32I-NEXT: .LBB14_6: # %start
; RV32I-NEXT: bgtz s3, .LBB14_8
; RV32I-NEXT: # %bb.7: # %start
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: .LBB14_8: # %start
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
@ -1515,15 +1515,15 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 790016
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixdfsi@plt
; RV32I-NEXT: lui s4, 1048568
; RV32I-NEXT: blt s3, s0, .LBB26_2
@ -1532,8 +1532,8 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV32I-NEXT: .LBB26_2: # %start
; RV32I-NEXT: lui a0, 265728
; RV32I-NEXT: addi a3, a0, -64
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: bge s0, a0, .LBB26_4
@ -1541,10 +1541,10 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV32I-NEXT: lui a0, 8
; RV32I-NEXT: addi s4, a0, -1
; RV32I-NEXT: .LBB26_4: # %start
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: bne a0, s0, .LBB26_6
; RV32I-NEXT: # %bb.5: # %start
@ -1574,12 +1574,12 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV64I-NEXT: slli a1, a0, 53
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gedf2@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixdfdi@plt
; RV64I-NEXT: li s1, 0
; RV64I-NEXT: li s2, 0
; RV64I-NEXT: lui s3, 1048568
; RV64I-NEXT: bltz s2, .LBB26_2
; RV64I-NEXT: bltz s1, .LBB26_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB26_2: # %start
@ -1588,7 +1588,7 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV64I-NEXT: slli a1, a0, 38
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: bge s1, a0, .LBB26_4
; RV64I-NEXT: bge s2, a0, .LBB26_4
; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: lui a0, 8
; RV64I-NEXT: addiw s3, a0, -1
@ -1596,11 +1596,11 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: bne a0, s1, .LBB26_6
; RV64I-NEXT: bne a0, s2, .LBB26_6
; RV64I-NEXT: # %bb.5: # %start
; RV64I-NEXT: mv s1, s3
; RV64I-NEXT: mv s2, s3
; RV64I-NEXT: .LBB26_6: # %start
; RV64I-NEXT: slli a0, s1, 48
; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
@ -1677,20 +1677,20 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a0, 265984
; RV32I-NEXT: addi a3, a0, -32
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixunsdfsi@plt
; RV32I-NEXT: li a1, 0
@ -1701,7 +1701,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind {
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: bgtz s2, .LBB28_4
; RV32I-NEXT: bgtz s0, .LBB28_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: .LBB28_4: # %start
@ -1833,15 +1833,15 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 787968
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixdfsi@plt
; RV32I-NEXT: li s4, -128
; RV32I-NEXT: blt s3, s0, .LBB30_2
@ -1849,8 +1849,8 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: .LBB30_2: # %start
; RV32I-NEXT: lui a3, 263676
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: li s3, 127
@ -1858,10 +1858,10 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s3, s4
; RV32I-NEXT: .LBB30_4: # %start
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: bne a0, s0, .LBB30_6
; RV32I-NEXT: # %bb.5: # %start
@ -1891,12 +1891,12 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV64I-NEXT: slli a1, a0, 53
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gedf2@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixdfdi@plt
; RV64I-NEXT: li s1, 0
; RV64I-NEXT: li s2, 0
; RV64I-NEXT: li s3, -128
; RV64I-NEXT: bltz s2, .LBB30_2
; RV64I-NEXT: bltz s1, .LBB30_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB30_2: # %start
@ -1904,19 +1904,19 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV64I-NEXT: slli a1, a0, 34
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: li s2, 127
; RV64I-NEXT: blt s1, a0, .LBB30_4
; RV64I-NEXT: li s1, 127
; RV64I-NEXT: blt s2, a0, .LBB30_4
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: mv s2, s3
; RV64I-NEXT: mv s1, s3
; RV64I-NEXT: .LBB30_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: bne a0, s1, .LBB30_6
; RV64I-NEXT: bne a0, s2, .LBB30_6
; RV64I-NEXT: # %bb.5: # %start
; RV64I-NEXT: mv s1, s2
; RV64I-NEXT: mv s2, s1
; RV64I-NEXT: .LBB30_6: # %start
; RV64I-NEXT: slli a0, s1, 56
; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
@ -1997,18 +1997,18 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 263934
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixunsdfsi@plt
; RV32I-NEXT: li a1, 0
@ -2017,7 +2017,7 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: .LBB32_2: # %start
; RV32I-NEXT: li a0, 255
; RV32I-NEXT: bgtz s2, .LBB32_4
; RV32I-NEXT: bgtz s0, .LBB32_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB32_4: # %start

64
llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
View File

@ -250,16 +250,16 @@ define i32 @fcmp_one(double %a, double %b) nounwind strictfp {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: snez s4, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: and a0, a0, s4
@ -378,16 +378,16 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: seqz s4, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: or a0, a0, s4
@ -885,16 +885,16 @@ define i32 @fcmps_one(double %a, double %b) nounwind strictfp {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: snez s4, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: and a0, a0, s4
@ -999,16 +999,16 @@ define i32 @fcmps_ueq(double %a, double %b) nounwind strictfp {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: seqz s4, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: or a0, a0, s4

32
llvm/test/CodeGen/RISCV/double-fcmp.ll
View File

@ -234,16 +234,16 @@ define i32 @fcmp_one(double %a, double %b) nounwind {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: snez s4, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: and a0, a0, s4
@ -348,16 +348,16 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: seqz s4, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: or a0, a0, s4

32
llvm/test/CodeGen/RISCV/float-arith-strict.ll
View File

@ -379,18 +379,18 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp {
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, s1, a2
; RV32I-NEXT: xor a1, s2, a2
; RV32I-NEXT: xor a2, a0, a2
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@ -407,18 +407,18 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: xor a1, s1, a2
; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@ -459,18 +459,18 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp {
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, s1, a2
; RV32I-NEXT: xor a1, s2, a2
; RV32I-NEXT: xor a2, a0, a2
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@ -487,18 +487,18 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: xor a1, s1, a2
; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload

124
llvm/test/CodeGen/RISCV/float-arith.ll
View File

@ -557,18 +557,18 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, s1, a2
; RV32I-NEXT: xor a1, s2, a2
; RV32I-NEXT: xor a2, a0, a2
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@ -585,18 +585,18 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: xor a1, s1, a2
; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@ -637,18 +637,18 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, s1, a2
; RV32I-NEXT: xor a1, s2, a2
; RV32I-NEXT: xor a2, a0, a2
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@ -665,18 +665,18 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: xor a1, s1, a2
; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@ -883,16 +883,16 @@ define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __subsf3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@ -908,16 +908,16 @@ define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@ -952,74 +952,70 @@ define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
;
; RV32I-LABEL: fnmadd_s_contract:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a2
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __subsf3@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: fnmadd_s_contract:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a ; avoid negation using xor
%b_ = fadd float 0.0, %b ; avoid negation using xor
@ -1054,19 +1050,19 @@ define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a2
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __subsf3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@ -1082,19 +1078,19 @@ define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload

88
llvm/test/CodeGen/RISCV/float-convert.ll
View File

@ -903,25 +903,25 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixunssfdi@plt
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: li s5, 0
; RV32I-NEXT: bltz s1, .LBB14_2
; RV32I-NEXT: bltz s2, .LBB14_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: .LBB14_2: # %start
; RV32I-NEXT: lui a0, 391168
; RV32I-NEXT: addi s1, a0, -1
; RV32I-NEXT: addi s4, a0, -1
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: li s2, -1
; RV32I-NEXT: li s3, -1
; RV32I-NEXT: li s4, -1
; RV32I-NEXT: bgtz a0, .LBB14_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s4, s5
; RV32I-NEXT: mv s3, s5
; RV32I-NEXT: .LBB14_4: # %start
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0
@ -929,17 +929,17 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV32I-NEXT: li s5, 0
; RV32I-NEXT: bltz a0, .LBB14_6
; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s5, s2
; RV32I-NEXT: mv s5, s1
; RV32I-NEXT: .LBB14_6: # %start
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: bgtz a0, .LBB14_8
; RV32I-NEXT: # %bb.7: # %start
; RV32I-NEXT: mv s3, s5
; RV32I-NEXT: mv s2, s5
; RV32I-NEXT: .LBB14_8: # %start
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
@ -1382,12 +1382,12 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a1, 815104
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfsi@plt
; RV32I-NEXT: li s1, 0
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: lui s3, 1048568
; RV32I-NEXT: bltz s2, .LBB24_2
; RV32I-NEXT: bltz s1, .LBB24_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: .LBB24_2: # %start
@ -1395,7 +1395,7 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV32I-NEXT: addi a1, a0, -512
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: bge s1, a0, .LBB24_4
; RV32I-NEXT: bge s2, a0, .LBB24_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: lui a0, 8
; RV32I-NEXT: addi s3, a0, -1
@ -1403,11 +1403,11 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: bne a0, s1, .LBB24_6
; RV32I-NEXT: bne a0, s2, .LBB24_6
; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s1, s3
; RV32I-NEXT: mv s2, s3
; RV32I-NEXT: .LBB24_6: # %start
; RV32I-NEXT: slli a0, s1, 16
; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@ -1428,12 +1428,12 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 815104
; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: li s1, 0
; RV64I-NEXT: li s2, 0
; RV64I-NEXT: lui s3, 1048568
; RV64I-NEXT: bltz s2, .LBB24_2
; RV64I-NEXT: bltz s1, .LBB24_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB24_2: # %start
@ -1441,7 +1441,7 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV64I-NEXT: addiw a1, a0, -512
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: bge s1, a0, .LBB24_4
; RV64I-NEXT: bge s2, a0, .LBB24_4
; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: lui a0, 8
; RV64I-NEXT: addiw s3, a0, -1
@ -1449,11 +1449,11 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: bne a0, s1, .LBB24_6
; RV64I-NEXT: bne a0, s2, .LBB24_6
; RV64I-NEXT: # %bb.5: # %start
; RV64I-NEXT: mv s1, s3
; RV64I-NEXT: mv s2, s3
; RV64I-NEXT: .LBB24_6: # %start
; RV64I-NEXT: slli a0, s1, 48
; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
@ -1678,31 +1678,31 @@ define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a1, 798720
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfsi@plt
; RV32I-NEXT: li s1, 0
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: li s3, -128
; RV32I-NEXT: bltz s2, .LBB28_2
; RV32I-NEXT: bltz s1, .LBB28_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: .LBB28_2: # %start
; RV32I-NEXT: lui a1, 274400
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: li s2, 127
; RV32I-NEXT: blt s1, a0, .LBB28_4
; RV32I-NEXT: li s1, 127
; RV32I-NEXT: blt s2, a0, .LBB28_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s2, s3
; RV32I-NEXT: mv s1, s3
; RV32I-NEXT: .LBB28_4: # %start
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: bne a0, s1, .LBB28_6
; RV32I-NEXT: bne a0, s2, .LBB28_6
; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s1, s2
; RV32I-NEXT: mv s2, s1
; RV32I-NEXT: .LBB28_6: # %start
; RV32I-NEXT: slli a0, s1, 24
; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@ -1723,31 +1723,31 @@ define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 798720
; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: li s1, 0
; RV64I-NEXT: li s2, 0
; RV64I-NEXT: li s3, -128
; RV64I-NEXT: bltz s2, .LBB28_2
; RV64I-NEXT: bltz s1, .LBB28_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB28_2: # %start
; RV64I-NEXT: lui a1, 274400
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: li s2, 127
; RV64I-NEXT: blt s1, a0, .LBB28_4
; RV64I-NEXT: li s1, 127
; RV64I-NEXT: blt s2, a0, .LBB28_4
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: mv s2, s3
; RV64I-NEXT: mv s1, s3
; RV64I-NEXT: .LBB28_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: bne a0, s1, .LBB28_6
; RV64I-NEXT: bne a0, s2, .LBB28_6
; RV64I-NEXT: # %bb.5: # %start
; RV64I-NEXT: mv s1, s2
; RV64I-NEXT: mv s2, s1
; RV64I-NEXT: .LBB28_6: # %start
; RV64I-NEXT: slli a0, s1, 56
; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload

32
llvm/test/CodeGen/RISCV/fp128.ll
View File

@ -14,25 +14,25 @@ define i32 @test_load_and_cmp() nounwind {
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: lw a6, %lo(x)(a0)
; RV32I-NEXT: lw a7, %lo(x+4)(a0)
; RV32I-NEXT: lw a2, %lo(x)(a0)
; RV32I-NEXT: lw a1, %lo(x+4)(a0)
; RV32I-NEXT: lw a3, %lo(x+8)(a0)
; RV32I-NEXT: lw a0, %lo(x+12)(a0)
; RV32I-NEXT: lui a4, %hi(y)
; RV32I-NEXT: lw a5, %lo(y)(a4)
; RV32I-NEXT: lw a2, %lo(y+4)(a4)
; RV32I-NEXT: lw a1, %lo(y+8)(a4)
; RV32I-NEXT: lw a6, %lo(y+4)(a4)
; RV32I-NEXT: lw a7, %lo(y+8)(a4)
; RV32I-NEXT: lw a4, %lo(y+12)(a4)
; RV32I-NEXT: sw a4, 20(sp)
; RV32I-NEXT: sw a1, 16(sp)
; RV32I-NEXT: sw a2, 12(sp)
; RV32I-NEXT: sw a7, 16(sp)
; RV32I-NEXT: sw a6, 12(sp)
; RV32I-NEXT: sw a5, 8(sp)
; RV32I-NEXT: sw a0, 36(sp)
; RV32I-NEXT: sw a3, 32(sp)
; RV32I-NEXT: sw a7, 28(sp)
; RV32I-NEXT: sw a1, 28(sp)
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a6, 24(sp)
; RV32I-NEXT: sw a2, 24(sp)
; RV32I-NEXT: call __netf2@plt
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
@ -51,26 +51,26 @@ define i32 @test_add_and_fptosi() nounwind {
; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: lw a6, %lo(x)(a0)
; RV32I-NEXT: lw a7, %lo(x+4)(a0)
; RV32I-NEXT: lw a3, %lo(x)(a0)
; RV32I-NEXT: lw a1, %lo(x+4)(a0)
; RV32I-NEXT: lw a2, %lo(x+8)(a0)
; RV32I-NEXT: lw a0, %lo(x+12)(a0)
; RV32I-NEXT: lui a4, %hi(y)
; RV32I-NEXT: lw a5, %lo(y)(a4)
; RV32I-NEXT: lw a3, %lo(y+4)(a4)
; RV32I-NEXT: lw a1, %lo(y+8)(a4)
; RV32I-NEXT: lw a6, %lo(y+4)(a4)
; RV32I-NEXT: lw a7, %lo(y+8)(a4)
; RV32I-NEXT: lw a4, %lo(y+12)(a4)
; RV32I-NEXT: sw a4, 36(sp)
; RV32I-NEXT: sw a1, 32(sp)
; RV32I-NEXT: sw a3, 28(sp)
; RV32I-NEXT: sw a7, 32(sp)
; RV32I-NEXT: sw a6, 28(sp)
; RV32I-NEXT: sw a5, 24(sp)
; RV32I-NEXT: sw a0, 52(sp)
; RV32I-NEXT: sw a2, 48(sp)
; RV32I-NEXT: sw a7, 44(sp)
; RV32I-NEXT: sw a1, 44(sp)
; RV32I-NEXT: addi a0, sp, 56
; RV32I-NEXT: addi a1, sp, 40
; RV32I-NEXT: addi a2, sp, 24
; RV32I-NEXT: sw a6, 40(sp)
; RV32I-NEXT: sw a3, 40(sp)
; RV32I-NEXT: call __addtf3@plt
; RV32I-NEXT: lw a1, 56(sp)
; RV32I-NEXT: lw a0, 60(sp)

414
llvm/test/CodeGen/RISCV/fpclamptosat.ll
View File

@ -1159,43 +1159,43 @@ define i64 @stest_f64i64(double %x) {
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: call __fixdfti@plt
; RV32-NEXT: lw a2, 20(sp)
; RV32-NEXT: lw t0, 16(sp)
; RV32-NEXT: lw a3, 16(sp)
; RV32-NEXT: lw a1, 12(sp)
; RV32-NEXT: lw a0, 8(sp)
; RV32-NEXT: lui a7, 524288
; RV32-NEXT: addi a5, a7, -1
; RV32-NEXT: lui a4, 524288
; RV32-NEXT: addi a5, a4, -1
; RV32-NEXT: beq a1, a5, .LBB18_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a4, a1, a5
; RV32-NEXT: or a3, t0, a2
; RV32-NEXT: bnez a3, .LBB18_3
; RV32-NEXT: sltu a7, a1, a5
; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: bnez a6, .LBB18_3
; RV32-NEXT: j .LBB18_4
; RV32-NEXT: .LBB18_2:
; RV32-NEXT: addi a4, a0, 1
; RV32-NEXT: snez a4, a4
; RV32-NEXT: or a3, t0, a2
; RV32-NEXT: beqz a3, .LBB18_4
; RV32-NEXT: addi a6, a0, 1
; RV32-NEXT: snez a7, a6
; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: beqz a6, .LBB18_4
; RV32-NEXT: .LBB18_3: # %entry
; RV32-NEXT: slti a4, a2, 0
; RV32-NEXT: slti a7, a2, 0
; RV32-NEXT: .LBB18_4: # %entry
; RV32-NEXT: li a6, -1
; RV32-NEXT: beqz a4, .LBB18_7
; RV32-NEXT: beqz a7, .LBB18_7
; RV32-NEXT: # %bb.5: # %entry
; RV32-NEXT: beq a1, a7, .LBB18_8
; RV32-NEXT: beq a1, a4, .LBB18_8
; RV32-NEXT: .LBB18_6: # %entry
; RV32-NEXT: sltu a4, a7, a1
; RV32-NEXT: and a3, t0, a2
; RV32-NEXT: sltu a4, a4, a1
; RV32-NEXT: and a3, a3, a2
; RV32-NEXT: bne a3, a6, .LBB18_9
; RV32-NEXT: j .LBB18_10
; RV32-NEXT: .LBB18_7: # %entry
; RV32-NEXT: li a2, 0
; RV32-NEXT: li t0, 0
; RV32-NEXT: li a3, 0
; RV32-NEXT: li a0, -1
; RV32-NEXT: mv a1, a5
; RV32-NEXT: bne a1, a7, .LBB18_6
; RV32-NEXT: bne a1, a4, .LBB18_6
; RV32-NEXT: .LBB18_8:
; RV32-NEXT: snez a4, a0
; RV32-NEXT: and a3, t0, a2
; RV32-NEXT: and a3, a3, a2
; RV32-NEXT: beq a3, a6, .LBB18_10
; RV32-NEXT: .LBB18_9: # %entry
; RV32-NEXT: slt a4, a6, a2
@ -1441,43 +1441,43 @@ define i64 @stest_f32i64(float %x) {
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: call __fixsfti@plt
; RV32-NEXT: lw a2, 20(sp)
; RV32-NEXT: lw t0, 16(sp)
; RV32-NEXT: lw a3, 16(sp)
; RV32-NEXT: lw a1, 12(sp)
; RV32-NEXT: lw a0, 8(sp)
; RV32-NEXT: lui a7, 524288
; RV32-NEXT: addi a5, a7, -1
; RV32-NEXT: lui a4, 524288
; RV32-NEXT: addi a5, a4, -1
; RV32-NEXT: beq a1, a5, .LBB21_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a4, a1, a5
; RV32-NEXT: or a3, t0, a2
; RV32-NEXT: bnez a3, .LBB21_3
; RV32-NEXT: sltu a7, a1, a5
; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: bnez a6, .LBB21_3
; RV32-NEXT: j .LBB21_4
; RV32-NEXT: .LBB21_2:
; RV32-NEXT: addi a4, a0, 1
; RV32-NEXT: snez a4, a4
; RV32-NEXT: or a3, t0, a2
; RV32-NEXT: beqz a3, .LBB21_4
; RV32-NEXT: addi a6, a0, 1
; RV32-NEXT: snez a7, a6
; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: beqz a6, .LBB21_4
; RV32-NEXT: .LBB21_3: # %entry
; RV32-NEXT: slti a4, a2, 0
; RV32-NEXT: slti a7, a2, 0
; RV32-NEXT: .LBB21_4: # %entry
; RV32-NEXT: li a6, -1
; RV32-NEXT: beqz a4, .LBB21_7
; RV32-NEXT: beqz a7, .LBB21_7
; RV32-NEXT: # %bb.5: # %entry
; RV32-NEXT: beq a1, a7, .LBB21_8
; RV32-NEXT: beq a1, a4, .LBB21_8
; RV32-NEXT: .LBB21_6: # %entry
; RV32-NEXT: sltu a4, a7, a1
; RV32-NEXT: and a3, t0, a2
; RV32-NEXT: sltu a4, a4, a1
; RV32-NEXT: and a3, a3, a2
; RV32-NEXT: bne a3, a6, .LBB21_9
; RV32-NEXT: j .LBB21_10
; RV32-NEXT: .LBB21_7: # %entry
; RV32-NEXT: li a2, 0
; RV32-NEXT: li t0, 0
; RV32-NEXT: li a3, 0
; RV32-NEXT: li a0, -1
; RV32-NEXT: mv a1, a5
; RV32-NEXT: bne a1, a7, .LBB21_6
; RV32-NEXT: bne a1, a4, .LBB21_6
; RV32-NEXT: .LBB21_8:
; RV32-NEXT: snez a4, a0
; RV32-NEXT: and a3, t0, a2
; RV32-NEXT: and a3, a3, a2
; RV32-NEXT: beq a3, a6, .LBB21_10
; RV32-NEXT: .LBB21_9: # %entry
; RV32-NEXT: slt a4, a6, a2
@ -1685,43 +1685,43 @@ define i64 @stest_f16i64(half %x) {
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: call __fixsfti@plt
; RV32-NEXT: lw a2, 20(sp)
; RV32-NEXT: lw t0, 16(sp)
; RV32-NEXT: lw a3, 16(sp)
; RV32-NEXT: lw a1, 12(sp)
; RV32-NEXT: lw a0, 8(sp)
; RV32-NEXT: lui a7, 524288
; RV32-NEXT: addi a5, a7, -1
; RV32-NEXT: lui a4, 524288
; RV32-NEXT: addi a5, a4, -1
; RV32-NEXT: beq a1, a5, .LBB24_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a4, a1, a5
; RV32-NEXT: or a3, t0, a2
; RV32-NEXT: bnez a3, .LBB24_3
; RV32-NEXT: sltu a7, a1, a5
; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: bnez a6, .LBB24_3
; RV32-NEXT: j .LBB24_4
; RV32-NEXT: .LBB24_2:
; RV32-NEXT: addi a4, a0, 1
; RV32-NEXT: snez a4, a4
; RV32-NEXT: or a3, t0, a2
; RV32-NEXT: beqz a3, .LBB24_4
; RV32-NEXT: addi a6, a0, 1
; RV32-NEXT: snez a7, a6
; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: beqz a6, .LBB24_4
; RV32-NEXT: .LBB24_3: # %entry
; RV32-NEXT: slti a4, a2, 0
; RV32-NEXT: slti a7, a2, 0
; RV32-NEXT: .LBB24_4: # %entry
; RV32-NEXT: li a6, -1
; RV32-NEXT: beqz a4, .LBB24_7
; RV32-NEXT: beqz a7, .LBB24_7
; RV32-NEXT: # %bb.5: # %entry
; RV32-NEXT: beq a1, a7, .LBB24_8
; RV32-NEXT: beq a1, a4, .LBB24_8
; RV32-NEXT: .LBB24_6: # %entry
; RV32-NEXT: sltu a4, a7, a1
; RV32-NEXT: and a3, t0, a2
; RV32-NEXT: sltu a4, a4, a1
; RV32-NEXT: and a3, a3, a2
; RV32-NEXT: bne a3, a6, .LBB24_9
; RV32-NEXT: j .LBB24_10
; RV32-NEXT: .LBB24_7: # %entry
; RV32-NEXT: li a2, 0
; RV32-NEXT: li t0, 0
; RV32-NEXT: li a3, 0
; RV32-NEXT: li a0, -1
; RV32-NEXT: mv a1, a5
; RV32-NEXT: bne a1, a7, .LBB24_6
; RV32-NEXT: bne a1, a4, .LBB24_6
; RV32-NEXT: .LBB24_8:
; RV32-NEXT: snez a4, a0
; RV32-NEXT: and a3, t0, a2
; RV32-NEXT: and a3, a3, a2
; RV32-NEXT: beq a3, a6, .LBB24_10
; RV32-NEXT: .LBB24_9: # %entry
; RV32-NEXT: slt a4, a6, a2
@ -3090,109 +3090,109 @@ define i64 @stest_f64i64_mm(double %x) {
; RV32-NEXT: lw a5, 8(sp)
; RV32-NEXT: lw a3, 20(sp)
; RV32-NEXT: lw a1, 12(sp)
; RV32-NEXT: li a6, -1
; RV32-NEXT: mv a4, a5
; RV32-NEXT: li a2, -1
; RV32-NEXT: mv a7, a5
; RV32-NEXT: bltz a3, .LBB45_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: li a4, -1
; RV32-NEXT: li a7, -1
; RV32-NEXT: .LBB45_2: # %entry
; RV32-NEXT: lui a7, 524288
; RV32-NEXT: addi a2, a7, -1
; RV32-NEXT: mv a0, a5
; RV32-NEXT: bgeu a1, a2, .LBB45_19
; RV32-NEXT: lui a4, 524288
; RV32-NEXT: addi a6, a4, -1
; RV32-NEXT: mv t0, a5
; RV32-NEXT: bgeu a1, a6, .LBB45_19
; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: lw t0, 16(sp)
; RV32-NEXT: bne a1, a2, .LBB45_20
; RV32-NEXT: lw a0, 16(sp)
; RV32-NEXT: bne a1, a6, .LBB45_20
; RV32-NEXT: .LBB45_4: # %entry
; RV32-NEXT: or a0, t0, a3
; RV32-NEXT: bnez a0, .LBB45_21
; RV32-NEXT: or t0, a0, a3
; RV32-NEXT: bnez t0, .LBB45_21
; RV32-NEXT: .LBB45_5: # %entry
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a7, a1
; RV32-NEXT: bgez a3, .LBB45_22
; RV32-NEXT: .LBB45_6: # %entry
; RV32-NEXT: bgeu a1, a2, .LBB45_23
; RV32-NEXT: bgeu a1, a6, .LBB45_23
; RV32-NEXT: .LBB45_7: # %entry
; RV32-NEXT: bnez a0, .LBB45_24
; RV32-NEXT: bnez t0, .LBB45_24
; RV32-NEXT: .LBB45_8: # %entry
; RV32-NEXT: li a2, 0
; RV32-NEXT: li a6, 0
; RV32-NEXT: bnez a3, .LBB45_25
; RV32-NEXT: .LBB45_9: # %entry
; RV32-NEXT: bgez a3, .LBB45_26
; RV32-NEXT: .LBB45_10: # %entry
; RV32-NEXT: mv a4, a5
; RV32-NEXT: bgeu a7, a1, .LBB45_27
; RV32-NEXT: mv a7, a5
; RV32-NEXT: bgeu a4, a1, .LBB45_27
; RV32-NEXT: .LBB45_11: # %entry
; RV32-NEXT: mv a0, a5
; RV32-NEXT: bne a1, a7, .LBB45_28
; RV32-NEXT: bne a1, a4, .LBB45_28
; RV32-NEXT: .LBB45_12: # %entry
; RV32-NEXT: bltz a3, .LBB45_29
; RV32-NEXT: .LBB45_13: # %entry
; RV32-NEXT: and a2, a2, a3
; RV32-NEXT: bne a2, a6, .LBB45_30
; RV32-NEXT: and a6, a6, a3
; RV32-NEXT: bne a6, a2, .LBB45_30
; RV32-NEXT: .LBB45_14: # %entry
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a5, a1
; RV32-NEXT: bltz a3, .LBB45_31
; RV32-NEXT: .LBB45_15: # %entry
; RV32-NEXT: bgeu a7, a1, .LBB45_32
; RV32-NEXT: bgeu a4, a1, .LBB45_32
; RV32-NEXT: .LBB45_16: # %entry
; RV32-NEXT: beq a2, a6, .LBB45_18
; RV32-NEXT: beq a6, a2, .LBB45_18
; RV32-NEXT: .LBB45_17: # %entry
; RV32-NEXT: mv a1, a4
; RV32-NEXT: mv a1, a5
; RV32-NEXT: .LBB45_18: # %entry
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret
; RV32-NEXT: .LBB45_19: # %entry
; RV32-NEXT: li a0, -1
; RV32-NEXT: lw t0, 16(sp)
; RV32-NEXT: beq a1, a2, .LBB45_4
; RV32-NEXT: li t0, -1
; RV32-NEXT: lw a0, 16(sp)
; RV32-NEXT: beq a1, a6, .LBB45_4
; RV32-NEXT: .LBB45_20: # %entry
; RV32-NEXT: mv a5, a0
; RV32-NEXT: or a0, t0, a3
; RV32-NEXT: beqz a0, .LBB45_5
; RV32-NEXT: mv a5, t0
; RV32-NEXT: or t0, a0, a3
; RV32-NEXT: beqz t0, .LBB45_5
; RV32-NEXT: .LBB45_21: # %entry
; RV32-NEXT: mv a5, a4
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a5, a7
; RV32-NEXT: mv a7, a1
; RV32-NEXT: bltz a3, .LBB45_6
; RV32-NEXT: .LBB45_22: # %entry
; RV32-NEXT: mv a4, a2
; RV32-NEXT: bltu a1, a2, .LBB45_7
; RV32-NEXT: mv a7, a6
; RV32-NEXT: bltu a1, a6, .LBB45_7
; RV32-NEXT: .LBB45_23: # %entry
; RV32-NEXT: mv a1, a2
; RV32-NEXT: beqz a0, .LBB45_8
; RV32-NEXT: mv a1, a6
; RV32-NEXT: beqz t0, .LBB45_8
; RV32-NEXT: .LBB45_24: # %entry
; RV32-NEXT: mv a1, a4
; RV32-NEXT: li a2, 0
; RV32-NEXT: mv a1, a7
; RV32-NEXT: li a6, 0
; RV32-NEXT: beqz a3, .LBB45_9
; RV32-NEXT: .LBB45_25: # %entry
; RV32-NEXT: srai a0, a3, 31
; RV32-NEXT: and a2, a0, t0
; RV32-NEXT: srai a6, a3, 31
; RV32-NEXT: and a6, a6, a0
; RV32-NEXT: bltz a3, .LBB45_10
; RV32-NEXT: .LBB45_26: # %entry
; RV32-NEXT: li a3, 0
; RV32-NEXT: mv a4, a5
; RV32-NEXT: bltu a7, a1, .LBB45_11
; RV32-NEXT: mv a7, a5
; RV32-NEXT: bltu a4, a1, .LBB45_11
; RV32-NEXT: .LBB45_27: # %entry
; RV32-NEXT: li a4, 0
; RV32-NEXT: li a7, 0
; RV32-NEXT: mv a0, a5
; RV32-NEXT: beq a1, a7, .LBB45_12
; RV32-NEXT: beq a1, a4, .LBB45_12
; RV32-NEXT: .LBB45_28: # %entry
; RV32-NEXT: mv a0, a4
; RV32-NEXT: mv a0, a7
; RV32-NEXT: bgez a3, .LBB45_13
; RV32-NEXT: .LBB45_29: # %entry
; RV32-NEXT: li a5, 0
; RV32-NEXT: and a2, a2, a3
; RV32-NEXT: beq a2, a6, .LBB45_14
; RV32-NEXT: and a6, a6, a3
; RV32-NEXT: beq a6, a2, .LBB45_14
; RV32-NEXT: .LBB45_30: # %entry
; RV32-NEXT: mv a0, a5
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a5, a1
; RV32-NEXT: bgez a3, .LBB45_15
; RV32-NEXT: .LBB45_31: # %entry
; RV32-NEXT: lui a4, 524288
; RV32-NEXT: bltu a7, a1, .LBB45_16
; RV32-NEXT: lui a5, 524288
; RV32-NEXT: bltu a4, a1, .LBB45_16
; RV32-NEXT: .LBB45_32: # %entry
; RV32-NEXT: lui a1, 524288
; RV32-NEXT: bne a2, a6, .LBB45_17
; RV32-NEXT: bne a6, a2, .LBB45_17
; RV32-NEXT: j .LBB45_18
;
; RV64IF-LABEL: stest_f64i64_mm:
@ -3514,109 +3514,109 @@ define i64 @stest_f32i64_mm(float %x) {
; RV32-NEXT: lw a5, 8(sp)
; RV32-NEXT: lw a3, 20(sp)
; RV32-NEXT: lw a1, 12(sp)
; RV32-NEXT: li a6, -1
; RV32-NEXT: mv a4, a5
; RV32-NEXT: li a2, -1
; RV32-NEXT: mv a7, a5
; RV32-NEXT: bltz a3, .LBB48_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: li a4, -1
; RV32-NEXT: li a7, -1
; RV32-NEXT: .LBB48_2: # %entry
; RV32-NEXT: lui a7, 524288
; RV32-NEXT: addi a2, a7, -1
; RV32-NEXT: mv a0, a5
; RV32-NEXT: bgeu a1, a2, .LBB48_19
; RV32-NEXT: lui a4, 524288
; RV32-NEXT: addi a6, a4, -1
; RV32-NEXT: mv t0, a5
; RV32-NEXT: bgeu a1, a6, .LBB48_19
; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: lw t0, 16(sp)
; RV32-NEXT: bne a1, a2, .LBB48_20
; RV32-NEXT: lw a0, 16(sp)
; RV32-NEXT: bne a1, a6, .LBB48_20
; RV32-NEXT: .LBB48_4: # %entry
; RV32-NEXT: or a0, t0, a3
; RV32-NEXT: bnez a0, .LBB48_21
; RV32-NEXT: or t0, a0, a3
; RV32-NEXT: bnez t0, .LBB48_21
; RV32-NEXT: .LBB48_5: # %entry
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a7, a1
; RV32-NEXT: bgez a3, .LBB48_22
; RV32-NEXT: .LBB48_6: # %entry
; RV32-NEXT: bgeu a1, a2, .LBB48_23
; RV32-NEXT: bgeu a1, a6, .LBB48_23
; RV32-NEXT: .LBB48_7: # %entry
; RV32-NEXT: bnez a0, .LBB48_24
; RV32-NEXT: bnez t0, .LBB48_24
; RV32-NEXT: .LBB48_8: # %entry
; RV32-NEXT: li a2, 0
; RV32-NEXT: li a6, 0
; RV32-NEXT: bnez a3, .LBB48_25
; RV32-NEXT: .LBB48_9: # %entry
; RV32-NEXT: bgez a3, .LBB48_26
; RV32-NEXT: .LBB48_10: # %entry
; RV32-NEXT: mv a4, a5
; RV32-NEXT: bgeu a7, a1, .LBB48_27
; RV32-NEXT: mv a7, a5
; RV32-NEXT: bgeu a4, a1, .LBB48_27
; RV32-NEXT: .LBB48_11: # %entry
; RV32-NEXT: mv a0, a5
; RV32-NEXT: bne a1, a7, .LBB48_28
; RV32-NEXT: bne a1, a4, .LBB48_28
; RV32-NEXT: .LBB48_12: # %entry
; RV32-NEXT: bltz a3, .LBB48_29
; RV32-NEXT: .LBB48_13: # %entry
; RV32-NEXT: and a2, a2, a3
; RV32-NEXT: bne a2, a6, .LBB48_30
; RV32-NEXT: and a6, a6, a3
; RV32-NEXT: bne a6, a2, .LBB48_30
; RV32-NEXT: .LBB48_14: # %entry
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a5, a1
; RV32-NEXT: bltz a3, .LBB48_31
; RV32-NEXT: .LBB48_15: # %entry
; RV32-NEXT: bgeu a7, a1, .LBB48_32
; RV32-NEXT: bgeu a4, a1, .LBB48_32
; RV32-NEXT: .LBB48_16: # %entry
; RV32-NEXT: beq a2, a6, .LBB48_18
; RV32-NEXT: beq a6, a2, .LBB48_18
; RV32-NEXT: .LBB48_17: # %entry
; RV32-NEXT: mv a1, a4
; RV32-NEXT: mv a1, a5
; RV32-NEXT: .LBB48_18: # %entry
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret
; RV32-NEXT: .LBB48_19: # %entry
; RV32-NEXT: li a0, -1
; RV32-NEXT: lw t0, 16(sp)
; RV32-NEXT: beq a1, a2, .LBB48_4
; RV32-NEXT: li t0, -1
; RV32-NEXT: lw a0, 16(sp)
; RV32-NEXT: beq a1, a6, .LBB48_4
; RV32-NEXT: .LBB48_20: # %entry
; RV32-NEXT: mv a5, a0
; RV32-NEXT: or a0, t0, a3
; RV32-NEXT: beqz a0, .LBB48_5
; RV32-NEXT: mv a5, t0
; RV32-NEXT: or t0, a0, a3
; RV32-NEXT: beqz t0, .LBB48_5
; RV32-NEXT: .LBB48_21: # %entry
; RV32-NEXT: mv a5, a4
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a5, a7
; RV32-NEXT: mv a7, a1
; RV32-NEXT: bltz a3, .LBB48_6
; RV32-NEXT: .LBB48_22: # %entry
; RV32-NEXT: mv a4, a2
; RV32-NEXT: bltu a1, a2, .LBB48_7
; RV32-NEXT: mv a7, a6
; RV32-NEXT: bltu a1, a6, .LBB48_7
; RV32-NEXT: .LBB48_23: # %entry
; RV32-NEXT: mv a1, a2
; RV32-NEXT: beqz a0, .LBB48_8
; RV32-NEXT: mv a1, a6
; RV32-NEXT: beqz t0, .LBB48_8
; RV32-NEXT: .LBB48_24: # %entry
; RV32-NEXT: mv a1, a4
; RV32-NEXT: li a2, 0
; RV32-NEXT: mv a1, a7
; RV32-NEXT: li a6, 0
; RV32-NEXT: beqz a3, .LBB48_9
; RV32-NEXT: .LBB48_25: # %entry
; RV32-NEXT: srai a0, a3, 31
; RV32-NEXT: and a2, a0, t0
; RV32-NEXT: srai a6, a3, 31
; RV32-NEXT: and a6, a6, a0
; RV32-NEXT: bltz a3, .LBB48_10
; RV32-NEXT: .LBB48_26: # %entry
; RV32-NEXT: li a3, 0
; RV32-NEXT: mv a4, a5
; RV32-NEXT: bltu a7, a1, .LBB48_11
; RV32-NEXT: mv a7, a5
; RV32-NEXT: bltu a4, a1, .LBB48_11
; RV32-NEXT: .LBB48_27: # %entry
; RV32-NEXT: li a4, 0
; RV32-NEXT: li a7, 0
; RV32-NEXT: mv a0, a5
; RV32-NEXT: beq a1, a7, .LBB48_12
; RV32-NEXT: beq a1, a4, .LBB48_12
; RV32-NEXT: .LBB48_28: # %entry
; RV32-NEXT: mv a0, a4
; RV32-NEXT: mv a0, a7
; RV32-NEXT: bgez a3, .LBB48_13
; RV32-NEXT: .LBB48_29: # %entry
; RV32-NEXT: li a5, 0
; RV32-NEXT: and a2, a2, a3
; RV32-NEXT: beq a2, a6, .LBB48_14
; RV32-NEXT: and a6, a6, a3
; RV32-NEXT: beq a6, a2, .LBB48_14
; RV32-NEXT: .LBB48_30: # %entry
; RV32-NEXT: mv a0, a5
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a5, a1
; RV32-NEXT: bgez a3, .LBB48_15
; RV32-NEXT: .LBB48_31: # %entry
; RV32-NEXT: lui a4, 524288
; RV32-NEXT: bltu a7, a1, .LBB48_16
; RV32-NEXT: lui a5, 524288
; RV32-NEXT: bltu a4, a1, .LBB48_16
; RV32-NEXT: .LBB48_32: # %entry
; RV32-NEXT: lui a1, 524288
; RV32-NEXT: bne a2, a6, .LBB48_17
; RV32-NEXT: bne a6, a2, .LBB48_17
; RV32-NEXT: j .LBB48_18
;
; RV64-LABEL: stest_f32i64_mm:
@ -3886,109 +3886,109 @@ define i64 @stest_f16i64_mm(half %x) {
; RV32-NEXT: lw a5, 8(sp)
; RV32-NEXT: lw a3, 20(sp)
; RV32-NEXT: lw a1, 12(sp)
; RV32-NEXT: li a6, -1
; RV32-NEXT: mv a4, a5
; RV32-NEXT: li a2, -1
; RV32-NEXT: mv a7, a5
; RV32-NEXT: bltz a3, .LBB51_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: li a4, -1
; RV32-NEXT: li a7, -1
; RV32-NEXT: .LBB51_2: # %entry
; RV32-NEXT: lui a7, 524288
; RV32-NEXT: addi a2, a7, -1
; RV32-NEXT: mv a0, a5
; RV32-NEXT: bgeu a1, a2, .LBB51_19
; RV32-NEXT: lui a4, 524288
; RV32-NEXT: addi a6, a4, -1
; RV32-NEXT: mv t0, a5
; RV32-NEXT: bgeu a1, a6, .LBB51_19
; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: lw t0, 16(sp)
; RV32-NEXT: bne a1, a2, .LBB51_20
; RV32-NEXT: lw a0, 16(sp)
; RV32-NEXT: bne a1, a6, .LBB51_20
; RV32-NEXT: .LBB51_4: # %entry
; RV32-NEXT: or a0, t0, a3
; RV32-NEXT: bnez a0, .LBB51_21
; RV32-NEXT: or t0, a0, a3
; RV32-NEXT: bnez t0, .LBB51_21
; RV32-NEXT: .LBB51_5: # %entry
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a7, a1
; RV32-NEXT: bgez a3, .LBB51_22
; RV32-NEXT: .LBB51_6: # %entry
; RV32-NEXT: bgeu a1, a2, .LBB51_23
; RV32-NEXT: bgeu a1, a6, .LBB51_23
; RV32-NEXT: .LBB51_7: # %entry
; RV32-NEXT: bnez a0, .LBB51_24
; RV32-NEXT: bnez t0, .LBB51_24
; RV32-NEXT: .LBB51_8: # %entry
; RV32-NEXT: li a2, 0
; RV32-NEXT: li a6, 0
; RV32-NEXT: bnez a3, .LBB51_25
; RV32-NEXT: .LBB51_9: # %entry
; RV32-NEXT: bgez a3, .LBB51_26
; RV32-NEXT: .LBB51_10: # %entry
; RV32-NEXT: mv a4, a5
; RV32-NEXT: bgeu a7, a1, .LBB51_27
; RV32-NEXT: mv a7, a5
; RV32-NEXT: bgeu a4, a1, .LBB51_27
; RV32-NEXT: .LBB51_11: # %entry
; RV32-NEXT: mv a0, a5
; RV32-NEXT: bne a1, a7, .LBB51_28
; RV32-NEXT: bne a1, a4, .LBB51_28
; RV32-NEXT: .LBB51_12: # %entry
; RV32-NEXT: bltz a3, .LBB51_29
; RV32-NEXT: .LBB51_13: # %entry
; RV32-NEXT: and a2, a2, a3
; RV32-NEXT: bne a2, a6, .LBB51_30
; RV32-NEXT: and a6, a6, a3
; RV32-NEXT: bne a6, a2, .LBB51_30
; RV32-NEXT: .LBB51_14: # %entry
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a5, a1
; RV32-NEXT: bltz a3, .LBB51_31
; RV32-NEXT: .LBB51_15: # %entry
; RV32-NEXT: bgeu a7, a1, .LBB51_32
; RV32-NEXT: bgeu a4, a1, .LBB51_32
; RV32-NEXT: .LBB51_16: # %entry
; RV32-NEXT: beq a2, a6, .LBB51_18
; RV32-NEXT: beq a6, a2, .LBB51_18
; RV32-NEXT: .LBB51_17: # %entry
; RV32-NEXT: mv a1, a4
; RV32-NEXT: mv a1, a5
; RV32-NEXT: .LBB51_18: # %entry
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret
; RV32-NEXT: .LBB51_19: # %entry
; RV32-NEXT: li a0, -1
; RV32-NEXT: lw t0, 16(sp)
; RV32-NEXT: beq a1, a2, .LBB51_4
; RV32-NEXT: li t0, -1
; RV32-NEXT: lw a0, 16(sp)
; RV32-NEXT: beq a1, a6, .LBB51_4
; RV32-NEXT: .LBB51_20: # %entry
; RV32-NEXT: mv a5, a0
; RV32-NEXT: or a0, t0, a3
; RV32-NEXT: beqz a0, .LBB51_5
; RV32-NEXT: mv a5, t0
; RV32-NEXT: or t0, a0, a3
; RV32-NEXT: beqz t0, .LBB51_5
; RV32-NEXT: .LBB51_21: # %entry
; RV32-NEXT: mv a5, a4
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a5, a7
; RV32-NEXT: mv a7, a1
; RV32-NEXT: bltz a3, .LBB51_6
; RV32-NEXT: .LBB51_22: # %entry
; RV32-NEXT: mv a4, a2
; RV32-NEXT: bltu a1, a2, .LBB51_7
; RV32-NEXT: mv a7, a6
; RV32-NEXT: bltu a1, a6, .LBB51_7
; RV32-NEXT: .LBB51_23: # %entry
; RV32-NEXT: mv a1, a2
; RV32-NEXT: beqz a0, .LBB51_8
; RV32-NEXT: mv a1, a6
; RV32-NEXT: beqz t0, .LBB51_8
; RV32-NEXT: .LBB51_24: # %entry
; RV32-NEXT: mv a1, a4
; RV32-NEXT: li a2, 0
; RV32-NEXT: mv a1, a7
; RV32-NEXT: li a6, 0
; RV32-NEXT: beqz a3, .LBB51_9
; RV32-NEXT: .LBB51_25: # %entry
; RV32-NEXT: srai a0, a3, 31
; RV32-NEXT: and a2, a0, t0
; RV32-NEXT: srai a6, a3, 31
; RV32-NEXT: and a6, a6, a0
; RV32-NEXT: bltz a3, .LBB51_10
; RV32-NEXT: .LBB51_26: # %entry
; RV32-NEXT: li a3, 0
; RV32-NEXT: mv a4, a5
; RV32-NEXT: bltu a7, a1, .LBB51_11
; RV32-NEXT: mv a7, a5
; RV32-NEXT: bltu a4, a1, .LBB51_11
; RV32-NEXT: .LBB51_27: # %entry
; RV32-NEXT: li a4, 0
; RV32-NEXT: li a7, 0
; RV32-NEXT: mv a0, a5
; RV32-NEXT: beq a1, a7, .LBB51_12
; RV32-NEXT: beq a1, a4, .LBB51_12
; RV32-NEXT: .LBB51_28: # %entry
; RV32-NEXT: mv a0, a4
; RV32-NEXT: mv a0, a7
; RV32-NEXT: bgez a3, .LBB51_13
; RV32-NEXT: .LBB51_29: # %entry
; RV32-NEXT: li a5, 0
; RV32-NEXT: and a2, a2, a3
; RV32-NEXT: beq a2, a6, .LBB51_14
; RV32-NEXT: and a6, a6, a3
; RV32-NEXT: beq a6, a2, .LBB51_14
; RV32-NEXT: .LBB51_30: # %entry
; RV32-NEXT: mv a0, a5
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a5, a1
; RV32-NEXT: bgez a3, .LBB51_15
; RV32-NEXT: .LBB51_31: # %entry
; RV32-NEXT: lui a4, 524288
; RV32-NEXT: bltu a7, a1, .LBB51_16
; RV32-NEXT: lui a5, 524288
; RV32-NEXT: bltu a4, a1, .LBB51_16
; RV32-NEXT: .LBB51_32: # %entry
; RV32-NEXT: lui a1, 524288
; RV32-NEXT: bne a2, a6, .LBB51_17
; RV32-NEXT: bne a6, a2, .LBB51_17
; RV32-NEXT: j .LBB51_18
;
; RV64-LABEL: stest_f16i64_mm:

1183
llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
View File

File diff suppressed because it is too large Load Diff

800
llvm/test/CodeGen/RISCV/half-arith.ll
View File

File diff suppressed because it is too large Load Diff

112
llvm/test/CodeGen/RISCV/half-convert.ll
View File

@ -336,17 +336,17 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: addi s0, a1, -1
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __fixunssfsi@plt
; RV32I-NEXT: li s3, 0
; RV32I-NEXT: bltz s0, .LBB3_2
; RV32I-NEXT: bltz s2, .LBB3_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: .LBB3_2: # %start
@ -356,9 +356,9 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: bgtz a0, .LBB3_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s2, s3
; RV32I-NEXT: mv s0, s3
; RV32I-NEXT: .LBB3_4: # %start
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
@ -376,17 +376,17 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: addiw s0, a1, -1
; RV64I-NEXT: and a0, a0, s0
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __fixunssfdi@plt
; RV64I-NEXT: li s3, 0
; RV64I-NEXT: bltz s0, .LBB3_2
; RV64I-NEXT: bltz s2, .LBB3_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB3_2: # %start
@ -396,9 +396,9 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: bgtz a0, .LBB3_4
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: mv s2, s3
; RV64I-NEXT: mv s0, s3
; RV64I-NEXT: .LBB3_4: # %start
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
@ -1378,25 +1378,25 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixunssfdi@plt
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: li s5, 0
; RV32I-NEXT: bltz s1, .LBB12_2
; RV32I-NEXT: bltz s2, .LBB12_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: .LBB12_2: # %start
; RV32I-NEXT: lui a0, 391168
; RV32I-NEXT: addi s1, a0, -1
; RV32I-NEXT: addi s4, a0, -1
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: li s2, -1
; RV32I-NEXT: li s3, -1
; RV32I-NEXT: li s4, -1
; RV32I-NEXT: bgtz a0, .LBB12_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s4, s5
; RV32I-NEXT: mv s3, s5
; RV32I-NEXT: .LBB12_4: # %start
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0
@ -1404,17 +1404,17 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV32I-NEXT: li s5, 0
; RV32I-NEXT: bltz a0, .LBB12_6
; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s5, s2
; RV32I-NEXT: mv s5, s1
; RV32I-NEXT: .LBB12_6: # %start
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: bgtz a0, .LBB12_8
; RV32I-NEXT: # %bb.7: # %start
; RV32I-NEXT: mv s3, s5
; RV32I-NEXT: mv s2, s5
; RV32I-NEXT: .LBB12_8: # %start
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
@ -2507,12 +2507,12 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a1, 815104
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfsi@plt
; RV32I-NEXT: li s1, 0
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: lui s3, 1048568
; RV32I-NEXT: bltz s2, .LBB32_2
; RV32I-NEXT: bltz s1, .LBB32_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: .LBB32_2: # %start
@ -2520,7 +2520,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV32I-NEXT: addi a1, a0, -512
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: bge s1, a0, .LBB32_4
; RV32I-NEXT: bge s2, a0, .LBB32_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: lui a0, 8
; RV32I-NEXT: addi s3, a0, -1
@ -2528,11 +2528,11 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: bne a0, s1, .LBB32_6
; RV32I-NEXT: bne a0, s2, .LBB32_6
; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s1, s3
; RV32I-NEXT: mv s2, s3
; RV32I-NEXT: .LBB32_6: # %start
; RV32I-NEXT: slli a0, s1, 16
; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@ -2556,12 +2556,12 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 815104
; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: li s1, 0
; RV64I-NEXT: li s2, 0
; RV64I-NEXT: lui s3, 1048568
; RV64I-NEXT: bltz s2, .LBB32_2
; RV64I-NEXT: bltz s1, .LBB32_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB32_2: # %start
@ -2569,7 +2569,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64I-NEXT: addiw a1, a0, -512
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: bge s1, a0, .LBB32_4
; RV64I-NEXT: bge s2, a0, .LBB32_4
; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: lui a0, 8
; RV64I-NEXT: addiw s3, a0, -1
@ -2577,11 +2577,11 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: bne a0, s1, .LBB32_6
; RV64I-NEXT: bne a0, s2, .LBB32_6
; RV64I-NEXT: # %bb.5: # %start
; RV64I-NEXT: mv s1, s3
; RV64I-NEXT: mv s2, s3
; RV64I-NEXT: .LBB32_6: # %start
; RV64I-NEXT: slli a0, s1, 48
; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
@ -2909,31 +2909,31 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a1, 798720
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfsi@plt
; RV32I-NEXT: li s1, 0
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: li s3, -128
; RV32I-NEXT: bltz s2, .LBB36_2
; RV32I-NEXT: bltz s1, .LBB36_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: .LBB36_2: # %start
; RV32I-NEXT: lui a1, 274400
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: li s2, 127
; RV32I-NEXT: blt s1, a0, .LBB36_4
; RV32I-NEXT: li s1, 127
; RV32I-NEXT: blt s2, a0, .LBB36_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s2, s3
; RV32I-NEXT: mv s1, s3
; RV32I-NEXT: .LBB36_4: # %start
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: bne a0, s1, .LBB36_6
; RV32I-NEXT: bne a0, s2, .LBB36_6
; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s1, s2
; RV32I-NEXT: mv s2, s1
; RV32I-NEXT: .LBB36_6: # %start
; RV32I-NEXT: slli a0, s1, 24
; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
@ -2957,31 +2957,31 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 798720
; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: li s1, 0
; RV64I-NEXT: li s2, 0
; RV64I-NEXT: li s3, -128
; RV64I-NEXT: bltz s2, .LBB36_2
; RV64I-NEXT: bltz s1, .LBB36_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB36_2: # %start
; RV64I-NEXT: lui a1, 274400
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: li s2, 127
; RV64I-NEXT: blt s1, a0, .LBB36_4
; RV64I-NEXT: li s1, 127
; RV64I-NEXT: blt s2, a0, .LBB36_4
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: mv s2, s3
; RV64I-NEXT: mv s1, s3
; RV64I-NEXT: .LBB36_4: # %start
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: bne a0, s1, .LBB36_6
; RV64I-NEXT: bne a0, s2, .LBB36_6
; RV64I-NEXT: # %bb.5: # %start
; RV64I-NEXT: mv s1, s2
; RV64I-NEXT: mv s2, s1
; RV64I-NEXT: .LBB36_6: # %start
; RV64I-NEXT: slli a0, s1, 56
; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload

168
llvm/test/CodeGen/RISCV/half-intrinsics.ll
View File

@ -398,24 +398,24 @@ define half @sincos_f16(half %a) nounwind {
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s1, a1, -1
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: call sinf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call cosf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s2, s1
; RV32I-NEXT: and a0, s1, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s0, s1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@ -433,24 +433,24 @@ define half @sincos_f16(half %a) nounwind {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s1, a1, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: call sinf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call cosf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s2, s1
; RV64I-NEXT: and a0, s1, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s0, s1
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
@ -523,13 +523,13 @@ define half @pow_f16(half %a, half %b) nounwind {
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0
; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1
@ -549,13 +549,13 @@ define half @pow_f16(half %a, half %b) nounwind {
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1
; RV64I-NEXT: and a0, a0, s0
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0
; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1
@ -982,20 +982,20 @@ define half @fma_f16(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a2
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: addi s3, a1, -1
; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: and a0, s1, s0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0
; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
@ -1015,20 +1015,20 @@ define half @fma_f16(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1
; RV64I-NEXT: and a0, a0, s0
; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: and a0, s1, s0
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0
; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
@ -1074,26 +1074,26 @@ define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a2
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s1, a1, -1
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s3, s1
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s2, s1
; RV32I-NEXT: addi s3, a1, -1
; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s0, s1
; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
@ -1112,26 +1112,26 @@ define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s1, a1, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s3, s1
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s2, s1
; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s0, s1
; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
@ -1213,13 +1213,13 @@ define half @minnum_f16(half %a, half %b) nounwind {
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0
; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1
@ -1239,13 +1239,13 @@ define half @minnum_f16(half %a, half %b) nounwind {
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1
; RV64I-NEXT: and a0, a0, s0
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0
; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1
@ -1291,13 +1291,13 @@ define half @maxnum_f16(half %a, half %b) nounwind {
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0
; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1
@ -1317,13 +1317,13 @@ define half @maxnum_f16(half %a, half %b) nounwind {
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1
; RV64I-NEXT: and a0, a0, s0
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0
; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1

388
llvm/test/CodeGen/RISCV/mul.ll
View File

@ -1141,50 +1141,50 @@ define i64 @muli64_m3840(i64 %a) nounwind {
define i128 @muli128_m3840(i128 %a) nounwind {
; RV32I-LABEL: muli128_m3840:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 4(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw a4, 0(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: srli a6, a2, 20
; RV32I-NEXT: slli a5, a3, 12
; RV32I-NEXT: or a6, a5, a6
; RV32I-NEXT: srli a7, a2, 24
; RV32I-NEXT: slli a5, a3, 8
; RV32I-NEXT: or a7, a5, a7
; RV32I-NEXT: sltu t0, a7, a6
; RV32I-NEXT: srli t1, a3, 20
; RV32I-NEXT: slli a5, a1, 12
; RV32I-NEXT: or a5, a5, t1
; RV32I-NEXT: srli a3, a3, 24
; RV32I-NEXT: slli a1, a1, 8
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: sub t2, a1, a5
; RV32I-NEXT: lw a6, 0(a1)
; RV32I-NEXT: lw a5, 12(a1)
; RV32I-NEXT: srli a1, a4, 20
; RV32I-NEXT: slli a3, a2, 12
; RV32I-NEXT: or a3, a3, a1
; RV32I-NEXT: srli a1, a4, 24
; RV32I-NEXT: slli a2, a2, 8
; RV32I-NEXT: or a5, a2, a1
; RV32I-NEXT: slli t1, a4, 12
; RV32I-NEXT: slli t3, a4, 8
; RV32I-NEXT: sltu t4, t3, t1
; RV32I-NEXT: sub t0, t2, t0
; RV32I-NEXT: mv a2, t4
; RV32I-NEXT: slli a2, a3, 12
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: srli a2, a4, 24
; RV32I-NEXT: slli a7, a3, 8
; RV32I-NEXT: or a2, a7, a2
; RV32I-NEXT: sltu t0, a2, a1
; RV32I-NEXT: srli a7, a3, 20
; RV32I-NEXT: slli t1, a5, 12
; RV32I-NEXT: or a7, t1, a7
; RV32I-NEXT: srli a3, a3, 24
; RV32I-NEXT: slli a5, a5, 8
; RV32I-NEXT: or a3, a5, a3
; RV32I-NEXT: sub t1, a3, a7
; RV32I-NEXT: srli a3, a6, 20
; RV32I-NEXT: slli a5, a4, 12
; RV32I-NEXT: or a3, a5, a3
; RV32I-NEXT: srli a5, a6, 24
; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: or a5, a4, a5
; RV32I-NEXT: slli a4, a6, 12
; RV32I-NEXT: slli a6, a6, 8
; RV32I-NEXT: sltu a7, a6, a4
; RV32I-NEXT: sub t0, t1, t0
; RV32I-NEXT: mv t1, a7
; RV32I-NEXT: beq a5, a3, .LBB30_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a5, a3
; RV32I-NEXT: sltu t1, a5, a3
; RV32I-NEXT: .LBB30_2:
; RV32I-NEXT: sub a1, a7, a6
; RV32I-NEXT: sltu a4, a1, a2
; RV32I-NEXT: sub a4, t0, a4
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: sub a2, a5, a3
; RV32I-NEXT: sub a2, a2, t4
; RV32I-NEXT: sub a3, t3, t1
; RV32I-NEXT: sw a3, 0(a0)
; RV32I-NEXT: sw a2, 4(a0)
; RV32I-NEXT: sub a1, a2, a1
; RV32I-NEXT: sltu a2, a1, t1
; RV32I-NEXT: sub a2, t0, a2
; RV32I-NEXT: sub a1, a1, t1
; RV32I-NEXT: sub a3, a5, a3
; RV32I-NEXT: sub a3, a3, a7
; RV32I-NEXT: sub a4, a6, a4
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: sw a4, 12(a0)
; RV32I-NEXT: sw a2, 12(a0)
; RV32I-NEXT: ret
;
; RV32IM-LABEL: muli128_m3840:
@ -1192,56 +1192,54 @@ define i128 @muli128_m3840(i128 %a) nounwind {
; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s2, 4(sp) # 4-byte Folded Spill
; RV32IM-NEXT: lw a6, 12(a1)
; RV32IM-NEXT: lw a7, 8(a1)
; RV32IM-NEXT: lw a2, 12(a1)
; RV32IM-NEXT: lw a3, 8(a1)
; RV32IM-NEXT: lw a4, 0(a1)
; RV32IM-NEXT: lw a1, 4(a1)
; RV32IM-NEXT: lui a5, 1048575
; RV32IM-NEXT: addi a5, a5, 256
; RV32IM-NEXT: mulhu a2, a4, a5
; RV32IM-NEXT: mul a3, a1, a5
; RV32IM-NEXT: add a2, a3, a2
; RV32IM-NEXT: sltu t0, a2, a3
; RV32IM-NEXT: mulhu a3, a1, a5
; RV32IM-NEXT: add t5, a3, t0
; RV32IM-NEXT: sub t0, a2, a4
; RV32IM-NEXT: neg t4, a4
; RV32IM-NEXT: sltu t1, t0, t4
; RV32IM-NEXT: mulhu a6, a4, a5
; RV32IM-NEXT: mul a7, a1, a5
; RV32IM-NEXT: add a6, a7, a6
; RV32IM-NEXT: sltu a7, a6, a7
; RV32IM-NEXT: mulhu t0, a1, a5
; RV32IM-NEXT: add a7, t0, a7
; RV32IM-NEXT: sub a6, a6, a4
; RV32IM-NEXT: neg t0, a4
; RV32IM-NEXT: sltu t1, a6, t0
; RV32IM-NEXT: li t2, -1
; RV32IM-NEXT: mulhu t3, a4, t2
; RV32IM-NEXT: add a2, t3, t1
; RV32IM-NEXT: add t1, t5, a2
; RV32IM-NEXT: sub a3, t1, a1
; RV32IM-NEXT: mul a2, a7, a5
; RV32IM-NEXT: sub a2, a2, a4
; RV32IM-NEXT: add t6, a3, a2
; RV32IM-NEXT: sltu s2, t6, a3
; RV32IM-NEXT: add t1, t3, t1
; RV32IM-NEXT: add t1, a7, t1
; RV32IM-NEXT: sub t4, t1, a1
; RV32IM-NEXT: mul t5, a3, a5
; RV32IM-NEXT: sub t5, t5, a4
; RV32IM-NEXT: add t6, t4, t5
; RV32IM-NEXT: sltu s0, t6, t4
; RV32IM-NEXT: neg s1, a1
; RV32IM-NEXT: sltu a3, a3, s1
; RV32IM-NEXT: sltu s1, t1, t5
; RV32IM-NEXT: mulhu s0, a1, t2
; RV32IM-NEXT: add s1, s0, s1
; RV32IM-NEXT: add a3, s1, a3
; RV32IM-NEXT: sltu a2, a2, t4
; RV32IM-NEXT: mul s1, a6, a5
; RV32IM-NEXT: mulhu s0, a7, a5
; RV32IM-NEXT: sub s0, s0, a7
; RV32IM-NEXT: add s1, s0, s1
; RV32IM-NEXT: sub s0, t3, a4
; RV32IM-NEXT: sub a1, s0, a1
; RV32IM-NEXT: add a1, a1, s1
; RV32IM-NEXT: sltu t4, t4, s1
; RV32IM-NEXT: sltu a7, t1, a7
; RV32IM-NEXT: mulhu t1, a1, t2
; RV32IM-NEXT: add a7, t1, a7
; RV32IM-NEXT: add a7, a7, t4
; RV32IM-NEXT: sltu t0, t5, t0
; RV32IM-NEXT: mul a2, a2, a5
; RV32IM-NEXT: mulhu t1, a3, a5
; RV32IM-NEXT: sub a3, t1, a3
; RV32IM-NEXT: add a2, a3, a2
; RV32IM-NEXT: sub a3, t3, a4
; RV32IM-NEXT: sub a1, a3, a1
; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: add a1, a3, a1
; RV32IM-NEXT: add a1, a1, s2
; RV32IM-NEXT: add a1, a1, t0
; RV32IM-NEXT: add a1, a7, a1
; RV32IM-NEXT: add a1, a1, s0
; RV32IM-NEXT: mul a2, a4, a5
; RV32IM-NEXT: sw a2, 0(a0)
; RV32IM-NEXT: sw t0, 4(a0)
; RV32IM-NEXT: sw a6, 4(a0)
; RV32IM-NEXT: sw t6, 8(a0)
; RV32IM-NEXT: sw a1, 12(a0)
; RV32IM-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret
;
@ -1279,39 +1277,39 @@ define i128 @muli128_m63(i128 %a) nounwind {
; RV32I-LABEL: muli128_m63:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: lw t0, 12(a1)
; RV32I-NEXT: lw a4, 8(a1)
; RV32I-NEXT: lw a5, 12(a1)
; RV32I-NEXT: lw a7, 8(a1)
; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: slli a6, a2, 6
; RV32I-NEXT: sltu a7, a2, a6
; RV32I-NEXT: srli a1, a2, 26
; RV32I-NEXT: slli a5, a3, 6
; RV32I-NEXT: or t2, a5, a1
; RV32I-NEXT: mv t3, a7
; RV32I-NEXT: beq a3, t2, .LBB31_2
; RV32I-NEXT: slli a1, a2, 6
; RV32I-NEXT: sltu a4, a2, a1
; RV32I-NEXT: srli a6, a2, 26
; RV32I-NEXT: slli t0, a3, 6
; RV32I-NEXT: or a6, t0, a6
; RV32I-NEXT: mv t0, a4
; RV32I-NEXT: beq a3, a6, .LBB31_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu t3, a3, t2
; RV32I-NEXT: sltu t0, a3, a6
; RV32I-NEXT: .LBB31_2:
; RV32I-NEXT: srli t1, a3, 26
; RV32I-NEXT: slli a1, a4, 6
; RV32I-NEXT: or a1, a1, t1
; RV32I-NEXT: sub a5, a4, a1
; RV32I-NEXT: sltu t1, a5, t3
; RV32I-NEXT: sltu t4, a4, a1
; RV32I-NEXT: srli a4, a4, 26
; RV32I-NEXT: slli a1, t0, 6
; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: sub a1, t0, a1
; RV32I-NEXT: sub a1, a1, t4
; RV32I-NEXT: sub a1, a1, t1
; RV32I-NEXT: sub a4, a5, t3
; RV32I-NEXT: sub a3, a3, t2
; RV32I-NEXT: sub a3, a3, a7
; RV32I-NEXT: sub a2, a2, a6
; RV32I-NEXT: sw a2, 0(a0)
; RV32I-NEXT: slli t2, a7, 6
; RV32I-NEXT: or t1, t2, t1
; RV32I-NEXT: sub t2, a7, t1
; RV32I-NEXT: sltu t3, t2, t0
; RV32I-NEXT: sltu t1, a7, t1
; RV32I-NEXT: srli a7, a7, 26
; RV32I-NEXT: slli t4, a5, 6
; RV32I-NEXT: or a7, t4, a7
; RV32I-NEXT: sub a5, a5, a7
; RV32I-NEXT: sub a5, a5, t1
; RV32I-NEXT: sub a5, a5, t3
; RV32I-NEXT: sub a7, t2, t0
; RV32I-NEXT: sub a3, a3, a6
; RV32I-NEXT: sub a3, a3, a4
; RV32I-NEXT: sub a1, a2, a1
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: sw a7, 8(a0)
; RV32I-NEXT: sw a5, 12(a0)
; RV32I-NEXT: ret
;
; RV32IM-LABEL: muli128_m63:
@ -1319,55 +1317,55 @@ define i128 @muli128_m63(i128 %a) nounwind {
; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32IM-NEXT: lw a7, 12(a1)
; RV32IM-NEXT: lw a2, 12(a1)
; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a4, 4(a1)
; RV32IM-NEXT: lw t5, 8(a1)
; RV32IM-NEXT: li a6, -63
; RV32IM-NEXT: mulhu a5, a3, a6
; RV32IM-NEXT: slli a2, a4, 6
; RV32IM-NEXT: sub a2, a2, a4
; RV32IM-NEXT: sub a5, a5, a2
; RV32IM-NEXT: neg a2, a2
; RV32IM-NEXT: sltu t0, a5, a2
; RV32IM-NEXT: mulhu a2, a4, a6
; RV32IM-NEXT: add t4, a2, t0
; RV32IM-NEXT: sub t0, a5, a3
; RV32IM-NEXT: neg t1, a3
; RV32IM-NEXT: sltu a5, t0, t1
; RV32IM-NEXT: lw a1, 8(a1)
; RV32IM-NEXT: li a5, -63
; RV32IM-NEXT: mulhu a6, a3, a5
; RV32IM-NEXT: slli a7, a4, 6
; RV32IM-NEXT: sub a7, a7, a4
; RV32IM-NEXT: sub a6, a6, a7
; RV32IM-NEXT: neg a7, a7
; RV32IM-NEXT: sltu a7, a6, a7
; RV32IM-NEXT: mulhu t0, a4, a5
; RV32IM-NEXT: add a7, t0, a7
; RV32IM-NEXT: sub a6, a6, a3
; RV32IM-NEXT: neg t0, a3
; RV32IM-NEXT: sltu t1, a6, t0
; RV32IM-NEXT: li t2, -1
; RV32IM-NEXT: mulhu t3, a3, t2
; RV32IM-NEXT: add a5, t3, a5
; RV32IM-NEXT: add a5, t4, a5
; RV32IM-NEXT: sub a2, a5, a4
; RV32IM-NEXT: slli a1, t5, 6
; RV32IM-NEXT: sub a1, a1, t5
; RV32IM-NEXT: add a1, a1, a3
; RV32IM-NEXT: sub t6, a2, a1
; RV32IM-NEXT: sltu s0, t6, a2
; RV32IM-NEXT: add t1, t3, t1
; RV32IM-NEXT: add t1, a7, t1
; RV32IM-NEXT: sub t4, t1, a4
; RV32IM-NEXT: slli t5, a1, 6
; RV32IM-NEXT: sub t5, t5, a1
; RV32IM-NEXT: add t5, t5, a3
; RV32IM-NEXT: sub t6, t4, t5
; RV32IM-NEXT: sltu s0, t6, t4
; RV32IM-NEXT: neg s1, a4
; RV32IM-NEXT: sltu a2, a2, s1
; RV32IM-NEXT: sltu a5, a5, t4
; RV32IM-NEXT: mulhu s1, a4, t2
; RV32IM-NEXT: add a5, s1, a5
; RV32IM-NEXT: add a2, a5, a2
; RV32IM-NEXT: slli a5, a7, 6
; RV32IM-NEXT: sub a5, a7, a5
; RV32IM-NEXT: mulhu s1, t5, a6
; RV32IM-NEXT: sub s1, s1, t5
; RV32IM-NEXT: add a5, s1, a5
; RV32IM-NEXT: sub s1, t3, a3
; RV32IM-NEXT: sub a4, s1, a4
; RV32IM-NEXT: add a4, a4, a5
; RV32IM-NEXT: neg a1, a1
; RV32IM-NEXT: sltu a1, a1, t1
; RV32IM-NEXT: add a1, a4, a1
; RV32IM-NEXT: sltu t4, t4, s1
; RV32IM-NEXT: sltu a7, t1, a7
; RV32IM-NEXT: mulhu t1, a4, t2
; RV32IM-NEXT: add a7, t1, a7
; RV32IM-NEXT: add a7, a7, t4
; RV32IM-NEXT: slli t1, a2, 6
; RV32IM-NEXT: sub a2, a2, t1
; RV32IM-NEXT: mulhu a5, a1, a5
; RV32IM-NEXT: sub a1, a5, a1
; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: sub a2, t3, a3
; RV32IM-NEXT: sub a2, a2, a4
; RV32IM-NEXT: add a1, a2, a1
; RV32IM-NEXT: neg a2, t5
; RV32IM-NEXT: sltu a2, a2, t0
; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: add a1, a7, a1
; RV32IM-NEXT: add a1, a1, s0
; RV32IM-NEXT: slli a2, a3, 6
; RV32IM-NEXT: sub a2, a3, a2
; RV32IM-NEXT: sw a2, 0(a0)
; RV32IM-NEXT: sw t0, 4(a0)
; RV32IM-NEXT: sw a6, 4(a0)
; RV32IM-NEXT: sw t6, 8(a0)
; RV32IM-NEXT: sw a1, 12(a0)
; RV32IM-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
@ -1417,60 +1415,60 @@ define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s5, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: srai s4, a3, 31
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: mv a2, s5
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: add s1, a0, s1
; RV32I-NEXT: sltu a0, s1, a0
; RV32I-NEXT: add s5, a0, s5
; RV32I-NEXT: sltu a0, s5, a0
; RV32I-NEXT: add s7, a1, a0
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: add a2, a0, s1
; RV32I-NEXT: add a2, a0, s5
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: add s8, s7, a0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv s9, a0
; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: mv s6, a1
; RV32I-NEXT: add s1, a0, s8
; RV32I-NEXT: mv a0, s5
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: add s9, a0, s8
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: add a3, a0, s0
; RV32I-NEXT: add a2, s1, a3
; RV32I-NEXT: sltu a4, a2, s1
; RV32I-NEXT: sltu a5, s1, s9
; RV32I-NEXT: sltu s1, s8, s7
; RV32I-NEXT: add s1, s6, s1
; RV32I-NEXT: add a5, s1, a5
; RV32I-NEXT: add a1, a1, s5
; RV32I-NEXT: add a3, a0, s2
; RV32I-NEXT: add a2, s9, a3
; RV32I-NEXT: sltu a4, a2, s9
; RV32I-NEXT: sltu a5, s9, s5
; RV32I-NEXT: sltu a6, s8, s7
; RV32I-NEXT: add a6, s6, a6
; RV32I-NEXT: add a5, a6, a5
; RV32I-NEXT: add a1, a1, s3
; RV32I-NEXT: sltu a0, a3, a0
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: add a0, a5, a0
@ -1492,36 +1490,36 @@ define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind {
;
; RV32IM-LABEL: mulhsu_i64:
; RV32IM: # %bb.0:
; RV32IM-NEXT: srai a7, a3, 31
; RV32IM-NEXT: mulhu a6, a0, a2
; RV32IM-NEXT: mul a5, a1, a2
; RV32IM-NEXT: add a4, a5, a6
; RV32IM-NEXT: sltu a5, a4, a5
; RV32IM-NEXT: srai a4, a3, 31
; RV32IM-NEXT: mulhu a5, a0, a2
; RV32IM-NEXT: mul a6, a1, a2
; RV32IM-NEXT: add a5, a6, a5
; RV32IM-NEXT: sltu a6, a5, a6
; RV32IM-NEXT: mulhu a2, a1, a2
; RV32IM-NEXT: add a6, a2, a5
; RV32IM-NEXT: add a6, a2, a6
; RV32IM-NEXT: mul a2, a0, a3
; RV32IM-NEXT: add a4, a2, a4
; RV32IM-NEXT: sltu a2, a4, a2
; RV32IM-NEXT: mulhu a4, a0, a3
; RV32IM-NEXT: add a2, a4, a2
; RV32IM-NEXT: add a4, a6, a2
; RV32IM-NEXT: mul a5, a1, a3
; RV32IM-NEXT: add a2, a5, a4
; RV32IM-NEXT: mul t1, a7, a0
; RV32IM-NEXT: add t0, a2, t1
; RV32IM-NEXT: sltu t2, t0, a2
; RV32IM-NEXT: sltu a2, a2, a5
; RV32IM-NEXT: sltu a4, a4, a6
; RV32IM-NEXT: add a5, a2, a5
; RV32IM-NEXT: sltu a2, a5, a2
; RV32IM-NEXT: mulhu a5, a0, a3
; RV32IM-NEXT: add a2, a5, a2
; RV32IM-NEXT: add a5, a6, a2
; RV32IM-NEXT: mul a7, a1, a3
; RV32IM-NEXT: add t0, a7, a5
; RV32IM-NEXT: mul t1, a4, a0
; RV32IM-NEXT: add a2, t0, t1
; RV32IM-NEXT: sltu t2, a2, t0
; RV32IM-NEXT: sltu a7, t0, a7
; RV32IM-NEXT: sltu a5, a5, a6
; RV32IM-NEXT: mulhu a3, a1, a3
; RV32IM-NEXT: add a3, a3, a4
; RV32IM-NEXT: add a2, a3, a2
; RV32IM-NEXT: mul a1, a7, a1
; RV32IM-NEXT: mulhu a0, a7, a0
; RV32IM-NEXT: add a3, a3, a5
; RV32IM-NEXT: add a3, a3, a7
; RV32IM-NEXT: mul a1, a4, a1
; RV32IM-NEXT: mulhu a0, a4, a0
; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: add a0, a0, t1
; RV32IM-NEXT: add a0, a2, a0
; RV32IM-NEXT: add a0, a3, a0
; RV32IM-NEXT: add a1, a0, t2
; RV32IM-NEXT: mv a0, t0
; RV32IM-NEXT: mv a0, a2
; RV32IM-NEXT: ret
;
; RV64I-LABEL: mulhsu_i64:

44
llvm/test/CodeGen/RISCV/remat.ll
View File

@ -37,16 +37,16 @@ define i32 @test() nounwind {
; RV32I-NEXT: sw s9, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s10, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui s6, %hi(a)
; RV32I-NEXT: lw a0, %lo(a)(s6)
; RV32I-NEXT: lui s0, %hi(a)
; RV32I-NEXT: lw a0, %lo(a)(s0)
; RV32I-NEXT: beqz a0, .LBB0_11
; RV32I-NEXT: # %bb.1: # %for.body.preheader
; RV32I-NEXT: lui s2, %hi(l)
; RV32I-NEXT: lui s3, %hi(k)
; RV32I-NEXT: lui s4, %hi(j)
; RV32I-NEXT: lui s5, %hi(i)
; RV32I-NEXT: lui s1, %hi(d)
; RV32I-NEXT: lui s0, %hi(e)
; RV32I-NEXT: lui s1, %hi(l)
; RV32I-NEXT: lui s2, %hi(k)
; RV32I-NEXT: lui s3, %hi(j)
; RV32I-NEXT: lui s4, %hi(i)
; RV32I-NEXT: lui s5, %hi(d)
; RV32I-NEXT: lui s6, %hi(e)
; RV32I-NEXT: lui s7, %hi(f)
; RV32I-NEXT: lui s8, %hi(g)
; RV32I-NEXT: lui s9, %hi(h)
@ -55,56 +55,56 @@ define i32 @test() nounwind {
; RV32I-NEXT: j .LBB0_3
; RV32I-NEXT: .LBB0_2: # %for.inc
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(a)(s6)
; RV32I-NEXT: lw a0, %lo(a)(s0)
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: sw a0, %lo(a)(s6)
; RV32I-NEXT: sw a0, %lo(a)(s0)
; RV32I-NEXT: beqz a0, .LBB0_11
; RV32I-NEXT: .LBB0_3: # %for.body
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: lw a1, %lo(l)(s2)
; RV32I-NEXT: lw a1, %lo(l)(s1)
; RV32I-NEXT: beqz a1, .LBB0_5
; RV32I-NEXT: # %bb.4: # %if.then
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a1, %lo(b)(s11)
; RV32I-NEXT: lw a2, %lo(c)(s10)
; RV32I-NEXT: lw a3, %lo(d)(s1)
; RV32I-NEXT: lw a4, %lo(e)(s0)
; RV32I-NEXT: lw a3, %lo(d)(s5)
; RV32I-NEXT: lw a4, %lo(e)(s6)
; RV32I-NEXT: li a5, 32
; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_5: # %if.end
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(k)(s3)
; RV32I-NEXT: lw a0, %lo(k)(s2)
; RV32I-NEXT: beqz a0, .LBB0_7
; RV32I-NEXT: # %bb.6: # %if.then3
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(b)(s11)
; RV32I-NEXT: lw a1, %lo(c)(s10)
; RV32I-NEXT: lw a2, %lo(d)(s1)
; RV32I-NEXT: lw a3, %lo(e)(s0)
; RV32I-NEXT: lw a2, %lo(d)(s5)
; RV32I-NEXT: lw a3, %lo(e)(s6)
; RV32I-NEXT: lw a4, %lo(f)(s7)
; RV32I-NEXT: li a5, 64
; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_7: # %if.end5
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(j)(s4)
; RV32I-NEXT: lw a0, %lo(j)(s3)
; RV32I-NEXT: beqz a0, .LBB0_9
; RV32I-NEXT: # %bb.8: # %if.then7
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(c)(s10)
; RV32I-NEXT: lw a1, %lo(d)(s1)
; RV32I-NEXT: lw a2, %lo(e)(s0)
; RV32I-NEXT: lw a1, %lo(d)(s5)
; RV32I-NEXT: lw a2, %lo(e)(s6)
; RV32I-NEXT: lw a3, %lo(f)(s7)
; RV32I-NEXT: lw a4, %lo(g)(s8)
; RV32I-NEXT: li a5, 32
; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_9: # %if.end9
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(i)(s5)
; RV32I-NEXT: lw a0, %lo(i)(s4)
; RV32I-NEXT: beqz a0, .LBB0_2
; RV32I-NEXT: # %bb.10: # %if.then11
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(d)(s1)
; RV32I-NEXT: lw a1, %lo(e)(s0)
; RV32I-NEXT: lw a0, %lo(d)(s5)
; RV32I-NEXT: lw a1, %lo(e)(s6)
; RV32I-NEXT: lw a2, %lo(f)(s7)
; RV32I-NEXT: lw a3, %lo(g)(s8)
; RV32I-NEXT: lw a4, %lo(h)(s9)

24
llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
View File

@ -19,18 +19,18 @@ define half @half_test(half %a, half %b) nounwind {
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s1, a1, -1
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s0, s1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __divsf3@plt
@ -51,18 +51,18 @@ define half @half_test(half %a, half %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s1, a1, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s0, s1
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __divsf3@plt

30
llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
View File

@ -183,18 +183,18 @@ define i64 @rol_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: sll a6, a4, a2
; RV32I-NEXT: sll a5, a4, a2
; RV32I-NEXT: bnez a3, .LBB7_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB7_4:
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: not a5, a2
; RV32I-NEXT: srl a1, a1, a5
; RV32I-NEXT: or a3, a6, a1
; RV32I-NEXT: not a6, a2
; RV32I-NEXT: srl a1, a1, a6
; RV32I-NEXT: or a3, a5, a1
; RV32I-NEXT: sll a0, a0, a2
; RV32I-NEXT: srli a1, a4, 1
; RV32I-NEXT: srl a1, a1, a5
; RV32I-NEXT: srl a1, a1, a6
; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: ret
@ -208,18 +208,18 @@ define i64 @rol_i64(i64 %a, i64 %b) nounwind {
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: mv a4, a0
; RV32ZBB-NEXT: .LBB7_2:
; RV32ZBB-NEXT: sll a6, a4, a2
; RV32ZBB-NEXT: sll a5, a4, a2
; RV32ZBB-NEXT: bnez a3, .LBB7_4
; RV32ZBB-NEXT: # %bb.3:
; RV32ZBB-NEXT: mv a0, a1
; RV32ZBB-NEXT: .LBB7_4:
; RV32ZBB-NEXT: srli a1, a0, 1
; RV32ZBB-NEXT: not a5, a2
; RV32ZBB-NEXT: srl a1, a1, a5
; RV32ZBB-NEXT: or a3, a6, a1
; RV32ZBB-NEXT: not a6, a2
; RV32ZBB-NEXT: srl a1, a1, a6
; RV32ZBB-NEXT: or a3, a5, a1
; RV32ZBB-NEXT: sll a0, a0, a2
; RV32ZBB-NEXT: srli a1, a4, 1
; RV32ZBB-NEXT: srl a1, a1, a5
; RV32ZBB-NEXT: srl a1, a1, a6
; RV32ZBB-NEXT: or a1, a0, a1
; RV32ZBB-NEXT: mv a0, a3
; RV32ZBB-NEXT: ret
@ -233,18 +233,18 @@ define i64 @rol_i64(i64 %a, i64 %b) nounwind {
; RV32ZBP-NEXT: # %bb.1:
; RV32ZBP-NEXT: mv a4, a0
; RV32ZBP-NEXT: .LBB7_2:
; RV32ZBP-NEXT: sll a6, a4, a2
; RV32ZBP-NEXT: sll a5, a4, a2
; RV32ZBP-NEXT: bnez a3, .LBB7_4
; RV32ZBP-NEXT: # %bb.3:
; RV32ZBP-NEXT: mv a0, a1
; RV32ZBP-NEXT: .LBB7_4:
; RV32ZBP-NEXT: srli a1, a0, 1
; RV32ZBP-NEXT: not a5, a2
; RV32ZBP-NEXT: srl a1, a1, a5
; RV32ZBP-NEXT: or a3, a6, a1
; RV32ZBP-NEXT: not a6, a2
; RV32ZBP-NEXT: srl a1, a1, a6
; RV32ZBP-NEXT: or a3, a5, a1
; RV32ZBP-NEXT: sll a0, a0, a2
; RV32ZBP-NEXT: srli a1, a4, 1
; RV32ZBP-NEXT: srl a1, a1, a5
; RV32ZBP-NEXT: srl a1, a1, a6
; RV32ZBP-NEXT: or a1, a0, a1
; RV32ZBP-NEXT: mv a0, a3
; RV32ZBP-NEXT: ret

96
llvm/test/CodeGen/RISCV/rv32zbb.ll
View File

@ -73,8 +73,8 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: srli a0, a1, 1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2
@ -88,14 +88,14 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: addi s4, a2, 1365
; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s1, a1, 819
; RV32I-NEXT: and a1, a0, s1
; RV32I-NEXT: addi s5, a1, 819
; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
@ -103,12 +103,12 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s0, a1, 257
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: addi s3, a1, 257
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: srli a0, s4, 1
; RV32I-NEXT: or a0, s4, a0
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: srli a0, s2, 1
; RV32I-NEXT: or a0, s2, a0
; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4
@ -119,24 +119,24 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s1
; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s3, .LBB1_2
; RV32I-NEXT: bnez s0, .LBB1_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB1_3
; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB1_3:
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
@ -227,21 +227,21 @@ define i64 @cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s4
; RV32I-NEXT: not a1, s2
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: addi s4, a2, 1365
; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: addi s5, a1, 819
; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
@ -249,32 +249,32 @@ define i64 @cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: addi s3, a1, 257
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, s3, -1
; RV32I-NEXT: not a1, s3
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a0, s1, -1
; RV32I-NEXT: not a1, s1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s4, .LBB3_2
; RV32I-NEXT: bnez s2, .LBB3_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB3_3
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: srli a0, s0, 24
; RV32I-NEXT: .LBB3_3:
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
@ -356,17 +356,17 @@ define i64 @ctpop_i64(i64 %a) nounwind {
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: srli a0, a1, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s3, a2, 1365
; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: addi s2, a2, 1365
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: addi s3, a1, 819
; RV32I-NEXT: and a1, a0, s3
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
@ -378,12 +378,12 @@ define i64 @ctpop_i64(i64 %a) nounwind {
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli s5, a0, 24
; RV32I-NEXT: srli a0, s2, 1
; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: sub a0, s2, a0
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, s0, 1
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: sub a0, s0, a0
; RV32I-NEXT: and a1, a0, s3
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1

560
llvm/test/CodeGen/RISCV/rv32zbp.ll
View File

@ -39,18 +39,18 @@ define i64 @gorc1_i64(i64 %a) nounwind {
; RV32I-NEXT: slli a3, a1, 1
; RV32I-NEXT: lui a4, 699051
; RV32I-NEXT: addi a4, a4, -1366
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 1
; RV32I-NEXT: srli a5, a0, 1
; RV32I-NEXT: lui a3, 349525
; RV32I-NEXT: addi a3, a3, 1365
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: lui a6, 349525
; RV32I-NEXT: addi a6, a6, 1365
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc1_i64:
@ -102,18 +102,18 @@ define i64 @gorc2_i64(i64 %a) nounwind {
; RV32I-NEXT: slli a3, a1, 2
; RV32I-NEXT: lui a4, 838861
; RV32I-NEXT: addi a4, a4, -820
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 2
; RV32I-NEXT: srli a5, a0, 2
; RV32I-NEXT: lui a3, 209715
; RV32I-NEXT: addi a3, a3, 819
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc2_i64:
@ -181,34 +181,34 @@ define i64 @gorc3_i64(i64 %a) nounwind {
; RV32I-NEXT: slli a3, a0, 1
; RV32I-NEXT: lui a4, 699051
; RV32I-NEXT: addi a4, a4, -1366
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: srli a5, a1, 1
; RV32I-NEXT: lui a3, 349525
; RV32I-NEXT: addi a3, a3, 1365
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: lui a6, 349525
; RV32I-NEXT: addi a6, a6, 1365
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a6
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a3, a1, 2
; RV32I-NEXT: lui a4, 838861
; RV32I-NEXT: addi a4, a4, -820
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 2
; RV32I-NEXT: srli a5, a0, 2
; RV32I-NEXT: lui a3, 209715
; RV32I-NEXT: addi a3, a3, 819
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc3_i64:
@ -266,18 +266,18 @@ define i64 @gorc4_i64(i64 %a) nounwind {
; RV32I-NEXT: slli a3, a1, 4
; RV32I-NEXT: lui a4, 986895
; RV32I-NEXT: addi a4, a4, 240
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 4
; RV32I-NEXT: srli a5, a0, 4
; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: lui a6, 61681
; RV32I-NEXT: addi a6, a6, -241
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc4_i64:
@ -345,34 +345,34 @@ define i64 @gorc5_i64(i64 %a) nounwind {
; RV32I-NEXT: slli a3, a0, 1
; RV32I-NEXT: lui a4, 699051
; RV32I-NEXT: addi a4, a4, -1366
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: srli a5, a1, 1
; RV32I-NEXT: lui a3, 349525
; RV32I-NEXT: addi a3, a3, 1365
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: lui a6, 349525
; RV32I-NEXT: addi a6, a6, 1365
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a6
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a2, a0, 4
; RV32I-NEXT: slli a3, a1, 4
; RV32I-NEXT: lui a4, 986895
; RV32I-NEXT: addi a4, a4, 240
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 4
; RV32I-NEXT: srli a5, a0, 4
; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: lui a6, 61681
; RV32I-NEXT: addi a6, a6, -241
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc5_i64:
@ -446,34 +446,34 @@ define i64 @gorc6_i64(i64 %a) nounwind {
; RV32I-NEXT: slli a3, a0, 2
; RV32I-NEXT: lui a4, 838861
; RV32I-NEXT: addi a4, a4, -820
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a0, 2
; RV32I-NEXT: srli a5, a1, 2
; RV32I-NEXT: lui a3, 209715
; RV32I-NEXT: addi a3, a3, 819
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a6
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a2, a0, 4
; RV32I-NEXT: slli a3, a1, 4
; RV32I-NEXT: lui a4, 986895
; RV32I-NEXT: addi a4, a4, 240
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 4
; RV32I-NEXT: srli a5, a0, 4
; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: lui a6, 61681
; RV32I-NEXT: addi a6, a6, -241
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc6_i64:
@ -563,50 +563,50 @@ define i64 @gorc7_i64(i64 %a) nounwind {
; RV32I-NEXT: slli a3, a1, 1
; RV32I-NEXT: lui a4, 699051
; RV32I-NEXT: addi a4, a4, -1366
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 1
; RV32I-NEXT: srli a5, a0, 1
; RV32I-NEXT: lui a3, 349525
; RV32I-NEXT: addi a3, a3, 1365
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: lui a6, 349525
; RV32I-NEXT: addi a6, a6, 1365
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a2, a1, 2
; RV32I-NEXT: slli a3, a0, 2
; RV32I-NEXT: lui a4, 838861
; RV32I-NEXT: addi a4, a4, -820
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a0, 2
; RV32I-NEXT: srli a5, a1, 2
; RV32I-NEXT: lui a3, 209715
; RV32I-NEXT: addi a3, a3, 819
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a6
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a2, a0, 4
; RV32I-NEXT: slli a3, a1, 4
; RV32I-NEXT: lui a4, 986895
; RV32I-NEXT: addi a4, a4, 240
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 4
; RV32I-NEXT: srli a5, a0, 4
; RV32I-NEXT: lui a3, 61681
; RV32I-NEXT: addi a3, a3, -241
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: lui a6, 61681
; RV32I-NEXT: addi a6, a6, -241
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc7_i64:
@ -670,18 +670,18 @@ define i64 @gorc8_i64(i64 %a) nounwind {
; RV32I-NEXT: slli a3, a1, 8
; RV32I-NEXT: lui a4, 1044496
; RV32I-NEXT: addi a4, a4, -256
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 8
; RV32I-NEXT: srli a5, a0, 8
; RV32I-NEXT: lui a3, 4080
; RV32I-NEXT: addi a3, a3, 255
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: lui a6, 4080
; RV32I-NEXT: addi a6, a6, 255
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc8_i64:
@ -830,30 +830,30 @@ define i64 @gorc2b_i64(i64 %a) nounwind {
; RV32I-NEXT: slli a3, a0, 2
; RV32I-NEXT: lui a4, 838861
; RV32I-NEXT: addi a4, a4, -820
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a7, a2, a4
; RV32I-NEXT: srli a5, a0, 2
; RV32I-NEXT: srli a3, a1, 2
; RV32I-NEXT: lui a2, 209715
; RV32I-NEXT: addi a2, a2, 819
; RV32I-NEXT: and a3, a3, a2
; RV32I-NEXT: and a5, a5, a2
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a1, a1, a7
; RV32I-NEXT: or a0, a0, a6
; RV32I-NEXT: slli a3, a0, 2
; RV32I-NEXT: slli a5, a1, 2
; RV32I-NEXT: and a6, a5, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a5, a0, 2
; RV32I-NEXT: srli a6, a1, 2
; RV32I-NEXT: lui a7, 209715
; RV32I-NEXT: addi a7, a7, 819
; RV32I-NEXT: and a6, a6, a7
; RV32I-NEXT: and a5, a5, a7
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a1, a6, a1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a3, a1, 2
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 2
; RV32I-NEXT: srli a5, a0, 2
; RV32I-NEXT: and a5, a5, a2
; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: and a5, a5, a7
; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc2b_i64:
@ -941,46 +941,46 @@ define i64 @gorc3b_i64(i64 %a) nounwind {
; RV32I-NEXT: slli a3, a1, 1
; RV32I-NEXT: lui a4, 699051
; RV32I-NEXT: addi a4, a4, -1366
; RV32I-NEXT: and a6, a3, a4
; RV32I-NEXT: and a7, a2, a4
; RV32I-NEXT: srli a5, a1, 1
; RV32I-NEXT: srli a3, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a3, a3, a2
; RV32I-NEXT: and a5, a5, a2
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a0, a0, a7
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: slli a6, a1, 2
; RV32I-NEXT: slli a5, a0, 2
; RV32I-NEXT: lui a3, 838861
; RV32I-NEXT: addi a3, a3, -820
; RV32I-NEXT: and a7, a5, a3
; RV32I-NEXT: and a6, a6, a3
; RV32I-NEXT: srli t0, a0, 2
; RV32I-NEXT: srli a3, a1, 2
; RV32I-NEXT: lui a5, 209715
; RV32I-NEXT: addi a5, a5, 819
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: and a5, t0, a5
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a0, a0, a7
; RV32I-NEXT: slli a3, a0, 1
; RV32I-NEXT: slli a5, a1, 1
; RV32I-NEXT: and a6, a5, a4
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a5, a1, 1
; RV32I-NEXT: srli a6, a0, 1
; RV32I-NEXT: lui a7, 349525
; RV32I-NEXT: addi a7, a7, 1365
; RV32I-NEXT: and a6, a6, a7
; RV32I-NEXT: and a5, a5, a7
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a0, a6, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a2, a1, 2
; RV32I-NEXT: slli a3, a0, 2
; RV32I-NEXT: lui a5, 838861
; RV32I-NEXT: addi a5, a5, -820
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: srli a5, a0, 2
; RV32I-NEXT: srli a6, a1, 2
; RV32I-NEXT: lui t0, 209715
; RV32I-NEXT: addi t0, t0, 819
; RV32I-NEXT: and a6, a6, t0
; RV32I-NEXT: and a5, a5, t0
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a1, a6, a1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a2, a0, 1
; RV32I-NEXT: slli a3, a1, 1
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 1
; RV32I-NEXT: srli a5, a0, 1
; RV32I-NEXT: and a5, a5, a2
; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: and a5, a5, a7
; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: gorc3b_i64:
@ -1818,20 +1818,20 @@ define i64 @grev2b_i64(i64 %a) nounwind {
; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: slli a6, a1, 2
; RV32I-NEXT: slli a2, a1, 2
; RV32I-NEXT: slli a3, a0, 2
; RV32I-NEXT: lui a2, 838861
; RV32I-NEXT: addi a2, a2, -820
; RV32I-NEXT: and a7, a3, a2
; RV32I-NEXT: and a2, a6, a2
; RV32I-NEXT: lui a6, 838861
; RV32I-NEXT: addi a6, a6, -820
; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: srli a1, a1, 2
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: lui a3, 209715
; RV32I-NEXT: addi a3, a3, 819
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: or a0, a7, a0
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: slli a2, a0, 1
; RV32I-NEXT: slli a3, a1, 1
; RV32I-NEXT: and a3, a3, a4
@ -1945,40 +1945,40 @@ define i64 @grev0_i64(i64 %a) nounwind {
; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: slli a6, a0, 2
; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a3, a1, 2
; RV32I-NEXT: lui a2, 838861
; RV32I-NEXT: addi a2, a2, -820
; RV32I-NEXT: and a7, a3, a2
; RV32I-NEXT: and a6, a6, a2
; RV32I-NEXT: lui a6, 838861
; RV32I-NEXT: addi a6, a6, -820
; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: srli a1, a1, 2
; RV32I-NEXT: lui a3, 209715
; RV32I-NEXT: addi a3, a3, 819
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: or t0, a6, a0
; RV32I-NEXT: or a1, a7, a1
; RV32I-NEXT: slli a6, a1, 1
; RV32I-NEXT: slli a0, t0, 1
; RV32I-NEXT: and a7, a0, a4
; RV32I-NEXT: and a4, a6, a4
; RV32I-NEXT: lui a7, 209715
; RV32I-NEXT: addi a7, a7, 819
; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: and a0, a0, a7
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: slli a2, a1, 1
; RV32I-NEXT: slli a3, a0, 1
; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: srli a0, t0, 1
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a7, a0
; RV32I-NEXT: slli a4, a0, 2
; RV32I-NEXT: slli a5, a1, 2
; RV32I-NEXT: and a5, a5, a2
; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a3, a1, 2
; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: srli a1, a1, 2
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: and a0, a0, a7
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: grev0_i64:
@ -2275,13 +2275,13 @@ define i64 @bitreverse_i64(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: srli a2, a1, 8
; RV32I-NEXT: lui a3, 16
; RV32I-NEXT: addi a7, a3, -256
; RV32I-NEXT: and a2, a2, a7
; RV32I-NEXT: addi a3, a3, -256
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: slli a4, a1, 8
; RV32I-NEXT: lui a6, 4080
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: lui a5, 4080
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: or a1, a1, a2
@ -2293,27 +2293,27 @@ define i64 @bitreverse_i64(i64 %a) nounwind {
; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: srli a2, a1, 2
; RV32I-NEXT: lui a5, 209715
; RV32I-NEXT: addi a5, a5, 819
; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: srli a2, a1, 1
; RV32I-NEXT: lui a3, 349525
; RV32I-NEXT: addi a3, a3, 1365
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: or t0, a2, a1
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: lui a7, 349525
; RV32I-NEXT: addi a7, a7, 1365
; RV32I-NEXT: and a2, a2, a7
; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: srli a2, a0, 24
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: slli a2, a0, 8
; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: or a2, a2, a1
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a3, a0, 8
; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: and a1, a1, a4
@ -2321,16 +2321,16 @@ define i64 @bitreverse_i64(i64 %a) nounwind {
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: and a0, a0, a7
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a1, a1, a0
; RV32I-NEXT: mv a0, t0
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: bitreverse_i64:
@ -2462,13 +2462,13 @@ define i64 @bitreverse_bswap_i64(i64 %a) {
; RV32I: # %bb.0:
; RV32I-NEXT: srli a3, a1, 8
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a7, a2, -256
; RV32I-NEXT: and a3, a3, a7
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a3, a3, a2
; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: or a4, a3, a4
; RV32I-NEXT: slli a5, a1, 8
; RV32I-NEXT: lui a6, 4080
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: lui a3, 4080
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a5
; RV32I-NEXT: or a1, a1, a4
@ -2480,58 +2480,58 @@ define i64 @bitreverse_bswap_i64(i64 %a) {
; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a1, 2
; RV32I-NEXT: lui a3, 209715
; RV32I-NEXT: addi a3, a3, 819
; RV32I-NEXT: and a4, a4, a3
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a1, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a4, a4, a2
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: lui a7, 349525
; RV32I-NEXT: addi a7, a7, 1365
; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a0, 8
; RV32I-NEXT: and t0, a4, a7
; RV32I-NEXT: srli a4, a0, 24
; RV32I-NEXT: or t0, t0, a4
; RV32I-NEXT: slli a4, a0, 8
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: and a4, a4, a2
; RV32I-NEXT: srli t0, a0, 24
; RV32I-NEXT: or a4, a4, t0
; RV32I-NEXT: slli t0, a0, 8
; RV32I-NEXT: and t0, t0, a3
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: or a0, a0, t0
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: srli a4, a0, 4
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: srli a4, a0, 2
; RV32I-NEXT: and a4, a4, a3
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: srli a3, a0, 1
; RV32I-NEXT: and a3, a3, a2
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: and a0, a0, a7
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: srli a2, a0, 8
; RV32I-NEXT: and a2, a2, a7
; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: or a2, a2, a3
; RV32I-NEXT: slli a3, a0, 8
; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: srli a4, a0, 8
; RV32I-NEXT: and a4, a4, a2
; RV32I-NEXT: srli a5, a0, 24
; RV32I-NEXT: or a4, a4, a5
; RV32I-NEXT: slli a5, a0, 8
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: srli a2, a1, 8
; RV32I-NEXT: and a2, a2, a7
; RV32I-NEXT: srli a3, a1, 24
; RV32I-NEXT: or a2, a2, a3
; RV32I-NEXT: slli a3, a1, 8
; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: or a0, a0, a5
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: srli a4, a1, 8
; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: slli a4, a1, 8
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: or a1, a1, a2
@ -2584,16 +2584,16 @@ define i64 @shfl1_i64(i64 %a, i64 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 629146
; RV32I-NEXT: addi a2, a2, -1639
; RV32I-NEXT: and a6, a0, a2
; RV32I-NEXT: and a3, a0, a2
; RV32I-NEXT: and a2, a1, a2
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: slli a5, a0, 1
; RV32I-NEXT: lui a3, 279620
; RV32I-NEXT: addi a3, a3, 1092
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a2, a2, a3
; RV32I-NEXT: or a3, a6, a5
; RV32I-NEXT: lui a6, 279620
; RV32I-NEXT: addi a6, a6, 1092
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: lui a4, 139810
@ -2656,16 +2656,16 @@ define i64 @shfl2_i64(i64 %a, i64 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 801852
; RV32I-NEXT: addi a2, a2, 963
; RV32I-NEXT: and a6, a0, a2
; RV32I-NEXT: and a3, a0, a2
; RV32I-NEXT: and a2, a1, a2
; RV32I-NEXT: slli a4, a1, 2
; RV32I-NEXT: slli a5, a0, 2
; RV32I-NEXT: lui a3, 197379
; RV32I-NEXT: addi a3, a3, 48
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a2, a2, a3
; RV32I-NEXT: or a3, a6, a5
; RV32I-NEXT: lui a6, 197379
; RV32I-NEXT: addi a6, a6, 48
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: srli a1, a1, 2
; RV32I-NEXT: lui a4, 49345
@ -2728,24 +2728,24 @@ define i64 @shfl4_i64(i64 %a, i64 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 983295
; RV32I-NEXT: addi a2, a2, 15
; RV32I-NEXT: and a6, a1, a2
; RV32I-NEXT: and a3, a1, a2
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: slli a4, a1, 4
; RV32I-NEXT: slli a5, a0, 4
; RV32I-NEXT: lui a3, 61441
; RV32I-NEXT: addi a3, a3, -256
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: lui a6, 61441
; RV32I-NEXT: addi a6, a6, -256
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: srli a1, a1, 4
; RV32I-NEXT: srli a0, a0, 4
; RV32I-NEXT: lui a4, 3840
; RV32I-NEXT: addi a4, a4, 240
; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: lui a6, 3840
; RV32I-NEXT: addi a6, a6, 240
; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: shfl4_i64:
@ -2799,22 +2799,22 @@ define i64 @shfl8_i64(i64 %a, i64 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 1044480
; RV32I-NEXT: addi a2, a2, 255
; RV32I-NEXT: and a6, a0, a2
; RV32I-NEXT: and a3, a0, a2
; RV32I-NEXT: and a2, a1, a2
; RV32I-NEXT: slli a4, a0, 8
; RV32I-NEXT: slli a5, a1, 8
; RV32I-NEXT: lui a3, 4080
; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: lui a6, 4080
; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: srli a1, a1, 8
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: lui a4, 16
; RV32I-NEXT: addi a4, a4, -256
; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: lui a6, 16
; RV32I-NEXT: addi a6, a6, -256
; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a6
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: ret
;

28
llvm/test/CodeGen/RISCV/rv32zbt.ll
View File

@ -341,14 +341,14 @@ define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: fshl_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a5, a4, 5
; RV32I-NEXT: andi a5, a5, 1
; RV32I-NEXT: mv a6, a3
; RV32I-NEXT: bnez a5, .LBB13_2
; RV32I-NEXT: andi a6, a5, 1
; RV32I-NEXT: mv a5, a3
; RV32I-NEXT: bnez a6, .LBB13_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a5, a0
; RV32I-NEXT: .LBB13_2:
; RV32I-NEXT: sll a7, a6, a4
; RV32I-NEXT: bnez a5, .LBB13_4
; RV32I-NEXT: sll a7, a5, a4
; RV32I-NEXT: bnez a6, .LBB13_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: .LBB13_4:
@ -356,12 +356,12 @@ define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-NEXT: not a3, a4
; RV32I-NEXT: srl a2, a2, a3
; RV32I-NEXT: or a2, a7, a2
; RV32I-NEXT: bnez a5, .LBB13_6
; RV32I-NEXT: bnez a6, .LBB13_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB13_6:
; RV32I-NEXT: sll a0, a0, a4
; RV32I-NEXT: srli a1, a6, 1
; RV32I-NEXT: srli a1, a5, 1
; RV32I-NEXT: srl a1, a1, a3
; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2
@ -420,24 +420,24 @@ define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: .LBB15_2:
; RV32I-NEXT: srl a6, a2, a4
; RV32I-NEXT: srl a2, a2, a4
; RV32I-NEXT: beqz a5, .LBB15_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: .LBB15_4:
; RV32I-NEXT: slli a7, a3, 1
; RV32I-NEXT: not t0, a4
; RV32I-NEXT: sll a2, a7, t0
; RV32I-NEXT: or a6, a2, a6
; RV32I-NEXT: not a6, a4
; RV32I-NEXT: sll a7, a7, a6
; RV32I-NEXT: or a2, a7, a2
; RV32I-NEXT: srl a3, a3, a4
; RV32I-NEXT: beqz a5, .LBB15_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB15_6:
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: sll a0, a0, t0
; RV32I-NEXT: sll a0, a0, a6
; RV32I-NEXT: or a1, a0, a3
; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: fshr_i64:

8
llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
View File

@ -13,15 +13,15 @@ define i64 @complex_float_add(i64 %a.coerce, i64 %b.coerce) nounwind {
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: srli s2, a0, 32
; CHECK-NEXT: srli s0, a0, 32
; CHECK-NEXT: srli s1, a1, 32
; CHECK-NEXT: call __addsf3@plt
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: mv a0, s0
; CHECK-NEXT: mv a1, s1
; CHECK-NEXT: call __addsf3@plt
; CHECK-NEXT: slli a0, a0, 32
; CHECK-NEXT: slli a1, s0, 32
; CHECK-NEXT: slli a1, s2, 32
; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload

56
llvm/test/CodeGen/RISCV/rv64zbp.ll
View File

@ -2408,38 +2408,38 @@ define i64 @bitreverse_bswap_i64(i64 %a) {
; RV64I-LABEL: bitreverse_bswap_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 24
; RV64I-NEXT: lui a6, 4080
; RV64I-NEXT: and a1, a1, a6
; RV64I-NEXT: lui a2, 4080
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a3, a0, 8
; RV64I-NEXT: li a4, 255
; RV64I-NEXT: slli a7, a4, 24
; RV64I-NEXT: and a3, a3, a7
; RV64I-NEXT: slli a5, a4, 24
; RV64I-NEXT: and a3, a3, a5
; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: srli a3, a0, 40
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a3, a3, a2
; RV64I-NEXT: srli a5, a0, 56
; RV64I-NEXT: or a3, a3, a5
; RV64I-NEXT: lui a6, 16
; RV64I-NEXT: addiw a6, a6, -256
; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: srli a7, a0, 56
; RV64I-NEXT: or a3, a3, a7
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a3, a0, 24
; RV64I-NEXT: slli t0, a4, 40
; RV64I-NEXT: and a3, a3, t0
; RV64I-NEXT: srliw a5, a0, 24
; RV64I-NEXT: slli a5, a5, 32
; RV64I-NEXT: or a3, a3, a5
; RV64I-NEXT: slli a5, a0, 40
; RV64I-NEXT: slli a7, a4, 40
; RV64I-NEXT: and a3, a3, a7
; RV64I-NEXT: srliw t0, a0, 24
; RV64I-NEXT: slli t0, t0, 32
; RV64I-NEXT: or a3, a3, t0
; RV64I-NEXT: slli t0, a0, 40
; RV64I-NEXT: slli a4, a4, 48
; RV64I-NEXT: and a5, a5, a4
; RV64I-NEXT: and t0, t0, a4
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a5
; RV64I-NEXT: lui a5, %hi(.LCPI68_0)
; RV64I-NEXT: ld a5, %lo(.LCPI68_0)(a5)
; RV64I-NEXT: or a0, a0, t0
; RV64I-NEXT: lui t0, %hi(.LCPI68_0)
; RV64I-NEXT: ld t0, %lo(.LCPI68_0)(t0)
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a1, a1, a5
; RV64I-NEXT: and a0, a0, a5
; RV64I-NEXT: and a1, a1, t0
; RV64I-NEXT: and a0, a0, t0
; RV64I-NEXT: lui a3, %hi(.LCPI68_1)
; RV64I-NEXT: ld a3, %lo(.LCPI68_1)(a3)
; RV64I-NEXT: slli a0, a0, 4
@ -2457,17 +2457,17 @@ define i64 @bitreverse_bswap_i64(i64 %a) {
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 40
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a2, a0, 56
; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: srli a2, a0, 24
; RV64I-NEXT: and a2, a2, a6
; RV64I-NEXT: and a1, a1, a6
; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srli a3, a0, 24
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: srli a3, a0, 8
; RV64I-NEXT: and a3, a3, a7
; RV64I-NEXT: and a3, a3, a5
; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: slli a2, a0, 24
; RV64I-NEXT: and a2, a2, t0
; RV64I-NEXT: and a2, a2, a7
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: or a2, a2, a3

88
llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
View File

@ -103,76 +103,76 @@ define fastcc <vscale x 128 x i32> @ret_split_nxv128i32(<vscale x 128 x i32>* %x
; CHECK-NEXT: slli a2, a2, 5
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a6, a2, 3
; CHECK-NEXT: add a4, a1, a6
; CHECK-NEXT: slli a3, a2, 3
; CHECK-NEXT: add a4, a1, a3
; CHECK-NEXT: vl8re32.v v8, (a4)
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: li a4, 24
; CHECK-NEXT: mul a3, a3, a4
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; CHECK-NEXT: slli a7, a2, 4
; CHECK-NEXT: add a5, a1, a7
; CHECK-NEXT: vl8re32.v v8, (a5)
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a3, a3, 4
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: li a5, 24
; CHECK-NEXT: mul a4, a4, a5
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; CHECK-NEXT: slli a4, a2, 4
; CHECK-NEXT: add a5, a1, a4
; CHECK-NEXT: vl8re32.v v8, (a5)
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: slli a5, a5, 4
; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a5, a5, 16
; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
; CHECK-NEXT: li a5, 24
; CHECK-NEXT: mul t1, a2, a5
; CHECK-NEXT: add a3, a1, t1
; CHECK-NEXT: vl8re32.v v8, (a3)
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a3, a3, 3
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; CHECK-NEXT: slli t3, a2, 5
; CHECK-NEXT: add a4, a1, t3
; CHECK-NEXT: vl8re32.v v8, (a4)
; CHECK-NEXT: addi a3, sp, 16
; CHECK-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; CHECK-NEXT: li a4, 40
; CHECK-NEXT: mul a4, a2, a4
; CHECK-NEXT: add t0, a1, a4
; CHECK-NEXT: li a5, 48
; CHECK-NEXT: mul a5, a2, a5
; CHECK-NEXT: add t2, a1, a5
; CHECK-NEXT: li a3, 56
; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a3, a1, a2
; CHECK-NEXT: add a6, a1, a5
; CHECK-NEXT: vl8re32.v v8, (a6)
; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: slli a6, a6, 3
; CHECK-NEXT: add a6, sp, a6
; CHECK-NEXT: addi a6, a6, 16
; CHECK-NEXT: vs8r.v v8, (a6) # Unknown-size Folded Spill
; CHECK-NEXT: slli a6, a2, 5
; CHECK-NEXT: add a7, a1, a6
; CHECK-NEXT: vl8re32.v v8, (a7)
; CHECK-NEXT: addi a7, sp, 16
; CHECK-NEXT: vs8r.v v8, (a7) # Unknown-size Folded Spill
; CHECK-NEXT: li a7, 40
; CHECK-NEXT: mul a7, a2, a7
; CHECK-NEXT: add t0, a1, a7
; CHECK-NEXT: li t1, 48
; CHECK-NEXT: mul t1, a2, t1
; CHECK-NEXT: add t2, a1, t1
; CHECK-NEXT: li t3, 56
; CHECK-NEXT: mul a2, a2, t3
; CHECK-NEXT: add t3, a1, a2
; CHECK-NEXT: vl8re32.v v8, (a1)
; CHECK-NEXT: vl8re32.v v0, (t0)
; CHECK-NEXT: vl8re32.v v16, (a3)
; CHECK-NEXT: vl8re32.v v16, (t3)
; CHECK-NEXT: vl8re32.v v24, (t2)
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: add a1, a0, a2
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: add a1, a0, a5
; CHECK-NEXT: add a1, a0, t1
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: add a1, a0, a4
; CHECK-NEXT: add a1, a0, a7
; CHECK-NEXT: vs8r.v v0, (a1)
; CHECK-NEXT: add a1, a0, t3
; CHECK-NEXT: add a1, a0, a6
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: add a1, a0, t1
; CHECK-NEXT: add a1, a0, a5
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: add a1, a0, a7
; CHECK-NEXT: add a1, a0, a4
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: add a0, a0, a6
; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a2, 24
; CHECK-NEXT: mul a1, a1, a2

88
llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
View File

@ -32,17 +32,17 @@ define void @gather(i8* noalias nocapture %A, i8* noalias nocapture readonly %B)
; CHECK-ASM-LABEL: gather:
; CHECK-ASM: # %bb.0: # %entry
; CHECK-ASM-NEXT: li a2, 0
; CHECK-ASM-NEXT: li a6, 32
; CHECK-ASM-NEXT: li a3, 32
; CHECK-ASM-NEXT: li a4, 5
; CHECK-ASM-NEXT: li a5, 1024
; CHECK-ASM-NEXT: .LBB0_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu
; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu
; CHECK-ASM-NEXT: vlse8.v v8, (a1), a4
; CHECK-ASM-NEXT: add a3, a0, a2
; CHECK-ASM-NEXT: vle8.v v9, (a3)
; CHECK-ASM-NEXT: add a6, a0, a2
; CHECK-ASM-NEXT: vle8.v v9, (a6)
; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
; CHECK-ASM-NEXT: vse8.v v8, (a3)
; CHECK-ASM-NEXT: vse8.v v8, (a6)
; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a1, a1, 160
; CHECK-ASM-NEXT: bne a2, a5, .LBB0_1
@ -101,18 +101,18 @@ define void @gather_masked(i8* noalias nocapture %A, i8* noalias nocapture reado
; CHECK-ASM-NEXT: addiw a3, a3, 873
; CHECK-ASM-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-ASM-NEXT: vmv.s.x v0, a3
; CHECK-ASM-NEXT: li a6, 32
; CHECK-ASM-NEXT: li a3, 32
; CHECK-ASM-NEXT: li a4, 5
; CHECK-ASM-NEXT: li a5, 1024
; CHECK-ASM-NEXT: .LBB1_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu
; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu
; CHECK-ASM-NEXT: vmv1r.v v9, v8
; CHECK-ASM-NEXT: vlse8.v v9, (a1), a4, v0.t
; CHECK-ASM-NEXT: add a3, a0, a2
; CHECK-ASM-NEXT: vle8.v v10, (a3)
; CHECK-ASM-NEXT: add a6, a0, a2
; CHECK-ASM-NEXT: vle8.v v10, (a6)
; CHECK-ASM-NEXT: vadd.vv v9, v10, v9
; CHECK-ASM-NEXT: vse8.v v9, (a3)
; CHECK-ASM-NEXT: vse8.v v9, (a6)
; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a1, a1, 160
; CHECK-ASM-NEXT: bne a2, a5, .LBB1_1
@ -168,17 +168,17 @@ define void @gather_negative_stride(i8* noalias nocapture %A, i8* noalias nocapt
; CHECK-ASM: # %bb.0: # %entry
; CHECK-ASM-NEXT: li a2, 0
; CHECK-ASM-NEXT: addi a1, a1, 155
; CHECK-ASM-NEXT: li a6, 32
; CHECK-ASM-NEXT: li a3, 32
; CHECK-ASM-NEXT: li a4, -5
; CHECK-ASM-NEXT: li a5, 1024
; CHECK-ASM-NEXT: .LBB2_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu
; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu
; CHECK-ASM-NEXT: vlse8.v v8, (a1), a4
; CHECK-ASM-NEXT: add a3, a0, a2
; CHECK-ASM-NEXT: vle8.v v9, (a3)
; CHECK-ASM-NEXT: add a6, a0, a2
; CHECK-ASM-NEXT: vle8.v v9, (a6)
; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
; CHECK-ASM-NEXT: vse8.v v8, (a3)
; CHECK-ASM-NEXT: vse8.v v8, (a6)
; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a1, a1, 160
; CHECK-ASM-NEXT: bne a2, a5, .LBB2_1
@ -303,14 +303,14 @@ define void @scatter(i8* noalias nocapture %A, i8* noalias nocapture readonly %B
; CHECK-ASM-LABEL: scatter:
; CHECK-ASM: # %bb.0: # %entry
; CHECK-ASM-NEXT: li a2, 0
; CHECK-ASM-NEXT: li a6, 32
; CHECK-ASM-NEXT: li a3, 32
; CHECK-ASM-NEXT: li a4, 5
; CHECK-ASM-NEXT: li a5, 1024
; CHECK-ASM-NEXT: .LBB4_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: add a3, a1, a2
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu
; CHECK-ASM-NEXT: vle8.v v8, (a3)
; CHECK-ASM-NEXT: add a6, a1, a2
; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu
; CHECK-ASM-NEXT: vle8.v v8, (a6)
; CHECK-ASM-NEXT: vlse8.v v9, (a0), a4
; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
; CHECK-ASM-NEXT: vsse8.v v8, (a0), a4
@ -369,7 +369,7 @@ define void @scatter_masked(i8* noalias nocapture %A, i8* noalias nocapture read
; CHECK-ASM-LABEL: scatter_masked:
; CHECK-ASM: # %bb.0: # %entry
; CHECK-ASM-NEXT: li a2, 0
; CHECK-ASM-NEXT: li a6, 32
; CHECK-ASM-NEXT: li a3, 32
; CHECK-ASM-NEXT: lui a4, 983765
; CHECK-ASM-NEXT: addiw a4, a4, 873
; CHECK-ASM-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
@ -378,9 +378,9 @@ define void @scatter_masked(i8* noalias nocapture %A, i8* noalias nocapture read
; CHECK-ASM-NEXT: li a5, 1024
; CHECK-ASM-NEXT: .LBB5_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: add a3, a1, a2
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu
; CHECK-ASM-NEXT: vle8.v v9, (a3)
; CHECK-ASM-NEXT: add a6, a1, a2
; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu
; CHECK-ASM-NEXT: vle8.v v9, (a6)
; CHECK-ASM-NEXT: vmv1r.v v10, v8
; CHECK-ASM-NEXT: vlse8.v v10, (a0), a4, v0.t
; CHECK-ASM-NEXT: vadd.vv v9, v10, v9
@ -1047,43 +1047,43 @@ define void @strided_load_startval_add_with_splat(i8* noalias nocapture %0, i8*
; CHECK-ASM-NEXT: # %bb.2:
; CHECK-ASM-NEXT: slli a3, a4, 32
; CHECK-ASM-NEXT: srli a3, a3, 32
; CHECK-ASM-NEXT: addi a6, a3, 1
; CHECK-ASM-NEXT: andi a7, a6, -32
; CHECK-ASM-NEXT: add a3, a7, a2
; CHECK-ASM-NEXT: slli a4, a2, 2
; CHECK-ASM-NEXT: add a4, a4, a2
; CHECK-ASM-NEXT: addi a4, a3, 1
; CHECK-ASM-NEXT: andi a5, a4, -32
; CHECK-ASM-NEXT: add a3, a5, a2
; CHECK-ASM-NEXT: slli a6, a2, 2
; CHECK-ASM-NEXT: add a6, a6, a2
; CHECK-ASM-NEXT: add a2, a0, a2
; CHECK-ASM-NEXT: add a4, a1, a4
; CHECK-ASM-NEXT: li t0, 32
; CHECK-ASM-NEXT: li t1, 5
; CHECK-ASM-NEXT: mv a5, a7
; CHECK-ASM-NEXT: add a6, a1, a6
; CHECK-ASM-NEXT: li a7, 32
; CHECK-ASM-NEXT: li t0, 5
; CHECK-ASM-NEXT: mv t1, a5
; CHECK-ASM-NEXT: .LBB12_3: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetvli zero, t0, e8, m1, ta, mu
; CHECK-ASM-NEXT: vlse8.v v8, (a4), t1
; CHECK-ASM-NEXT: vsetvli zero, a7, e8, m1, ta, mu
; CHECK-ASM-NEXT: vlse8.v v8, (a6), t0
; CHECK-ASM-NEXT: vle8.v v9, (a2)
; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
; CHECK-ASM-NEXT: vse8.v v8, (a2)
; CHECK-ASM-NEXT: addi a5, a5, -32
; CHECK-ASM-NEXT: addi t1, t1, -32
; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a4, a4, 160
; CHECK-ASM-NEXT: bnez a5, .LBB12_3
; CHECK-ASM-NEXT: addi a6, a6, 160
; CHECK-ASM-NEXT: bnez t1, .LBB12_3
; CHECK-ASM-NEXT: # %bb.4:
; CHECK-ASM-NEXT: beq a6, a7, .LBB12_7
; CHECK-ASM-NEXT: beq a4, a5, .LBB12_7
; CHECK-ASM-NEXT: .LBB12_5:
; CHECK-ASM-NEXT: slli a2, a3, 2
; CHECK-ASM-NEXT: add a2, a2, a3
; CHECK-ASM-NEXT: add a1, a1, a2
; CHECK-ASM-NEXT: li a6, 1024
; CHECK-ASM-NEXT: li a2, 1024
; CHECK-ASM-NEXT: .LBB12_6: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: lb a4, 0(a1)
; CHECK-ASM-NEXT: add a5, a0, a3
; CHECK-ASM-NEXT: lb a2, 0(a5)
; CHECK-ASM-NEXT: addw a2, a2, a4
; CHECK-ASM-NEXT: sb a2, 0(a5)
; CHECK-ASM-NEXT: addiw a2, a3, 1
; CHECK-ASM-NEXT: lb a6, 0(a5)
; CHECK-ASM-NEXT: addw a4, a6, a4
; CHECK-ASM-NEXT: sb a4, 0(a5)
; CHECK-ASM-NEXT: addiw a4, a3, 1
; CHECK-ASM-NEXT: addi a3, a3, 1
; CHECK-ASM-NEXT: addi a1, a1, 5
; CHECK-ASM-NEXT: bne a2, a6, .LBB12_6
; CHECK-ASM-NEXT: bne a4, a2, .LBB12_6
; CHECK-ASM-NEXT: .LBB12_7:
; CHECK-ASM-NEXT: ret
%4 = icmp eq i32 %2, 1024

174
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
View File

@ -866,8 +866,8 @@ define void @bitreverse_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsll.vi v11, v8, 8
; LMULMAX1-RV32-NEXT: lui a6, 4080
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a6
; LMULMAX1-RV32-NEXT: lui a3, 4080
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
@ -886,10 +886,10 @@ define void @bitreverse_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2
; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV32-NEXT: lui a3, 349525
; LMULMAX1-RV32-NEXT: addi a3, a3, 1365
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a3
; LMULMAX1-RV32-NEXT: lui a6, 349525
; LMULMAX1-RV32-NEXT: addi a6, a6, 1365
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a6
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a6
; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8
; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8
@ -897,7 +897,7 @@ define void @bitreverse_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsll.vi v11, v9, 8
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a6
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 24
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
@ -912,8 +912,8 @@ define void @bitreverse_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 2
; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a3
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a6
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a6
; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v9
; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV32-NEXT: vse32.v v9, (a0)
@ -933,8 +933,8 @@ define void @bitreverse_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8
; LMULMAX1-RV64-NEXT: lui a6, 4080
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6
; LMULMAX1-RV64-NEXT: lui a3, 4080
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
@ -953,10 +953,10 @@ define void @bitreverse_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: lui a3, 349525
; LMULMAX1-RV64-NEXT: addiw a3, a3, 1365
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3
; LMULMAX1-RV64-NEXT: lui a6, 349525
; LMULMAX1-RV64-NEXT: addiw a6, a6, 1365
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a6
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8
@ -964,7 +964,7 @@ define void @bitreverse_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 24
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
@ -979,8 +979,8 @@ define void @bitreverse_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a6
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vse32.v v9, (a0)
@ -1153,23 +1153,23 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v12, 24
; LMULMAX1-RV32-NEXT: lui a6, 4080
; LMULMAX1-RV32-NEXT: vand.vx v11, v9, a6
; LMULMAX1-RV32-NEXT: li a5, 5
; LMULMAX1-RV32-NEXT: lui a5, 4080
; LMULMAX1-RV32-NEXT: vand.vx v11, v9, a5
; LMULMAX1-RV32-NEXT: li a6, 5
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a5
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.i v9, 0
; LMULMAX1-RV32-NEXT: lui a5, 1044480
; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a5, v0
; LMULMAX1-RV32-NEXT: lui a6, 1044480
; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a6, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 8
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v9
; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11
; LMULMAX1-RV32-NEXT: vor.vv v13, v11, v10
; LMULMAX1-RV32-NEXT: li a5, 255
; LMULMAX1-RV32-NEXT: li a6, 255
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v10, a5
; LMULMAX1-RV32-NEXT: vmv.v.x v10, a6
; LMULMAX1-RV32-NEXT: vmerge.vim v10, v10, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vsll.vi v11, v12, 8
@ -1183,7 +1183,7 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: vor.vv v14, v15, v14
; LMULMAX1-RV32-NEXT: vsll.vx v15, v12, a3
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v16, a6
; LMULMAX1-RV32-NEXT: vmv.v.x v16, a5
; LMULMAX1-RV32-NEXT: vmerge.vim v16, v16, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v16
@ -1192,30 +1192,30 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v14
; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 4
; LMULMAX1-RV32-NEXT: lui a5, 61681
; LMULMAX1-RV32-NEXT: addi a5, a5, -241
; LMULMAX1-RV32-NEXT: lui a6, 61681
; LMULMAX1-RV32-NEXT: addi a6, a6, -241
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v14, a5
; LMULMAX1-RV32-NEXT: vmv.v.x v14, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v14
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v14
; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 4
; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 2
; LMULMAX1-RV32-NEXT: lui a5, 209715
; LMULMAX1-RV32-NEXT: addi a5, a5, 819
; LMULMAX1-RV32-NEXT: lui a6, 209715
; LMULMAX1-RV32-NEXT: addi a6, a6, 819
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v15, a5
; LMULMAX1-RV32-NEXT: vmv.v.x v15, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v15
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v15
; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 2
; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 1
; LMULMAX1-RV32-NEXT: lui a5, 349525
; LMULMAX1-RV32-NEXT: addi a5, a5, 1365
; LMULMAX1-RV32-NEXT: lui a6, 349525
; LMULMAX1-RV32-NEXT: addi a6, a6, 1365
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v17, a5
; LMULMAX1-RV32-NEXT: vmv.v.x v17, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v17
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v17
@ -1226,7 +1226,7 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: vand.vx v18, v18, a4
; LMULMAX1-RV32-NEXT: vor.vv v13, v18, v13
; LMULMAX1-RV32-NEXT: vsrl.vi v18, v8, 24
; LMULMAX1-RV32-NEXT: vand.vx v18, v18, a6
; LMULMAX1-RV32-NEXT: vand.vx v18, v18, a5
; LMULMAX1-RV32-NEXT: vsrl.vi v19, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v9, v19, v9
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v18
@ -1264,99 +1264,99 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-LABEL: bitreverse_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a7, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v9, (a7)
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v9, (a1)
; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: li t0, 56
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, t0
; LMULMAX1-RV64-NEXT: li t1, 40
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, t1
; LMULMAX1-RV64-NEXT: li a2, 56
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: li a3, 40
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, a3
; LMULMAX1-RV64-NEXT: lui a4, 16
; LMULMAX1-RV64-NEXT: addiw t2, a4, -256
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t2
; LMULMAX1-RV64-NEXT: addiw a4, a4, -256
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV64-NEXT: lui a6, 4080
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6
; LMULMAX1-RV64-NEXT: lui a5, 4080
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v9, 8
; LMULMAX1-RV64-NEXT: li a5, 255
; LMULMAX1-RV64-NEXT: slli t3, a5, 24
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t3
; LMULMAX1-RV64-NEXT: li a6, 255
; LMULMAX1-RV64-NEXT: slli a7, a6, 24
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a7
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8
; LMULMAX1-RV64-NEXT: slli t4, a5, 32
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t4
; LMULMAX1-RV64-NEXT: slli t0, a6, 32
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t0
; LMULMAX1-RV64-NEXT: vsll.vi v12, v9, 24
; LMULMAX1-RV64-NEXT: slli a3, a5, 40
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a3
; LMULMAX1-RV64-NEXT: slli t1, a6, 40
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t1
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, t0
; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, t1
; LMULMAX1-RV64-NEXT: slli a5, a5, 48
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, a2
; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, a3
; LMULMAX1-RV64-NEXT: slli a6, a6, 48
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vor.vv v9, v12, v9
; LMULMAX1-RV64-NEXT: lui a4, %hi(.LCPI5_0)
; LMULMAX1-RV64-NEXT: ld a4, %lo(.LCPI5_0)(a4)
; LMULMAX1-RV64-NEXT: lui t2, %hi(.LCPI5_0)
; LMULMAX1-RV64-NEXT: ld t2, %lo(.LCPI5_0)(t2)
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
; LMULMAX1-RV64-NEXT: lui a1, %hi(.LCPI5_1)
; LMULMAX1-RV64-NEXT: ld a1, %lo(.LCPI5_1)(a1)
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t2
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, t2
; LMULMAX1-RV64-NEXT: lui t3, %hi(.LCPI5_1)
; LMULMAX1-RV64-NEXT: ld t3, %lo(.LCPI5_1)(t3)
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI5_2)
; LMULMAX1-RV64-NEXT: ld a2, %lo(.LCPI5_2)(a2)
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t3
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, t3
; LMULMAX1-RV64-NEXT: lui t4, %hi(.LCPI5_2)
; LMULMAX1-RV64-NEXT: ld t4, %lo(.LCPI5_2)(t4)
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a2
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t4
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, t4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, t0
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, t1
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t2
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, a3
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v8, 8
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t3
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a7
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t4
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t0
; LMULMAX1-RV64-NEXT: vsll.vi v12, v8, 24
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a3
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t1
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, t0
; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, t1
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, a2
; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, a3
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: vor.vv v8, v12, v8
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t2
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, t2
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t3
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, t3
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a2
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t4
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, t4
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v9, (a7)
; LMULMAX1-RV64-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y

80
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
View File

@ -595,8 +595,8 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle64.v v9, (a1)
; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: li a6, 56
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a6
; LMULMAX1-RV32-NEXT: li a2, 56
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a2
; LMULMAX1-RV32-NEXT: li a3, 40
; LMULMAX1-RV32-NEXT: vsrl.vx v11, v9, a3
; LMULMAX1-RV32-NEXT: lui a4, 16
@ -606,21 +606,21 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV32-NEXT: lui a5, 4080
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV32-NEXT: li a2, 5
; LMULMAX1-RV32-NEXT: li a6, 5
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.i v12, 0
; LMULMAX1-RV32-NEXT: lui a2, 1044480
; LMULMAX1-RV32-NEXT: vmerge.vxm v12, v12, a2, v0
; LMULMAX1-RV32-NEXT: lui a6, 1044480
; LMULMAX1-RV32-NEXT: vmerge.vxm v12, v12, a6, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v9, 8
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v12
; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV32-NEXT: li a2, 255
; LMULMAX1-RV32-NEXT: li a6, 255
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v11, a2
; LMULMAX1-RV32-NEXT: vmv.v.x v11, a6
; LMULMAX1-RV32-NEXT: vmerge.vim v11, v11, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vsll.vi v13, v9, 8
@ -638,11 +638,11 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: vmerge.vim v16, v16, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v16
; LMULMAX1-RV32-NEXT: vsll.vx v9, v9, a6
; LMULMAX1-RV32-NEXT: vsll.vx v9, v9, a2
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v15
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v13
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v8, a6
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV32-NEXT: vsrl.vx v13, v8, a3
; LMULMAX1-RV32-NEXT: vand.vx v13, v13, a4
; LMULMAX1-RV32-NEXT: vor.vv v10, v13, v10
@ -659,7 +659,7 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV32-NEXT: vsll.vx v12, v8, a3
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v16
; LMULMAX1-RV32-NEXT: vsll.vx v8, v8, a6
; LMULMAX1-RV32-NEXT: vsll.vx v8, v8, a2
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v12
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
@ -670,63 +670,63 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV64-LABEL: bswap_v4i64:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi t1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v8, (t1)
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle64.v v9, (a0)
; LMULMAX1-RV64-NEXT: li a7, 56
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a7
; LMULMAX1-RV64-NEXT: li t0, 40
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, t0
; LMULMAX1-RV64-NEXT: li a2, 56
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: li a3, 40
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, a3
; LMULMAX1-RV64-NEXT: lui a4, 16
; LMULMAX1-RV64-NEXT: addiw a4, a4, -256
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: lui a6, 4080
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6
; LMULMAX1-RV64-NEXT: lui a5, 4080
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v8, 8
; LMULMAX1-RV64-NEXT: li a5, 255
; LMULMAX1-RV64-NEXT: slli a2, a5, 24
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a2
; LMULMAX1-RV64-NEXT: li a6, 255
; LMULMAX1-RV64-NEXT: slli a7, a6, 24
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a7
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8
; LMULMAX1-RV64-NEXT: slli a3, a5, 32
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV64-NEXT: slli t0, a6, 32
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t0
; LMULMAX1-RV64-NEXT: vsll.vi v12, v8, 24
; LMULMAX1-RV64-NEXT: slli a1, a5, 40
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a1
; LMULMAX1-RV64-NEXT: slli t1, a6, 40
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t1
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, a7
; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, t0
; LMULMAX1-RV64-NEXT: slli a5, a5, 48
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, a2
; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, a3
; LMULMAX1-RV64-NEXT: slli a6, a6, 48
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: vor.vv v8, v12, v8
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a7
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, t0
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, a3
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v9, 8
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a2
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a7
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t0
; LMULMAX1-RV64-NEXT: vsll.vi v12, v9, 24
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a1
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t1
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, a7
; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, t0
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, a2
; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, a3
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vor.vv v9, v12, v9
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v8, (t1)
; LMULMAX1-RV64-NEXT: vse64.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y

14
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
View File

@ -1746,8 +1746,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) nounwind {
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 16
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: li a6, 32
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a6
; LMULMAX1-RV64-NEXT: li a2, 32
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vxor.vi v8, v8, -1
; LMULMAX1-RV64-NEXT: lui a3, %hi(.LCPI7_0)
@ -1763,12 +1763,12 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) nounwind {
; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: lui a5, %hi(.LCPI7_2)
; LMULMAX1-RV64-NEXT: ld a5, %lo(.LCPI7_2)(a5)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI7_3)
; LMULMAX1-RV64-NEXT: ld a2, %lo(.LCPI7_3)(a2)
; LMULMAX1-RV64-NEXT: lui a6, %hi(.LCPI7_3)
; LMULMAX1-RV64-NEXT: ld a6, %lo(.LCPI7_3)(a6)
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a2
; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: li a7, 56
; LMULMAX1-RV64-NEXT: vsrl.vx v8, v8, a7
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
@ -1781,7 +1781,7 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) nounwind {
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 16
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a6
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vxor.vi v9, v9, -1
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
@ -1794,7 +1794,7 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) nounwind {
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a2
; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vsrl.vx v9, v9, a7
; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v8, (a1)

66
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
View File

@ -1030,8 +1030,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) nounwind {
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle16.v v8, (a1)
; LMULMAX1-RV32-NEXT: vle16.v v9, (a0)
; LMULMAX1-RV32-NEXT: li a6, 1
; LMULMAX1-RV32-NEXT: vsub.vx v10, v8, a6
; LMULMAX1-RV32-NEXT: li a2, 1
; LMULMAX1-RV32-NEXT: vsub.vx v10, v8, a2
; LMULMAX1-RV32-NEXT: vxor.vi v8, v8, -1
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
@ -1050,10 +1050,10 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) nounwind {
; LMULMAX1-RV32-NEXT: lui a5, 1
; LMULMAX1-RV32-NEXT: addi a5, a5, -241
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV32-NEXT: li a2, 257
; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a2
; LMULMAX1-RV32-NEXT: li a6, 257
; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a6
; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 8
; LMULMAX1-RV32-NEXT: vsub.vx v10, v9, a6
; LMULMAX1-RV32-NEXT: vsub.vx v10, v9, a2
; LMULMAX1-RV32-NEXT: vxor.vi v9, v9, -1
; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1
@ -1066,7 +1066,7 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) nounwind {
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV32-NEXT: vmul.vx v9, v9, a2
; LMULMAX1-RV32-NEXT: vmul.vx v9, v9, a6
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 8
; LMULMAX1-RV32-NEXT: vse16.v v9, (a0)
; LMULMAX1-RV32-NEXT: vse16.v v8, (a1)
@ -1078,8 +1078,8 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) nounwind {
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle16.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle16.v v9, (a0)
; LMULMAX1-RV64-NEXT: li a6, 1
; LMULMAX1-RV64-NEXT: vsub.vx v10, v8, a6
; LMULMAX1-RV64-NEXT: li a2, 1
; LMULMAX1-RV64-NEXT: vsub.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: vxor.vi v8, v8, -1
; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
@ -1098,10 +1098,10 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) nounwind {
; LMULMAX1-RV64-NEXT: lui a5, 1
; LMULMAX1-RV64-NEXT: addiw a5, a5, -241
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: li a2, 257
; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a2
; LMULMAX1-RV64-NEXT: li a6, 257
; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 8
; LMULMAX1-RV64-NEXT: vsub.vx v10, v9, a6
; LMULMAX1-RV64-NEXT: vsub.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: vxor.vi v9, v9, -1
; LMULMAX1-RV64-NEXT: vand.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
@ -1114,7 +1114,7 @@ define void @cttz_v16i16(<16 x i16>* %x, <16 x i16>* %y) nounwind {
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a2
; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 8
; LMULMAX1-RV64-NEXT: vse16.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse16.v v8, (a1)
@ -1228,8 +1228,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) nounwind {
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV32-NEXT: li a6, 1
; LMULMAX1-RV32-NEXT: vsub.vx v10, v8, a6
; LMULMAX1-RV32-NEXT: li a2, 1
; LMULMAX1-RV32-NEXT: vsub.vx v10, v8, a2
; LMULMAX1-RV32-NEXT: vxor.vi v8, v8, -1
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
@ -1248,11 +1248,11 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) nounwind {
; LMULMAX1-RV32-NEXT: lui a5, 61681
; LMULMAX1-RV32-NEXT: addi a5, a5, -241
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV32-NEXT: lui a2, 4112
; LMULMAX1-RV32-NEXT: addi a2, a2, 257
; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a2
; LMULMAX1-RV32-NEXT: lui a6, 4112
; LMULMAX1-RV32-NEXT: addi a6, a6, 257
; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a6
; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 24
; LMULMAX1-RV32-NEXT: vsub.vx v10, v9, a6
; LMULMAX1-RV32-NEXT: vsub.vx v10, v9, a2
; LMULMAX1-RV32-NEXT: vxor.vi v9, v9, -1
; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1
@ -1265,7 +1265,7 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) nounwind {
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV32-NEXT: vmul.vx v9, v9, a2
; LMULMAX1-RV32-NEXT: vmul.vx v9, v9, a6
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 24
; LMULMAX1-RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1-RV32-NEXT: vse32.v v8, (a1)
@ -1277,8 +1277,8 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) nounwind {
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV64-NEXT: li a6, 1
; LMULMAX1-RV64-NEXT: vsub.vx v10, v8, a6
; LMULMAX1-RV64-NEXT: li a2, 1
; LMULMAX1-RV64-NEXT: vsub.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: vxor.vi v8, v8, -1
; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
@ -1297,11 +1297,11 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) nounwind {
; LMULMAX1-RV64-NEXT: lui a5, 61681
; LMULMAX1-RV64-NEXT: addiw a5, a5, -241
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: lui a2, 4112
; LMULMAX1-RV64-NEXT: addiw a2, a2, 257
; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a2
; LMULMAX1-RV64-NEXT: lui a6, 4112
; LMULMAX1-RV64-NEXT: addiw a6, a6, 257
; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 24
; LMULMAX1-RV64-NEXT: vsub.vx v10, v9, a6
; LMULMAX1-RV64-NEXT: vsub.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: vxor.vi v9, v9, -1
; LMULMAX1-RV64-NEXT: vand.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
@ -1314,7 +1314,7 @@ define void @cttz_v8i32(<8 x i32>* %x, <8 x i32>* %y) nounwind {
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a2
; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 24
; LMULMAX1-RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse32.v v8, (a1)
@ -1512,8 +1512,8 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) nounwind {
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle64.v v9, (a0)
; LMULMAX1-RV64-NEXT: li a6, 1
; LMULMAX1-RV64-NEXT: vsub.vx v10, v8, a6
; LMULMAX1-RV64-NEXT: li a2, 1
; LMULMAX1-RV64-NEXT: vsub.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: vxor.vi v8, v8, -1
; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: lui a3, %hi(.LCPI7_0)
@ -1529,15 +1529,15 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) nounwind {
; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: lui a5, %hi(.LCPI7_2)
; LMULMAX1-RV64-NEXT: ld a5, %lo(.LCPI7_2)(a5)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI7_3)
; LMULMAX1-RV64-NEXT: ld a2, %lo(.LCPI7_3)(a2)
; LMULMAX1-RV64-NEXT: lui a6, %hi(.LCPI7_3)
; LMULMAX1-RV64-NEXT: ld a6, %lo(.LCPI7_3)(a6)
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a2
; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: li a7, 56
; LMULMAX1-RV64-NEXT: vsrl.vx v8, v8, a7
; LMULMAX1-RV64-NEXT: vsub.vx v10, v9, a6
; LMULMAX1-RV64-NEXT: vsub.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: vxor.vi v9, v9, -1
; LMULMAX1-RV64-NEXT: vand.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
@ -1550,7 +1550,7 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) nounwind {
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a2
; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vsrl.vx v9, v9, a7
; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v8, (a1)

28
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
View File

@ -29,25 +29,25 @@ define void @add_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; RV32-LABEL: add_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: lw a2, 8(a0)
; RV32-NEXT: lw a6, 12(a0)
; RV32-NEXT: lw a3, 12(a0)
; RV32-NEXT: lw a4, 0(a0)
; RV32-NEXT: lw a7, 4(a0)
; RV32-NEXT: lw a3, 4(a1)
; RV32-NEXT: lw a5, 0(a1)
; RV32-NEXT: lw a5, 4(a0)
; RV32-NEXT: lw a6, 4(a1)
; RV32-NEXT: lw a7, 0(a1)
; RV32-NEXT: lw t0, 8(a1)
; RV32-NEXT: lw a1, 12(a1)
; RV32-NEXT: add a3, a7, a3
; RV32-NEXT: add a5, a4, a5
; RV32-NEXT: sltu a4, a5, a4
; RV32-NEXT: add a3, a3, a4
; RV32-NEXT: add a1, a6, a1
; RV32-NEXT: add a4, a2, t0
; RV32-NEXT: sltu a2, a4, a2
; RV32-NEXT: add a5, a5, a6
; RV32-NEXT: add a6, a4, a7
; RV32-NEXT: sltu a4, a6, a4
; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a3, a2, t0
; RV32-NEXT: sltu a2, a3, a2
; RV32-NEXT: add a1, a1, a2
; RV32-NEXT: sw a4, 8(a0)
; RV32-NEXT: sw a5, 0(a0)
; RV32-NEXT: sw a3, 8(a0)
; RV32-NEXT: sw a6, 0(a0)
; RV32-NEXT: sw a1, 12(a0)
; RV32-NEXT: sw a3, 4(a0)
; RV32-NEXT: sw a4, 4(a0)
; RV32-NEXT: ret
;
; RV64-LABEL: add_v2i64:

48
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
View File

@ -63,24 +63,24 @@ define void @gather_const_v64f16(<64 x half>* %x) {
;
; LMULMAX1-LABEL: gather_const_v64f16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a6, a0, 16
; LMULMAX1-NEXT: addi a7, a0, 48
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: addi a3, a0, 32
; LMULMAX1-NEXT: addi a4, a0, 80
; LMULMAX1-NEXT: addi a5, a0, 94
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vlse16.v v8, (a5), zero
; LMULMAX1-NEXT: addi a5, a0, 64
; LMULMAX1-NEXT: addi a1, a0, 112
; LMULMAX1-NEXT: addi a2, a0, 96
; LMULMAX1-NEXT: vse16.v v8, (a2)
; LMULMAX1-NEXT: vse16.v v8, (a1)
; LMULMAX1-NEXT: addi a6, a0, 112
; LMULMAX1-NEXT: addi a7, a0, 96
; LMULMAX1-NEXT: vse16.v v8, (a7)
; LMULMAX1-NEXT: vse16.v v8, (a6)
; LMULMAX1-NEXT: vse16.v v8, (a5)
; LMULMAX1-NEXT: vse16.v v8, (a4)
; LMULMAX1-NEXT: vse16.v v8, (a3)
; LMULMAX1-NEXT: vse16.v v8, (a7)
; LMULMAX1-NEXT: vse16.v v8, (a2)
; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: vse16.v v8, (a6)
; LMULMAX1-NEXT: vse16.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = extractelement <64 x half> %a, i32 47
@ -102,24 +102,24 @@ define void @gather_const_v32f32(<32 x float>* %x) {
;
; LMULMAX1-LABEL: gather_const_v32f32:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a6, a0, 16
; LMULMAX1-NEXT: addi a7, a0, 48
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: addi a3, a0, 32
; LMULMAX1-NEXT: addi a4, a0, 80
; LMULMAX1-NEXT: addi a5, a0, 68
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vlse32.v v8, (a5), zero
; LMULMAX1-NEXT: addi a5, a0, 64
; LMULMAX1-NEXT: addi a1, a0, 112
; LMULMAX1-NEXT: addi a2, a0, 96
; LMULMAX1-NEXT: vse32.v v8, (a2)
; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: addi a6, a0, 112
; LMULMAX1-NEXT: addi a7, a0, 96
; LMULMAX1-NEXT: vse32.v v8, (a7)
; LMULMAX1-NEXT: vse32.v v8, (a6)
; LMULMAX1-NEXT: vse32.v v8, (a5)
; LMULMAX1-NEXT: vse32.v v8, (a4)
; LMULMAX1-NEXT: vse32.v v8, (a3)
; LMULMAX1-NEXT: vse32.v v8, (a7)
; LMULMAX1-NEXT: vse32.v v8, (a2)
; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: vse32.v v8, (a6)
; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = extractelement <32 x float> %a, i32 17
@ -140,23 +140,23 @@ define void @gather_const_v16f64(<16 x double>* %x) {
;
; LMULMAX1-LABEL: gather_const_v16f64:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a6, a0, 16
; LMULMAX1-NEXT: addi a7, a0, 48
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: addi a3, a0, 32
; LMULMAX1-NEXT: addi a4, a0, 80
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-NEXT: vlse64.v v8, (a4), zero
; LMULMAX1-NEXT: addi a5, a0, 64
; LMULMAX1-NEXT: addi a1, a0, 112
; LMULMAX1-NEXT: addi a2, a0, 96
; LMULMAX1-NEXT: vse64.v v8, (a2)
; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: addi a6, a0, 112
; LMULMAX1-NEXT: addi a7, a0, 96
; LMULMAX1-NEXT: vse64.v v8, (a7)
; LMULMAX1-NEXT: vse64.v v8, (a6)
; LMULMAX1-NEXT: vse64.v v8, (a5)
; LMULMAX1-NEXT: vse64.v v8, (a4)
; LMULMAX1-NEXT: vse64.v v8, (a3)
; LMULMAX1-NEXT: vse64.v v8, (a7)
; LMULMAX1-NEXT: vse64.v v8, (a2)
; LMULMAX1-NEXT: vse64.v v8, (a0)
; LMULMAX1-NEXT: vse64.v v8, (a6)
; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = extractelement <16 x double> %a, i32 10

32
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
View File

@ -548,16 +548,16 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
; RV32-NEXT: andi a3, a2, 1
; RV32-NEXT: beqz a3, .LBB8_2
; RV32-NEXT: # %bb.1: # %cond.load
; RV32-NEXT: lbu a6, 1(a0)
; RV32-NEXT: lbu a7, 0(a0)
; RV32-NEXT: lbu a3, 1(a0)
; RV32-NEXT: lbu a4, 0(a0)
; RV32-NEXT: lbu a5, 3(a0)
; RV32-NEXT: lbu a3, 2(a0)
; RV32-NEXT: slli a4, a6, 8
; RV32-NEXT: or a4, a4, a7
; RV32-NEXT: slli a5, a5, 8
; RV32-NEXT: or a3, a5, a3
; RV32-NEXT: slli a3, a3, 16
; RV32-NEXT: lbu a6, 2(a0)
; RV32-NEXT: slli a3, a3, 8
; RV32-NEXT: or a3, a3, a4
; RV32-NEXT: slli a4, a5, 8
; RV32-NEXT: or a4, a4, a6
; RV32-NEXT: slli a4, a4, 16
; RV32-NEXT: or a3, a4, a3
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vmv.v.x v8, a3
; RV32-NEXT: andi a2, a2, 2
@ -608,16 +608,16 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
; RV64-NEXT: andi a3, a2, 1
; RV64-NEXT: beqz a3, .LBB8_2
; RV64-NEXT: # %bb.1: # %cond.load
; RV64-NEXT: lbu a6, 1(a0)
; RV64-NEXT: lbu a7, 0(a0)
; RV64-NEXT: lbu a3, 1(a0)
; RV64-NEXT: lbu a4, 0(a0)
; RV64-NEXT: lb a5, 3(a0)
; RV64-NEXT: lbu a3, 2(a0)
; RV64-NEXT: slli a4, a6, 8
; RV64-NEXT: or a4, a4, a7
; RV64-NEXT: slli a5, a5, 8
; RV64-NEXT: or a3, a5, a3
; RV64-NEXT: slli a3, a3, 16
; RV64-NEXT: lbu a6, 2(a0)
; RV64-NEXT: slli a3, a3, 8
; RV64-NEXT: or a3, a3, a4
; RV64-NEXT: slli a4, a5, 8
; RV64-NEXT: or a4, a4, a6
; RV64-NEXT: slli a4, a4, 16
; RV64-NEXT: or a3, a4, a3
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vmv.v.x v8, a3
; RV64-NEXT: andi a2, a2, 2

18
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
View File

@ -421,18 +421,18 @@ define <33 x double> @vpload_v33f64(<33 x double>* %ptr, <33 x i1> %m, i32 zeroe
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a5, a4
; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: li a6, 16
; CHECK-NEXT: bltu a5, a6, .LBB32_4
; CHECK-NEXT: li a4, 16
; CHECK-NEXT: bltu a5, a4, .LBB32_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: li a5, 16
; CHECK-NEXT: .LBB32_4:
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v0, v8, 4
; CHECK-NEXT: addi a4, a1, 256
; CHECK-NEXT: addi a6, a1, 256
; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v16, (a4), v0.t
; CHECK-NEXT: li a4, 32
; CHECK-NEXT: bltu a2, a4, .LBB32_6
; CHECK-NEXT: vle64.v v16, (a6), v0.t
; CHECK-NEXT: li a5, 32
; CHECK-NEXT: bltu a2, a5, .LBB32_6
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: .LBB32_6:
@ -443,10 +443,10 @@ define <33 x double> @vpload_v33f64(<33 x double>* %ptr, <33 x i1> %m, i32 zeroe
; CHECK-NEXT: .LBB32_8:
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v0, v8, 2
; CHECK-NEXT: addi a4, a1, 128
; CHECK-NEXT: addi a5, a1, 128
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v24, (a4), v0.t
; CHECK-NEXT: bltu a2, a6, .LBB32_10
; CHECK-NEXT: vle64.v v24, (a5), v0.t
; CHECK-NEXT: bltu a2, a4, .LBB32_10
; CHECK-NEXT: # %bb.9:
; CHECK-NEXT: li a2, 16
; CHECK-NEXT: .LBB32_10:

8
llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
View File

@ -27,13 +27,13 @@ define signext i32 @foo(i32 signext %aa) #0 {
; CHECK-NEXT: lw a6, 24(s1)
; CHECK-NEXT: lw a7, 20(s1)
; CHECK-NEXT: lw t1, 16(s1)
; CHECK-NEXT: lw t2, 12(s1)
; CHECK-NEXT: lw a1, 8(s1)
; CHECK-NEXT: lw a1, 12(s1)
; CHECK-NEXT: lw t2, 8(s1)
; CHECK-NEXT: sw a0, 52(s1)
; CHECK-NEXT: sw a0, 48(s1)
; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sd a1, 16(sp)
; CHECK-NEXT: sd t2, 8(sp)
; CHECK-NEXT: sd t2, 16(sp)
; CHECK-NEXT: sd a1, 8(sp)
; CHECK-NEXT: addi a1, s1, 48
; CHECK-NEXT: sd t1, 0(sp)
; CHECK-NEXT: mv a0, t0

692
llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
View File

File diff suppressed because it is too large Load Diff

50
llvm/test/CodeGen/RISCV/rvv/vpload.ll
View File

@ -495,48 +495,48 @@ define <vscale x 16 x double> @vpload_nxv17f64(<vscale x 17 x double>* %ptr, <vs
; CHECK-LABEL: vpload_nxv17f64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a7, a3, 1
; CHECK-NEXT: slli a5, a3, 1
; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: mv t0, a2
; CHECK-NEXT: bltu a2, a7, .LBB38_2
; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: bltu a2, a5, .LBB38_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv t0, a7
; CHECK-NEXT: mv a4, a5
; CHECK-NEXT: .LBB38_2:
; CHECK-NEXT: sub a5, t0, a3
; CHECK-NEXT: sub a7, a4, a3
; CHECK-NEXT: li a6, 0
; CHECK-NEXT: bltu t0, a5, .LBB38_4
; CHECK-NEXT: bltu a4, a7, .LBB38_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a6, a5
; CHECK-NEXT: mv a6, a7
; CHECK-NEXT: .LBB38_4:
; CHECK-NEXT: li a5, 0
; CHECK-NEXT: srli t1, a3, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v0, v8, t1
; CHECK-NEXT: slli a4, a3, 3
; CHECK-NEXT: add a4, a0, a4
; CHECK-NEXT: li a7, 0
; CHECK-NEXT: srli t0, a3, 3
; CHECK-NEXT: vsetvli t1, zero, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v0, v8, t0
; CHECK-NEXT: slli t0, a3, 3
; CHECK-NEXT: add t0, a0, t0
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v16, (a4), v0.t
; CHECK-NEXT: vle64.v v16, (t0), v0.t
; CHECK-NEXT: srli a6, a3, 2
; CHECK-NEXT: sub a4, a2, a7
; CHECK-NEXT: slli a7, a3, 4
; CHECK-NEXT: bltu a2, a4, .LBB38_6
; CHECK-NEXT: sub t0, a2, a5
; CHECK-NEXT: slli a5, a3, 4
; CHECK-NEXT: bltu a2, t0, .LBB38_6
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: mv a5, a4
; CHECK-NEXT: mv a7, t0
; CHECK-NEXT: .LBB38_6:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v0, v8, a6
; CHECK-NEXT: add a2, a0, a7
; CHECK-NEXT: bltu a5, a3, .LBB38_8
; CHECK-NEXT: add a2, a0, a5
; CHECK-NEXT: bltu a7, a3, .LBB38_8
; CHECK-NEXT: # %bb.7:
; CHECK-NEXT: mv a5, a3
; CHECK-NEXT: mv a7, a3
; CHECK-NEXT: .LBB38_8:
; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, mu
; CHECK-NEXT: vsetvli zero, a7, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v24, (a2), v0.t
; CHECK-NEXT: bltu t0, a3, .LBB38_10
; CHECK-NEXT: bltu a4, a3, .LBB38_10
; CHECK-NEXT: # %bb.9:
; CHECK-NEXT: mv t0, a3
; CHECK-NEXT: mv a4, a3
; CHECK-NEXT: .LBB38_10:
; CHECK-NEXT: vsetvli zero, t0, e64, m8, ta, mu
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vle64.v v8, (a0), v0.t
; CHECK-NEXT: vs1r.v v24, (a1)

52
llvm/test/CodeGen/RISCV/rvv/vpstore.ll
View File

@ -408,50 +408,50 @@ define void @vpstore_nxv17f64(<vscale x 17 x double> %val, <vscale x 17 x double
; CHECK-NEXT: slli a3, a3, 3
; CHECK-NEXT: sub sp, sp, a3
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a6, a3, 1
; CHECK-NEXT: slli a4, a3, 1
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: addi a4, sp, 16
; CHECK-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; CHECK-NEXT: addi a5, sp, 16
; CHECK-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; CHECK-NEXT: mv a5, a2
; CHECK-NEXT: bltu a2, a6, .LBB31_2
; CHECK-NEXT: bltu a2, a4, .LBB31_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a5, a6
; CHECK-NEXT: mv a5, a4
; CHECK-NEXT: .LBB31_2:
; CHECK-NEXT: mv a4, a5
; CHECK-NEXT: mv a7, a5
; CHECK-NEXT: bltu a5, a3, .LBB31_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a4, a3
; CHECK-NEXT: mv a7, a3
; CHECK-NEXT: .LBB31_4:
; CHECK-NEXT: li a7, 0
; CHECK-NEXT: li a6, 0
; CHECK-NEXT: vl8re64.v v16, (a0)
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, mu
; CHECK-NEXT: vsetvli zero, a7, e64, m8, ta, mu
; CHECK-NEXT: sub a0, a5, a3
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vse64.v v8, (a1), v0.t
; CHECK-NEXT: bltu a5, a0, .LBB31_6
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: mv a6, a0
; CHECK-NEXT: .LBB31_6:
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: srli a4, a3, 3
; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v0, v24, a4
; CHECK-NEXT: slli a4, a3, 3
; CHECK-NEXT: add a4, a1, a4
; CHECK-NEXT: vsetvli zero, a7, e64, m8, ta, mu
; CHECK-NEXT: addi a5, sp, 16
; CHECK-NEXT: vl8re8.v v8, (a5) # Unknown-size Folded Reload
; CHECK-NEXT: vse64.v v8, (a4), v0.t
; CHECK-NEXT: srli a7, a3, 2
; CHECK-NEXT: sub a4, a2, a6
; CHECK-NEXT: slli a5, a3, 4
; CHECK-NEXT: bltu a2, a4, .LBB31_8
; CHECK-NEXT: srli a5, a3, 3
; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v0, v24, a5
; CHECK-NEXT: slli a5, a3, 3
; CHECK-NEXT: add a5, a1, a5
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, mu
; CHECK-NEXT: addi a6, sp, 16
; CHECK-NEXT: vl8re8.v v8, (a6) # Unknown-size Folded Reload
; CHECK-NEXT: vse64.v v8, (a5), v0.t
; CHECK-NEXT: srli a5, a3, 2
; CHECK-NEXT: sub a6, a2, a4
; CHECK-NEXT: slli a4, a3, 4
; CHECK-NEXT: bltu a2, a6, .LBB31_8
; CHECK-NEXT: # %bb.7:
; CHECK-NEXT: mv a0, a4
; CHECK-NEXT: mv a0, a6
; CHECK-NEXT: .LBB31_8:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v0, v24, a7
; CHECK-NEXT: add a1, a1, a5
; CHECK-NEXT: vslidedown.vx v0, v24, a5
; CHECK-NEXT: add a1, a1, a4
; CHECK-NEXT: bltu a0, a3, .LBB31_10
; CHECK-NEXT: # %bb.9:
; CHECK-NEXT: mv a0, a3

6
llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
View File

@ -1185,7 +1185,7 @@ define signext i32 @vpreduce_umax_nxv32i32(i32 signext %s, <vscale x 32 x i32> %
; RV64-LABEL: vpreduce_umax_nxv32i32:
; RV64: # %bb.0:
; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: srli a6, a3, 2
; RV64-NEXT: srli a2, a3, 2
; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: slli a0, a3, 1
; RV64-NEXT: srli a3, a4, 32
@ -1195,8 +1195,8 @@ define signext i32 @vpreduce_umax_nxv32i32(i32 signext %s, <vscale x 32 x i32> %
; RV64-NEXT: mv a4, a0
; RV64-NEXT: .LBB67_2:
; RV64-NEXT: li a5, 0
; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
; RV64-NEXT: vslidedown.vx v24, v0, a6
; RV64-NEXT: vsetvli a6, zero, e8, mf2, ta, mu
; RV64-NEXT: vslidedown.vx v24, v0, a2
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV64-NEXT: vmv.s.x v25, a3
; RV64-NEXT: vsetvli zero, a4, e32, m8, tu, mu

8
llvm/test/CodeGen/RISCV/sadd_sat.ll
View File

@ -160,12 +160,12 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; RV32IZbbZbt-NEXT: add a0, a4, a0
; RV32IZbbZbt-NEXT: srai a4, a0, 31
; RV32IZbbZbt-NEXT: lui a5, 524288
; RV32IZbbZbt-NEXT: xor a6, a4, a5
; RV32IZbbZbt-NEXT: xor a5, a1, a0
; RV32IZbbZbt-NEXT: xor a5, a4, a5
; RV32IZbbZbt-NEXT: xor a6, a1, a0
; RV32IZbbZbt-NEXT: xor a1, a1, a3
; RV32IZbbZbt-NEXT: andn a1, a5, a1
; RV32IZbbZbt-NEXT: andn a1, a6, a1
; RV32IZbbZbt-NEXT: slti a3, a1, 0
; RV32IZbbZbt-NEXT: cmov a1, a3, a6, a0
; RV32IZbbZbt-NEXT: cmov a1, a3, a5, a0
; RV32IZbbZbt-NEXT: cmov a0, a3, a4, a2
; RV32IZbbZbt-NEXT: ret
;

12
llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
View File

@ -168,13 +168,13 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; RV32IZbbZbt-NEXT: add a0, a2, a0
; RV32IZbbZbt-NEXT: srai a2, a0, 31
; RV32IZbbZbt-NEXT: lui a4, 524288
; RV32IZbbZbt-NEXT: xor a6, a2, a4
; RV32IZbbZbt-NEXT: xor a4, a1, a0
; RV32IZbbZbt-NEXT: xor a4, a2, a4
; RV32IZbbZbt-NEXT: xor a6, a1, a0
; RV32IZbbZbt-NEXT: xor a1, a1, a5
; RV32IZbbZbt-NEXT: andn a1, a4, a1
; RV32IZbbZbt-NEXT: slti a4, a1, 0
; RV32IZbbZbt-NEXT: cmov a1, a4, a6, a0
; RV32IZbbZbt-NEXT: cmov a0, a4, a2, a3
; RV32IZbbZbt-NEXT: andn a1, a6, a1
; RV32IZbbZbt-NEXT: slti a5, a1, 0
; RV32IZbbZbt-NEXT: cmov a1, a5, a4, a0
; RV32IZbbZbt-NEXT: cmov a0, a5, a2, a3
; RV32IZbbZbt-NEXT: ret
;
; RV64IZbbZbt-LABEL: func64:

98
llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
View File

@ -65,20 +65,20 @@ define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind {
; RV32I-NEXT: .LBB1_2: # %entry
; RV32I-NEXT: beqz a1, .LBB1_5
; RV32I-NEXT: # %bb.3: # %entry
; RV32I-NEXT: addi a7, a4, 4
; RV32I-NEXT: addi a5, a4, 4
; RV32I-NEXT: bnez a1, .LBB1_6
; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: addi a5, a3, 8
; RV32I-NEXT: addi a6, a3, 8
; RV32I-NEXT: j .LBB1_7
; RV32I-NEXT: .LBB1_5:
; RV32I-NEXT: addi a7, a3, 4
; RV32I-NEXT: addi a5, a3, 4
; RV32I-NEXT: beqz a1, .LBB1_4
; RV32I-NEXT: .LBB1_6: # %entry
; RV32I-NEXT: addi a5, a4, 8
; RV32I-NEXT: addi a6, a4, 8
; RV32I-NEXT: .LBB1_7: # %entry
; RV32I-NEXT: lw a6, 0(a2)
; RV32I-NEXT: lw a7, 0(a7)
; RV32I-NEXT: lw a2, 0(a5)
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a5, 0(a5)
; RV32I-NEXT: lw a6, 0(a6)
; RV32I-NEXT: beqz a1, .LBB1_9
; RV32I-NEXT: # %bb.8: # %entry
; RV32I-NEXT: addi a1, a4, 12
@ -88,25 +88,25 @@ define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind {
; RV32I-NEXT: .LBB1_10: # %entry
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: sw a2, 8(a0)
; RV32I-NEXT: sw a7, 4(a0)
; RV32I-NEXT: sw a6, 0(a0)
; RV32I-NEXT: sw a6, 8(a0)
; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a2, 0(a0)
; RV32I-NEXT: ret
;
; RV32IBT-LABEL: cmovcc128:
; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: addi a6, a3, 12
; RV32IBT-NEXT: addi a7, a4, 12
; RV32IBT-NEXT: addi t0, a3, 8
; RV32IBT-NEXT: addi t1, a4, 8
; RV32IBT-NEXT: addi t2, a3, 4
; RV32IBT-NEXT: addi a5, a4, 4
; RV32IBT-NEXT: addi a5, a3, 12
; RV32IBT-NEXT: addi a6, a4, 12
; RV32IBT-NEXT: addi a7, a3, 8
; RV32IBT-NEXT: addi t0, a4, 8
; RV32IBT-NEXT: addi t1, a3, 4
; RV32IBT-NEXT: addi t2, a4, 4
; RV32IBT-NEXT: xori a1, a1, 123
; RV32IBT-NEXT: or a1, a1, a2
; RV32IBT-NEXT: cmov a2, a1, a4, a3
; RV32IBT-NEXT: cmov a3, a1, a5, t2
; RV32IBT-NEXT: cmov a4, a1, t1, t0
; RV32IBT-NEXT: cmov a1, a1, a7, a6
; RV32IBT-NEXT: cmov a3, a1, t2, t1
; RV32IBT-NEXT: cmov a4, a1, t0, a7
; RV32IBT-NEXT: cmov a1, a1, a6, a5
; RV32IBT-NEXT: lw a1, 0(a1)
; RV32IBT-NEXT: lw a4, 0(a4)
; RV32IBT-NEXT: lw a3, 0(a3)
@ -192,20 +192,20 @@ define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {
; RV32I-NEXT: .LBB3_2: # %entry
; RV32I-NEXT: bnez a1, .LBB3_5
; RV32I-NEXT: # %bb.3: # %entry
; RV32I-NEXT: addi a7, a3, 4
; RV32I-NEXT: addi a5, a3, 4
; RV32I-NEXT: beqz a1, .LBB3_6
; RV32I-NEXT: .LBB3_4:
; RV32I-NEXT: addi a5, a2, 8
; RV32I-NEXT: addi a6, a2, 8
; RV32I-NEXT: j .LBB3_7
; RV32I-NEXT: .LBB3_5:
; RV32I-NEXT: addi a7, a2, 4
; RV32I-NEXT: addi a5, a2, 4
; RV32I-NEXT: bnez a1, .LBB3_4
; RV32I-NEXT: .LBB3_6: # %entry
; RV32I-NEXT: addi a5, a3, 8
; RV32I-NEXT: addi a6, a3, 8
; RV32I-NEXT: .LBB3_7: # %entry
; RV32I-NEXT: lw a6, 0(a4)
; RV32I-NEXT: lw a7, 0(a7)
; RV32I-NEXT: lw a4, 0(a5)
; RV32I-NEXT: lw a4, 0(a4)
; RV32I-NEXT: lw a5, 0(a5)
; RV32I-NEXT: lw a6, 0(a6)
; RV32I-NEXT: bnez a1, .LBB3_9
; RV32I-NEXT: # %bb.8: # %entry
; RV32I-NEXT: addi a1, a3, 12
@ -215,26 +215,26 @@ define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {
; RV32I-NEXT: .LBB3_10: # %entry
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw a7, 4(a0)
; RV32I-NEXT: sw a6, 0(a0)
; RV32I-NEXT: sw a6, 8(a0)
; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: ret
;
; RV32IBT-LABEL: cmov128:
; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: addi a6, a3, 12
; RV32IBT-NEXT: addi a7, a2, 12
; RV32IBT-NEXT: addi t0, a3, 8
; RV32IBT-NEXT: addi t1, a2, 8
; RV32IBT-NEXT: addi a4, a3, 4
; RV32IBT-NEXT: addi a5, a2, 4
; RV32IBT-NEXT: addi a4, a3, 12
; RV32IBT-NEXT: addi a5, a2, 12
; RV32IBT-NEXT: addi a6, a3, 8
; RV32IBT-NEXT: addi a7, a2, 8
; RV32IBT-NEXT: addi t0, a3, 4
; RV32IBT-NEXT: addi t1, a2, 4
; RV32IBT-NEXT: andi a1, a1, 1
; RV32IBT-NEXT: cmov a2, a1, a2, a3
; RV32IBT-NEXT: cmov a3, a1, a5, a4
; RV32IBT-NEXT: cmov a4, a1, t1, t0
; RV32IBT-NEXT: cmov a1, a1, a7, a6
; RV32IBT-NEXT: cmov a3, a1, t1, t0
; RV32IBT-NEXT: cmov a6, a1, a7, a6
; RV32IBT-NEXT: cmov a1, a1, a5, a4
; RV32IBT-NEXT: lw a1, 0(a1)
; RV32IBT-NEXT: lw a4, 0(a4)
; RV32IBT-NEXT: lw a4, 0(a6)
; RV32IBT-NEXT: lw a3, 0(a3)
; RV32IBT-NEXT: lw a2, 0(a2)
; RV32IBT-NEXT: sw a1, 12(a0)
@ -476,17 +476,17 @@ entry:
define i32 @cmovdiffcc(i1 %a, i1 %b, i32 %c, i32 %d, i32 %e, i32 %f) nounwind {
; RV32I-LABEL: cmovdiffcc:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: andi a1, a1, 1
; RV32I-NEXT: beqz a0, .LBB7_3
; RV32I-NEXT: andi a6, a0, 1
; RV32I-NEXT: andi a0, a1, 1
; RV32I-NEXT: beqz a6, .LBB7_3
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: beqz a1, .LBB7_4
; RV32I-NEXT: beqz a0, .LBB7_4
; RV32I-NEXT: .LBB7_2: # %entry
; RV32I-NEXT: add a0, a2, a4
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB7_3: # %entry
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bnez a1, .LBB7_2
; RV32I-NEXT: bnez a0, .LBB7_2
; RV32I-NEXT: .LBB7_4: # %entry
; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: add a0, a2, a4
@ -503,17 +503,17 @@ define i32 @cmovdiffcc(i1 %a, i1 %b, i32 %c, i32 %d, i32 %e, i32 %f) nounwind {
;
; RV64I-LABEL: cmovdiffcc:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: andi a1, a1, 1
; RV64I-NEXT: beqz a0, .LBB7_3
; RV64I-NEXT: andi a6, a0, 1
; RV64I-NEXT: andi a0, a1, 1
; RV64I-NEXT: beqz a6, .LBB7_3
; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: beqz a1, .LBB7_4
; RV64I-NEXT: beqz a0, .LBB7_4
; RV64I-NEXT: .LBB7_2: # %entry
; RV64I-NEXT: addw a0, a2, a4
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB7_3: # %entry
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bnez a1, .LBB7_2
; RV64I-NEXT: bnez a0, .LBB7_2
; RV64I-NEXT: .LBB7_4: # %entry
; RV64I-NEXT: mv a4, a5
; RV64I-NEXT: addw a0, a2, a4

12
llvm/test/CodeGen/RISCV/sextw-removal.ll
View File

@ -179,19 +179,19 @@ define void @test5(i32 signext %arg, i32 signext %arg1) nounwind {
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: lui a1, 349525
; RV64I-NEXT: addiw s2, a1, 1365
; RV64I-NEXT: addiw s0, a1, 1365
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw s1, a1, 819
; RV64I-NEXT: lui a1, 61681
; RV64I-NEXT: addiw s3, a1, -241
; RV64I-NEXT: addiw s2, a1, -241
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw s0, a1, 257
; RV64I-NEXT: addiw s3, a1, 257
; RV64I-NEXT: .LBB4_1: # %bb2
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: call bar@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: and a0, a0, s0
; RV64I-NEXT: subw a0, a1, a0
; RV64I-NEXT: and a2, a0, s1
; RV64I-NEXT: srli a0, a0, 2
@ -199,8 +199,8 @@ define void @test5(i32 signext %arg, i32 signext %arg1) nounwind {
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: mulw a0, a0, s0
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: mulw a0, a0, s3
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: bnez a1, .LBB4_1
; RV64I-NEXT: # %bb.2: # %bb7

16
llvm/test/CodeGen/RISCV/shadowcallstack.ll
View File

@ -82,14 +82,14 @@ define i32 @f4() shadowcallstack {
; RV32-NEXT: .cfi_offset s1, -12
; RV32-NEXT: .cfi_offset s3, -16
; RV32-NEXT: call bar@plt
; RV32-NEXT: mv s3, a0
; RV32-NEXT: mv s0, a0
; RV32-NEXT: call bar@plt
; RV32-NEXT: mv s1, a0
; RV32-NEXT: call bar@plt
; RV32-NEXT: mv s0, a0
; RV32-NEXT: mv s3, a0
; RV32-NEXT: call bar@plt
; RV32-NEXT: add a1, s3, s1
; RV32-NEXT: add a0, s0, a0
; RV32-NEXT: add a1, s0, s1
; RV32-NEXT: add a0, s3, a0
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@ -115,14 +115,14 @@ define i32 @f4() shadowcallstack {
; RV64-NEXT: .cfi_offset s1, -24
; RV64-NEXT: .cfi_offset s3, -32
; RV64-NEXT: call bar@plt
; RV64-NEXT: mv s3, a0
; RV64-NEXT: mv s0, a0
; RV64-NEXT: call bar@plt
; RV64-NEXT: mv s1, a0
; RV64-NEXT: call bar@plt
; RV64-NEXT: mv s0, a0
; RV64-NEXT: mv s3, a0
; RV64-NEXT: call bar@plt
; RV64-NEXT: addw a1, s3, s1
; RV64-NEXT: addw a0, s0, a0
; RV64-NEXT: addw a1, s0, s1
; RV64-NEXT: addw a0, s3, a0
; RV64-NEXT: addw a0, a1, a0
; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload

484
llvm/test/CodeGen/RISCV/shifts.ll
View File

@ -148,120 +148,116 @@ define i64 @shl64_minsize(i64 %a, i64 %b) minsize nounwind {
define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: lshr128:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw t0, 8(a1)
; RV32I-NEXT: lw t4, 12(a1)
; RV32I-NEXT: li a6, 64
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: li a3, 64
; RV32I-NEXT: sub t0, a3, a2
; RV32I-NEXT: li a6, 32
; RV32I-NEXT: sub t1, a6, a2
; RV32I-NEXT: li a3, 32
; RV32I-NEXT: sub t5, a3, a2
; RV32I-NEXT: li t2, 31
; RV32I-NEXT: bltz t5, .LBB6_2
; RV32I-NEXT: bltz t1, .LBB6_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sll a3, t0, t5
; RV32I-NEXT: sll t6, a5, t1
; RV32I-NEXT: j .LBB6_3
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: sll a3, t4, t1
; RV32I-NEXT: sub a4, t2, t1
; RV32I-NEXT: srli a5, t0, 1
; RV32I-NEXT: srl a4, a5, a4
; RV32I-NEXT: or a3, a3, a4
; RV32I-NEXT: sll a6, a4, t0
; RV32I-NEXT: sub a7, t2, t0
; RV32I-NEXT: srli t3, a5, 1
; RV32I-NEXT: srl a7, t3, a7
; RV32I-NEXT: or t6, a6, a7
; RV32I-NEXT: .LBB6_3:
; RV32I-NEXT: lw a5, 4(a1)
; RV32I-NEXT: addi t6, a2, -32
; RV32I-NEXT: bgez t6, .LBB6_5
; RV32I-NEXT: lw t5, 4(a1)
; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: bgez a6, .LBB6_5
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: srl a4, a5, a2
; RV32I-NEXT: or a3, a3, a4
; RV32I-NEXT: srl a7, t5, a2
; RV32I-NEXT: or t6, t6, a7
; RV32I-NEXT: .LBB6_5:
; RV32I-NEXT: addi a4, a2, -96
; RV32I-NEXT: addi t4, a2, -96
; RV32I-NEXT: addi t3, a2, -64
; RV32I-NEXT: bltz a4, .LBB6_7
; RV32I-NEXT: bltz t4, .LBB6_7
; RV32I-NEXT: # %bb.6:
; RV32I-NEXT: li a7, 0
; RV32I-NEXT: bgeu a2, a6, .LBB6_8
; RV32I-NEXT: bgeu a2, a3, .LBB6_8
; RV32I-NEXT: j .LBB6_9
; RV32I-NEXT: .LBB6_7:
; RV32I-NEXT: srl a7, t4, t3
; RV32I-NEXT: bltu a2, a6, .LBB6_9
; RV32I-NEXT: srl a7, a4, t3
; RV32I-NEXT: bltu a2, a3, .LBB6_9
; RV32I-NEXT: .LBB6_8:
; RV32I-NEXT: mv a3, a7
; RV32I-NEXT: mv t6, a7
; RV32I-NEXT: .LBB6_9:
; RV32I-NEXT: mv a7, a5
; RV32I-NEXT: mv a7, t5
; RV32I-NEXT: beqz a2, .LBB6_11
; RV32I-NEXT: # %bb.10:
; RV32I-NEXT: mv a7, a3
; RV32I-NEXT: mv a7, t6
; RV32I-NEXT: .LBB6_11:
; RV32I-NEXT: lw s0, 0(a1)
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sub t2, t2, a2
; RV32I-NEXT: bltz t6, .LBB6_13
; RV32I-NEXT: bltz a6, .LBB6_13
; RV32I-NEXT: # %bb.12:
; RV32I-NEXT: srl a5, a5, t6
; RV32I-NEXT: bltz t5, .LBB6_14
; RV32I-NEXT: srl t5, t5, a6
; RV32I-NEXT: bltz t1, .LBB6_14
; RV32I-NEXT: j .LBB6_15
; RV32I-NEXT: .LBB6_13:
; RV32I-NEXT: srl a3, s0, a2
; RV32I-NEXT: slli a5, a5, 1
; RV32I-NEXT: sll a5, a5, t2
; RV32I-NEXT: or a5, a3, a5
; RV32I-NEXT: bgez t5, .LBB6_15
; RV32I-NEXT: srl t6, a1, a2
; RV32I-NEXT: slli t5, t5, 1
; RV32I-NEXT: sll t5, t5, t2
; RV32I-NEXT: or t5, t6, t5
; RV32I-NEXT: bgez t1, .LBB6_15
; RV32I-NEXT: .LBB6_14:
; RV32I-NEXT: sll a3, t0, t1
; RV32I-NEXT: or a5, a5, a3
; RV32I-NEXT: sll t0, a5, t0
; RV32I-NEXT: or t5, t5, t0
; RV32I-NEXT: .LBB6_15:
; RV32I-NEXT: slli a3, t4, 1
; RV32I-NEXT: bltz a4, .LBB6_17
; RV32I-NEXT: slli t0, a4, 1
; RV32I-NEXT: bltz t4, .LBB6_17
; RV32I-NEXT: # %bb.16:
; RV32I-NEXT: srl a4, t4, a4
; RV32I-NEXT: bgeu a2, a6, .LBB6_18
; RV32I-NEXT: srl t1, a4, t4
; RV32I-NEXT: bgeu a2, a3, .LBB6_18
; RV32I-NEXT: j .LBB6_19
; RV32I-NEXT: .LBB6_17:
; RV32I-NEXT: li a4, 95
; RV32I-NEXT: sub a4, a4, a2
; RV32I-NEXT: sll a4, a3, a4
; RV32I-NEXT: srl a1, t0, t3
; RV32I-NEXT: or a4, a1, a4
; RV32I-NEXT: bltu a2, a6, .LBB6_19
; RV32I-NEXT: li t1, 95
; RV32I-NEXT: sub t1, t1, a2
; RV32I-NEXT: sll t1, t0, t1
; RV32I-NEXT: srl t3, a5, t3
; RV32I-NEXT: or t1, t3, t1
; RV32I-NEXT: bltu a2, a3, .LBB6_19
; RV32I-NEXT: .LBB6_18:
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: .LBB6_19:
; RV32I-NEXT: bnez a2, .LBB6_22
; RV32I-NEXT: # %bb.20:
; RV32I-NEXT: bltz t6, .LBB6_23
; RV32I-NEXT: bltz a6, .LBB6_23
; RV32I-NEXT: .LBB6_21:
; RV32I-NEXT: srl a3, t4, t6
; RV32I-NEXT: bgeu a2, a6, .LBB6_24
; RV32I-NEXT: srl a5, a4, a6
; RV32I-NEXT: bgeu a2, a3, .LBB6_24
; RV32I-NEXT: j .LBB6_25
; RV32I-NEXT: .LBB6_22:
; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: bgez t6, .LBB6_21
; RV32I-NEXT: mv a1, t5
; RV32I-NEXT: bgez a6, .LBB6_21
; RV32I-NEXT: .LBB6_23:
; RV32I-NEXT: srl a1, t0, a2
; RV32I-NEXT: sll a3, a3, t2
; RV32I-NEXT: or a3, a1, a3
; RV32I-NEXT: bltu a2, a6, .LBB6_25
; RV32I-NEXT: srl a5, a5, a2
; RV32I-NEXT: sll t0, t0, t2
; RV32I-NEXT: or a5, a5, t0
; RV32I-NEXT: bltu a2, a3, .LBB6_25
; RV32I-NEXT: .LBB6_24:
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a5, 0
; RV32I-NEXT: .LBB6_25:
; RV32I-NEXT: bltz t6, .LBB6_27
; RV32I-NEXT: bltz a6, .LBB6_27
; RV32I-NEXT: # %bb.26:
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: bgeu a2, a6, .LBB6_28
; RV32I-NEXT: bgeu a2, a3, .LBB6_28
; RV32I-NEXT: j .LBB6_29
; RV32I-NEXT: .LBB6_27:
; RV32I-NEXT: srl a4, t4, a2
; RV32I-NEXT: bltu a2, a6, .LBB6_29
; RV32I-NEXT: srl a4, a4, a2
; RV32I-NEXT: bltu a2, a3, .LBB6_29
; RV32I-NEXT: .LBB6_28:
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: .LBB6_29:
; RV32I-NEXT: sw a4, 12(a0)
; RV32I-NEXT: sw a3, 8(a0)
; RV32I-NEXT: sw s0, 0(a0)
; RV32I-NEXT: sw a5, 8(a0)
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a7, 4(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: lshr128:
@ -290,120 +286,118 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw t2, 8(a1)
; RV32I-NEXT: lw t5, 12(a1)
; RV32I-NEXT: li a6, 64
; RV32I-NEXT: sub t1, a6, a2
; RV32I-NEXT: li a3, 32
; RV32I-NEXT: sub t6, a3, a2
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: li a3, 64
; RV32I-NEXT: sub t1, a3, a2
; RV32I-NEXT: li a6, 32
; RV32I-NEXT: sub t2, a6, a2
; RV32I-NEXT: li t4, 31
; RV32I-NEXT: bltz t6, .LBB7_2
; RV32I-NEXT: bltz t2, .LBB7_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sll s0, t2, t6
; RV32I-NEXT: sll s0, a5, t2
; RV32I-NEXT: j .LBB7_3
; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: sll a3, t5, t1
; RV32I-NEXT: sub a4, t4, t1
; RV32I-NEXT: srli a5, t2, 1
; RV32I-NEXT: srl a4, a5, a4
; RV32I-NEXT: or s0, a3, a4
; RV32I-NEXT: sll a6, a4, t1
; RV32I-NEXT: sub a7, t4, t1
; RV32I-NEXT: srli t0, a5, 1
; RV32I-NEXT: srl a7, t0, a7
; RV32I-NEXT: or s0, a6, a7
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: lw a5, 4(a1)
; RV32I-NEXT: addi a3, a2, -32
; RV32I-NEXT: bgez a3, .LBB7_5
; RV32I-NEXT: lw t6, 4(a1)
; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: bgez a6, .LBB7_5
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: srl a4, a5, a2
; RV32I-NEXT: or s0, s0, a4
; RV32I-NEXT: srl a7, t6, a2
; RV32I-NEXT: or s0, s0, a7
; RV32I-NEXT: .LBB7_5:
; RV32I-NEXT: addi t3, a2, -64
; RV32I-NEXT: addi a4, a2, -96
; RV32I-NEXT: srai a7, t5, 31
; RV32I-NEXT: bltz a4, .LBB7_7
; RV32I-NEXT: addi t5, a2, -96
; RV32I-NEXT: srai a7, a4, 31
; RV32I-NEXT: bltz t5, .LBB7_7
; RV32I-NEXT: # %bb.6:
; RV32I-NEXT: mv t0, a7
; RV32I-NEXT: bgeu a2, a6, .LBB7_8
; RV32I-NEXT: bgeu a2, a3, .LBB7_8
; RV32I-NEXT: j .LBB7_9
; RV32I-NEXT: .LBB7_7:
; RV32I-NEXT: sra t0, t5, t3
; RV32I-NEXT: bltu a2, a6, .LBB7_9
; RV32I-NEXT: sra t0, a4, t3
; RV32I-NEXT: bltu a2, a3, .LBB7_9
; RV32I-NEXT: .LBB7_8:
; RV32I-NEXT: mv s0, t0
; RV32I-NEXT: .LBB7_9:
; RV32I-NEXT: mv t0, a5
; RV32I-NEXT: mv t0, t6
; RV32I-NEXT: beqz a2, .LBB7_11
; RV32I-NEXT: # %bb.10:
; RV32I-NEXT: mv t0, s0
; RV32I-NEXT: .LBB7_11:
; RV32I-NEXT: lw s1, 0(a1)
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sub t4, t4, a2
; RV32I-NEXT: bltz a3, .LBB7_13
; RV32I-NEXT: bltz a6, .LBB7_13
; RV32I-NEXT: # %bb.12:
; RV32I-NEXT: srl a5, a5, a3
; RV32I-NEXT: bltz t6, .LBB7_14
; RV32I-NEXT: srl t6, t6, a6
; RV32I-NEXT: bltz t2, .LBB7_14
; RV32I-NEXT: j .LBB7_15
; RV32I-NEXT: .LBB7_13:
; RV32I-NEXT: srl s0, s1, a2
; RV32I-NEXT: slli a5, a5, 1
; RV32I-NEXT: sll a5, a5, t4
; RV32I-NEXT: or a5, s0, a5
; RV32I-NEXT: bgez t6, .LBB7_15
; RV32I-NEXT: srl s0, a1, a2
; RV32I-NEXT: slli t6, t6, 1
; RV32I-NEXT: sll t6, t6, t4
; RV32I-NEXT: or t6, s0, t6
; RV32I-NEXT: bgez t2, .LBB7_15
; RV32I-NEXT: .LBB7_14:
; RV32I-NEXT: sll s0, t2, t1
; RV32I-NEXT: or a5, a5, s0
; RV32I-NEXT: sll t1, a5, t1
; RV32I-NEXT: or t6, t6, t1
; RV32I-NEXT: .LBB7_15:
; RV32I-NEXT: slli s0, t5, 1
; RV32I-NEXT: bltz a4, .LBB7_17
; RV32I-NEXT: slli t1, a4, 1
; RV32I-NEXT: bltz t5, .LBB7_17
; RV32I-NEXT: # %bb.16:
; RV32I-NEXT: sra a4, t5, a4
; RV32I-NEXT: bgeu a2, a6, .LBB7_18
; RV32I-NEXT: sra t2, a4, t5
; RV32I-NEXT: bgeu a2, a3, .LBB7_18
; RV32I-NEXT: j .LBB7_19
; RV32I-NEXT: .LBB7_17:
; RV32I-NEXT: li a4, 95
; RV32I-NEXT: sub a4, a4, a2
; RV32I-NEXT: sll a4, s0, a4
; RV32I-NEXT: srl a1, t2, t3
; RV32I-NEXT: or a4, a1, a4
; RV32I-NEXT: bltu a2, a6, .LBB7_19
; RV32I-NEXT: li t2, 95
; RV32I-NEXT: sub t2, t2, a2
; RV32I-NEXT: sll t2, t1, t2
; RV32I-NEXT: srl t3, a5, t3
; RV32I-NEXT: or t2, t3, t2
; RV32I-NEXT: bltu a2, a3, .LBB7_19
; RV32I-NEXT: .LBB7_18:
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: mv t6, t2
; RV32I-NEXT: .LBB7_19:
; RV32I-NEXT: bnez a2, .LBB7_22
; RV32I-NEXT: # %bb.20:
; RV32I-NEXT: bltz a3, .LBB7_23
; RV32I-NEXT: bltz a6, .LBB7_23
; RV32I-NEXT: .LBB7_21:
; RV32I-NEXT: sra a4, t5, a3
; RV32I-NEXT: bgeu a2, a6, .LBB7_24
; RV32I-NEXT: sra a5, a4, a6
; RV32I-NEXT: bgeu a2, a3, .LBB7_24
; RV32I-NEXT: j .LBB7_25
; RV32I-NEXT: .LBB7_22:
; RV32I-NEXT: mv s1, a5
; RV32I-NEXT: bgez a3, .LBB7_21
; RV32I-NEXT: mv a1, t6
; RV32I-NEXT: bgez a6, .LBB7_21
; RV32I-NEXT: .LBB7_23:
; RV32I-NEXT: srl a1, t2, a2
; RV32I-NEXT: sll a4, s0, t4
; RV32I-NEXT: or a4, a1, a4
; RV32I-NEXT: bltu a2, a6, .LBB7_25
; RV32I-NEXT: srl a5, a5, a2
; RV32I-NEXT: sll t1, t1, t4
; RV32I-NEXT: or a5, a5, t1
; RV32I-NEXT: bltu a2, a3, .LBB7_25
; RV32I-NEXT: .LBB7_24:
; RV32I-NEXT: mv a4, a7
; RV32I-NEXT: mv a5, a7
; RV32I-NEXT: .LBB7_25:
; RV32I-NEXT: bltz a3, .LBB7_27
; RV32I-NEXT: bltz a6, .LBB7_27
; RV32I-NEXT: # %bb.26:
; RV32I-NEXT: mv a3, a7
; RV32I-NEXT: bgeu a2, a6, .LBB7_28
; RV32I-NEXT: mv a4, a7
; RV32I-NEXT: bgeu a2, a3, .LBB7_28
; RV32I-NEXT: j .LBB7_29
; RV32I-NEXT: .LBB7_27:
; RV32I-NEXT: sra a3, t5, a2
; RV32I-NEXT: bltu a2, a6, .LBB7_29
; RV32I-NEXT: sra a4, a4, a2
; RV32I-NEXT: bltu a2, a3, .LBB7_29
; RV32I-NEXT: .LBB7_28:
; RV32I-NEXT: mv a3, a7
; RV32I-NEXT: mv a4, a7
; RV32I-NEXT: .LBB7_29:
; RV32I-NEXT: sw a3, 12(a0)
; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw s1, 0(a0)
; RV32I-NEXT: sw a4, 12(a0)
; RV32I-NEXT: sw a5, 8(a0)
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw t0, 4(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
@ -431,120 +425,116 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: shl128:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw t0, 4(a1)
; RV32I-NEXT: lw t4, 0(a1)
; RV32I-NEXT: li a6, 64
; RV32I-NEXT: lw a5, 4(a1)
; RV32I-NEXT: lw a4, 0(a1)
; RV32I-NEXT: li a3, 64
; RV32I-NEXT: sub t0, a3, a2
; RV32I-NEXT: li a6, 32
; RV32I-NEXT: sub t1, a6, a2
; RV32I-NEXT: li a3, 32
; RV32I-NEXT: sub t5, a3, a2
; RV32I-NEXT: li t2, 31
; RV32I-NEXT: bltz t5, .LBB8_2
; RV32I-NEXT: bltz t1, .LBB8_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srl a3, t0, t5
; RV32I-NEXT: srl t6, a5, t1
; RV32I-NEXT: j .LBB8_3
; RV32I-NEXT: .LBB8_2:
; RV32I-NEXT: srl a3, t4, t1
; RV32I-NEXT: sub a4, t2, t1
; RV32I-NEXT: slli a5, t0, 1
; RV32I-NEXT: sll a4, a5, a4
; RV32I-NEXT: or a3, a3, a4
; RV32I-NEXT: srl a6, a4, t0
; RV32I-NEXT: sub a7, t2, t0
; RV32I-NEXT: slli t3, a5, 1
; RV32I-NEXT: sll a7, t3, a7
; RV32I-NEXT: or t6, a6, a7
; RV32I-NEXT: .LBB8_3:
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: addi t6, a2, -32
; RV32I-NEXT: bgez t6, .LBB8_5
; RV32I-NEXT: lw t5, 8(a1)
; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: bgez a6, .LBB8_5
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: sll a4, a5, a2
; RV32I-NEXT: or a3, a3, a4
; RV32I-NEXT: sll a7, t5, a2
; RV32I-NEXT: or t6, t6, a7
; RV32I-NEXT: .LBB8_5:
; RV32I-NEXT: addi a4, a2, -96
; RV32I-NEXT: addi t4, a2, -96
; RV32I-NEXT: addi t3, a2, -64
; RV32I-NEXT: bltz a4, .LBB8_7
; RV32I-NEXT: bltz t4, .LBB8_7
; RV32I-NEXT: # %bb.6:
; RV32I-NEXT: li a7, 0
; RV32I-NEXT: bgeu a2, a6, .LBB8_8
; RV32I-NEXT: bgeu a2, a3, .LBB8_8
; RV32I-NEXT: j .LBB8_9
; RV32I-NEXT: .LBB8_7:
; RV32I-NEXT: sll a7, t4, t3
; RV32I-NEXT: bltu a2, a6, .LBB8_9
; RV32I-NEXT: sll a7, a4, t3
; RV32I-NEXT: bltu a2, a3, .LBB8_9
; RV32I-NEXT: .LBB8_8:
; RV32I-NEXT: mv a3, a7
; RV32I-NEXT: mv t6, a7
; RV32I-NEXT: .LBB8_9:
; RV32I-NEXT: mv a7, a5
; RV32I-NEXT: mv a7, t5
; RV32I-NEXT: beqz a2, .LBB8_11
; RV32I-NEXT: # %bb.10:
; RV32I-NEXT: mv a7, a3
; RV32I-NEXT: mv a7, t6
; RV32I-NEXT: .LBB8_11:
; RV32I-NEXT: lw s0, 12(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: sub t2, t2, a2
; RV32I-NEXT: bltz t6, .LBB8_13
; RV32I-NEXT: bltz a6, .LBB8_13
; RV32I-NEXT: # %bb.12:
; RV32I-NEXT: sll a5, a5, t6
; RV32I-NEXT: bltz t5, .LBB8_14
; RV32I-NEXT: sll t5, t5, a6
; RV32I-NEXT: bltz t1, .LBB8_14
; RV32I-NEXT: j .LBB8_15
; RV32I-NEXT: .LBB8_13:
; RV32I-NEXT: sll a3, s0, a2
; RV32I-NEXT: srli a5, a5, 1
; RV32I-NEXT: srl a5, a5, t2
; RV32I-NEXT: or a5, a3, a5
; RV32I-NEXT: bgez t5, .LBB8_15
; RV32I-NEXT: sll t6, a1, a2
; RV32I-NEXT: srli t5, t5, 1
; RV32I-NEXT: srl t5, t5, t2
; RV32I-NEXT: or t5, t6, t5
; RV32I-NEXT: bgez t1, .LBB8_15
; RV32I-NEXT: .LBB8_14:
; RV32I-NEXT: srl a3, t0, t1
; RV32I-NEXT: or a5, a5, a3
; RV32I-NEXT: srl t0, a5, t0
; RV32I-NEXT: or t5, t5, t0
; RV32I-NEXT: .LBB8_15:
; RV32I-NEXT: srli a3, t4, 1
; RV32I-NEXT: bltz a4, .LBB8_17
; RV32I-NEXT: srli t0, a4, 1
; RV32I-NEXT: bltz t4, .LBB8_17
; RV32I-NEXT: # %bb.16:
; RV32I-NEXT: sll a4, t4, a4
; RV32I-NEXT: bgeu a2, a6, .LBB8_18
; RV32I-NEXT: sll t1, a4, t4
; RV32I-NEXT: bgeu a2, a3, .LBB8_18
; RV32I-NEXT: j .LBB8_19
; RV32I-NEXT: .LBB8_17:
; RV32I-NEXT: li a4, 95
; RV32I-NEXT: sub a4, a4, a2
; RV32I-NEXT: srl a4, a3, a4
; RV32I-NEXT: sll a1, t0, t3
; RV32I-NEXT: or a4, a1, a4
; RV32I-NEXT: bltu a2, a6, .LBB8_19
; RV32I-NEXT: li t1, 95
; RV32I-NEXT: sub t1, t1, a2
; RV32I-NEXT: srl t1, t0, t1
; RV32I-NEXT: sll t3, a5, t3
; RV32I-NEXT: or t1, t3, t1
; RV32I-NEXT: bltu a2, a3, .LBB8_19
; RV32I-NEXT: .LBB8_18:
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: .LBB8_19:
; RV32I-NEXT: bnez a2, .LBB8_22
; RV32I-NEXT: # %bb.20:
; RV32I-NEXT: bltz t6, .LBB8_23
; RV32I-NEXT: bltz a6, .LBB8_23
; RV32I-NEXT: .LBB8_21:
; RV32I-NEXT: sll a3, t4, t6
; RV32I-NEXT: bgeu a2, a6, .LBB8_24
; RV32I-NEXT: sll a5, a4, a6
; RV32I-NEXT: bgeu a2, a3, .LBB8_24
; RV32I-NEXT: j .LBB8_25
; RV32I-NEXT: .LBB8_22:
; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: bgez t6, .LBB8_21
; RV32I-NEXT: mv a1, t5
; RV32I-NEXT: bgez a6, .LBB8_21
; RV32I-NEXT: .LBB8_23:
; RV32I-NEXT: sll a1, t0, a2
; RV32I-NEXT: srl a3, a3, t2
; RV32I-NEXT: or a3, a1, a3
; RV32I-NEXT: bltu a2, a6, .LBB8_25
; RV32I-NEXT: sll a5, a5, a2
; RV32I-NEXT: srl t0, t0, t2
; RV32I-NEXT: or a5, a5, t0
; RV32I-NEXT: bltu a2, a3, .LBB8_25
; RV32I-NEXT: .LBB8_24:
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a5, 0
; RV32I-NEXT: .LBB8_25:
; RV32I-NEXT: bltz t6, .LBB8_27
; RV32I-NEXT: bltz a6, .LBB8_27
; RV32I-NEXT: # %bb.26:
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: bgeu a2, a6, .LBB8_28
; RV32I-NEXT: bgeu a2, a3, .LBB8_28
; RV32I-NEXT: j .LBB8_29
; RV32I-NEXT: .LBB8_27:
; RV32I-NEXT: sll a4, t4, a2
; RV32I-NEXT: bltu a2, a6, .LBB8_29
; RV32I-NEXT: sll a4, a4, a2
; RV32I-NEXT: bltu a2, a3, .LBB8_29
; RV32I-NEXT: .LBB8_28:
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: .LBB8_29:
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: sw s0, 12(a0)
; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: sw a7, 8(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: shl128:
@ -606,69 +596,69 @@ define i64 @fshr64_minsize(i64 %a, i64 %b) minsize nounwind {
define i128 @fshr128_minsize(i128 %a, i128 %b) minsize nounwind {
; RV32I-LABEL: fshr128_minsize:
; RV32I: # %bb.0:
; RV32I-NEXT: lw t2, 8(a1)
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw t2, 0(a1)
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a7, 4(a1)
; RV32I-NEXT: lw t1, 12(a1)
; RV32I-NEXT: andi a1, a2, 64
; RV32I-NEXT: mv a5, a7
; RV32I-NEXT: mv a6, a3
; RV32I-NEXT: beqz a1, .LBB10_2
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: andi t1, a2, 64
; RV32I-NEXT: mv t0, a7
; RV32I-NEXT: mv a4, t2
; RV32I-NEXT: beqz t1, .LBB10_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a5, t1
; RV32I-NEXT: mv a6, t2
; RV32I-NEXT: mv t0, a1
; RV32I-NEXT: mv a4, a3
; RV32I-NEXT: .LBB10_2:
; RV32I-NEXT: andi a4, a2, 32
; RV32I-NEXT: mv t0, a6
; RV32I-NEXT: bnez a4, .LBB10_13
; RV32I-NEXT: andi a6, a2, 32
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: bnez a6, .LBB10_13
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: bnez a1, .LBB10_14
; RV32I-NEXT: bnez t1, .LBB10_14
; RV32I-NEXT: .LBB10_4:
; RV32I-NEXT: beqz a4, .LBB10_6
; RV32I-NEXT: beqz a6, .LBB10_6
; RV32I-NEXT: .LBB10_5:
; RV32I-NEXT: mv a5, t2
; RV32I-NEXT: mv t0, a3
; RV32I-NEXT: .LBB10_6:
; RV32I-NEXT: slli t3, a5, 1
; RV32I-NEXT: not a3, a2
; RV32I-NEXT: beqz a1, .LBB10_8
; RV32I-NEXT: slli t3, t0, 1
; RV32I-NEXT: not t2, a2
; RV32I-NEXT: beqz t1, .LBB10_8
; RV32I-NEXT: # %bb.7:
; RV32I-NEXT: mv t1, a7
; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB10_8:
; RV32I-NEXT: srl a7, t0, a2
; RV32I-NEXT: sll a1, t3, a3
; RV32I-NEXT: srl a5, a5, a2
; RV32I-NEXT: beqz a4, .LBB10_10
; RV32I-NEXT: srl a7, a5, a2
; RV32I-NEXT: sll t1, t3, t2
; RV32I-NEXT: srl t0, t0, a2
; RV32I-NEXT: beqz a6, .LBB10_10
; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: mv t2, t1
; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: .LBB10_10:
; RV32I-NEXT: or a7, a1, a7
; RV32I-NEXT: slli a1, t2, 1
; RV32I-NEXT: sll a1, a1, a3
; RV32I-NEXT: or a5, a1, a5
; RV32I-NEXT: srl a1, t2, a2
; RV32I-NEXT: beqz a4, .LBB10_12
; RV32I-NEXT: or a7, t1, a7
; RV32I-NEXT: slli t1, a3, 1
; RV32I-NEXT: sll t1, t1, t2
; RV32I-NEXT: or t0, t1, t0
; RV32I-NEXT: srl a3, a3, a2
; RV32I-NEXT: beqz a6, .LBB10_12
; RV32I-NEXT: # %bb.11:
; RV32I-NEXT: mv t1, a6
; RV32I-NEXT: mv a1, a4
; RV32I-NEXT: .LBB10_12:
; RV32I-NEXT: slli a4, t1, 1
; RV32I-NEXT: sll a4, a4, a3
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srl a2, t1, a2
; RV32I-NEXT: slli a4, t0, 1
; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: or a2, a3, a2
; RV32I-NEXT: sw a2, 12(a0)
; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a4, a4, t2
; RV32I-NEXT: or a3, a4, a3
; RV32I-NEXT: srl a1, a1, a2
; RV32I-NEXT: slli a2, a5, 1
; RV32I-NEXT: sll a2, a2, t2
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: sw a3, 8(a0)
; RV32I-NEXT: sw t0, 4(a0)
; RV32I-NEXT: sw a7, 0(a0)
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB10_13:
; RV32I-NEXT: mv t0, a5
; RV32I-NEXT: beqz a1, .LBB10_4
; RV32I-NEXT: mv a5, t0
; RV32I-NEXT: beqz t1, .LBB10_4
; RV32I-NEXT: .LBB10_14:
; RV32I-NEXT: mv t2, a3
; RV32I-NEXT: bnez a4, .LBB10_5
; RV32I-NEXT: mv a3, t2
; RV32I-NEXT: bnez a6, .LBB10_5
; RV32I-NEXT: j .LBB10_6
;
; RV64I-LABEL: fshr128_minsize:

32
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
View File

@ -306,13 +306,13 @@ define void @test_srem_vec(<3 x i33>* %X) nounwind {
; RV32-NEXT: lbu a1, 12(s0)
; RV32-NEXT: lw a2, 8(s0)
; RV32-NEXT: andi a3, a0, 1
; RV32-NEXT: neg s2, a3
; RV32-NEXT: neg s1, a3
; RV32-NEXT: slli a3, a1, 30
; RV32-NEXT: srli a4, a2, 2
; RV32-NEXT: or s3, a4, a3
; RV32-NEXT: or s2, a4, a3
; RV32-NEXT: srli a1, a1, 2
; RV32-NEXT: andi a1, a1, 1
; RV32-NEXT: neg s1, a1
; RV32-NEXT: neg s3, a1
; RV32-NEXT: slli a1, a2, 31
; RV32-NEXT: srli a0, a0, 1
; RV32-NEXT: or a0, a0, a1
@ -327,17 +327,17 @@ define void @test_srem_vec(<3 x i33>* %X) nounwind {
; RV32-NEXT: mv s6, a1
; RV32-NEXT: li a2, -5
; RV32-NEXT: li a3, -1
; RV32-NEXT: mv a0, s3
; RV32-NEXT: mv a1, s1
; RV32-NEXT: mv a0, s2
; RV32-NEXT: mv a1, s3
; RV32-NEXT: call __moddi3@plt
; RV32-NEXT: mv s1, a0
; RV32-NEXT: mv s2, a0
; RV32-NEXT: mv s3, a1
; RV32-NEXT: li a2, 6
; RV32-NEXT: mv a0, s4
; RV32-NEXT: mv a1, s2
; RV32-NEXT: mv a1, s1
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __moddi3@plt
; RV32-NEXT: xori a2, s1, 2
; RV32-NEXT: xori a2, s2, 2
; RV32-NEXT: or a2, a2, s3
; RV32-NEXT: snez a2, a2
; RV32-NEXT: xori a3, s5, 1
@ -460,13 +460,13 @@ define void @test_srem_vec(<3 x i33>* %X) nounwind {
; RV32M-NEXT: lbu a1, 12(s0)
; RV32M-NEXT: lw a2, 8(s0)
; RV32M-NEXT: andi a3, a0, 1
; RV32M-NEXT: neg s2, a3
; RV32M-NEXT: neg s1, a3
; RV32M-NEXT: slli a3, a1, 30
; RV32M-NEXT: srli a4, a2, 2
; RV32M-NEXT: or s3, a4, a3
; RV32M-NEXT: or s2, a4, a3
; RV32M-NEXT: srli a1, a1, 2
; RV32M-NEXT: andi a1, a1, 1
; RV32M-NEXT: neg s1, a1
; RV32M-NEXT: neg s3, a1
; RV32M-NEXT: slli a1, a2, 31
; RV32M-NEXT: srli a0, a0, 1
; RV32M-NEXT: or a0, a0, a1
@ -481,17 +481,17 @@ define void @test_srem_vec(<3 x i33>* %X) nounwind {
; RV32M-NEXT: mv s6, a1
; RV32M-NEXT: li a2, -5
; RV32M-NEXT: li a3, -1
; RV32M-NEXT: mv a0, s3
; RV32M-NEXT: mv a1, s1
; RV32M-NEXT: mv a0, s2
; RV32M-NEXT: mv a1, s3
; RV32M-NEXT: call __moddi3@plt
; RV32M-NEXT: mv s1, a0
; RV32M-NEXT: mv s2, a0
; RV32M-NEXT: mv s3, a1
; RV32M-NEXT: li a2, 6
; RV32M-NEXT: mv a0, s4
; RV32M-NEXT: mv a1, s2
; RV32M-NEXT: mv a1, s1
; RV32M-NEXT: li a3, 0
; RV32M-NEXT: call __moddi3@plt
; RV32M-NEXT: xori a2, s1, 2
; RV32M-NEXT: xori a2, s2, 2
; RV32M-NEXT: or a2, a2, s3
; RV32M-NEXT: snez a2, a2
; RV32M-NEXT: xori a3, s5, 1

976
llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
View File

File diff suppressed because it is too large Load Diff

14
llvm/test/CodeGen/RISCV/ssub_sat.ll
View File

@ -156,16 +156,16 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; RV32IZbbZbt-NEXT: sltu a4, a0, a2
; RV32IZbbZbt-NEXT: sub a5, a1, a3
; RV32IZbbZbt-NEXT: sub a4, a5, a4
; RV32IZbbZbt-NEXT: srai a6, a4, 31
; RV32IZbbZbt-NEXT: lui a5, 524288
; RV32IZbbZbt-NEXT: xor a7, a6, a5
; RV32IZbbZbt-NEXT: xor a5, a1, a4
; RV32IZbbZbt-NEXT: srai a5, a4, 31
; RV32IZbbZbt-NEXT: lui a6, 524288
; RV32IZbbZbt-NEXT: xor a6, a5, a6
; RV32IZbbZbt-NEXT: xor a7, a1, a4
; RV32IZbbZbt-NEXT: xor a1, a1, a3
; RV32IZbbZbt-NEXT: and a1, a1, a5
; RV32IZbbZbt-NEXT: and a1, a1, a7
; RV32IZbbZbt-NEXT: slti a3, a1, 0
; RV32IZbbZbt-NEXT: cmov a1, a3, a7, a4
; RV32IZbbZbt-NEXT: cmov a1, a3, a6, a4
; RV32IZbbZbt-NEXT: sub a0, a0, a2
; RV32IZbbZbt-NEXT: cmov a0, a3, a6, a0
; RV32IZbbZbt-NEXT: cmov a0, a3, a5, a0
; RV32IZbbZbt-NEXT: ret
;
; RV64IZbbZbt-LABEL: func2:

16
llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
View File

@ -164,16 +164,16 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; RV32IZbbZbt-NEXT: sltu a2, a0, a4
; RV32IZbbZbt-NEXT: sub a3, a1, a5
; RV32IZbbZbt-NEXT: sub a2, a3, a2
; RV32IZbbZbt-NEXT: srai a6, a2, 31
; RV32IZbbZbt-NEXT: lui a3, 524288
; RV32IZbbZbt-NEXT: xor a7, a6, a3
; RV32IZbbZbt-NEXT: xor a3, a1, a2
; RV32IZbbZbt-NEXT: srai a3, a2, 31
; RV32IZbbZbt-NEXT: lui a6, 524288
; RV32IZbbZbt-NEXT: xor a6, a3, a6
; RV32IZbbZbt-NEXT: xor a7, a1, a2
; RV32IZbbZbt-NEXT: xor a1, a1, a5
; RV32IZbbZbt-NEXT: and a1, a1, a3
; RV32IZbbZbt-NEXT: slti a3, a1, 0
; RV32IZbbZbt-NEXT: cmov a1, a3, a7, a2
; RV32IZbbZbt-NEXT: and a1, a1, a7
; RV32IZbbZbt-NEXT: slti a5, a1, 0
; RV32IZbbZbt-NEXT: cmov a1, a5, a6, a2
; RV32IZbbZbt-NEXT: sub a0, a0, a4
; RV32IZbbZbt-NEXT: cmov a0, a3, a6, a0
; RV32IZbbZbt-NEXT: cmov a0, a5, a3, a0
; RV32IZbbZbt-NEXT: ret
;
; RV64IZbbZbt-LABEL: func64:

84
llvm/test/CodeGen/RISCV/stack-store-check.ll
View File

@ -32,12 +32,12 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: lw s6, %lo(U)(a0)
; CHECK-NEXT: lw s7, %lo(U+4)(a0)
; CHECK-NEXT: lw s8, %lo(U+8)(a0)
; CHECK-NEXT: lw s2, %lo(U+12)(a0)
; CHECK-NEXT: lw s0, %lo(U+12)(a0)
; CHECK-NEXT: sw zero, 612(sp)
; CHECK-NEXT: sw zero, 608(sp)
; CHECK-NEXT: sw zero, 604(sp)
; CHECK-NEXT: sw zero, 600(sp)
; CHECK-NEXT: sw s2, 596(sp)
; CHECK-NEXT: sw s0, 596(sp)
; CHECK-NEXT: sw s8, 592(sp)
; CHECK-NEXT: sw s7, 588(sp)
; CHECK-NEXT: addi a0, sp, 616
@ -45,21 +45,21 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: addi a2, sp, 584
; CHECK-NEXT: sw s6, 584(sp)
; CHECK-NEXT: call __subtf3@plt
; CHECK-NEXT: lw s4, 616(sp)
; CHECK-NEXT: lw s5, 620(sp)
; CHECK-NEXT: lw s9, 616(sp)
; CHECK-NEXT: lw s2, 620(sp)
; CHECK-NEXT: lw s3, 624(sp)
; CHECK-NEXT: lw s11, 628(sp)
; CHECK-NEXT: sw s2, 548(sp)
; CHECK-NEXT: lw s4, 628(sp)
; CHECK-NEXT: sw s0, 548(sp)
; CHECK-NEXT: sw s8, 544(sp)
; CHECK-NEXT: sw s7, 540(sp)
; CHECK-NEXT: sw s6, 536(sp)
; CHECK-NEXT: sw s11, 564(sp)
; CHECK-NEXT: sw s4, 564(sp)
; CHECK-NEXT: sw s3, 560(sp)
; CHECK-NEXT: sw s5, 556(sp)
; CHECK-NEXT: sw s2, 556(sp)
; CHECK-NEXT: addi a0, sp, 568
; CHECK-NEXT: addi a1, sp, 552
; CHECK-NEXT: addi a2, sp, 536
; CHECK-NEXT: sw s4, 552(sp)
; CHECK-NEXT: sw s9, 552(sp)
; CHECK-NEXT: call __subtf3@plt
; CHECK-NEXT: lw a0, 568(sp)
; CHECK-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
@ -73,7 +73,7 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: sw zero, 496(sp)
; CHECK-NEXT: sw zero, 492(sp)
; CHECK-NEXT: sw zero, 488(sp)
; CHECK-NEXT: sw s2, 516(sp)
; CHECK-NEXT: sw s0, 516(sp)
; CHECK-NEXT: sw s8, 512(sp)
; CHECK-NEXT: sw s7, 508(sp)
; CHECK-NEXT: addi a0, sp, 520
@ -81,10 +81,10 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: addi a2, sp, 488
; CHECK-NEXT: sw s6, 504(sp)
; CHECK-NEXT: call __addtf3@plt
; CHECK-NEXT: lw s9, 520(sp)
; CHECK-NEXT: lw s11, 520(sp)
; CHECK-NEXT: lw s10, 524(sp)
; CHECK-NEXT: lw s0, 528(sp)
; CHECK-NEXT: sw s0, 20(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw s5, 528(sp)
; CHECK-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw s1, 532(sp)
; CHECK-NEXT: sw s1, 16(sp) # 4-byte Folded Spill
; CHECK-NEXT: lui a0, %hi(Y1)
@ -100,13 +100,13 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: sw a3, 304(sp)
; CHECK-NEXT: sw a2, 300(sp)
; CHECK-NEXT: sw a1, 296(sp)
; CHECK-NEXT: sw s11, 324(sp)
; CHECK-NEXT: sw s4, 324(sp)
; CHECK-NEXT: sw s3, 320(sp)
; CHECK-NEXT: sw s5, 316(sp)
; CHECK-NEXT: sw s2, 316(sp)
; CHECK-NEXT: addi a0, sp, 328
; CHECK-NEXT: addi a1, sp, 312
; CHECK-NEXT: addi a2, sp, 296
; CHECK-NEXT: sw s4, 312(sp)
; CHECK-NEXT: sw s9, 312(sp)
; CHECK-NEXT: call __multf3@plt
; CHECK-NEXT: lw a0, 328(sp)
; CHECK-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
@ -114,18 +114,18 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, 336(sp)
; CHECK-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw s4, 340(sp)
; CHECK-NEXT: sw s2, 468(sp)
; CHECK-NEXT: lw s9, 340(sp)
; CHECK-NEXT: sw s0, 468(sp)
; CHECK-NEXT: sw s8, 464(sp)
; CHECK-NEXT: sw s7, 460(sp)
; CHECK-NEXT: sw s6, 456(sp)
; CHECK-NEXT: sw s1, 452(sp)
; CHECK-NEXT: sw s0, 448(sp)
; CHECK-NEXT: sw s5, 448(sp)
; CHECK-NEXT: sw s10, 444(sp)
; CHECK-NEXT: addi a0, sp, 472
; CHECK-NEXT: addi a1, sp, 456
; CHECK-NEXT: addi a2, sp, 440
; CHECK-NEXT: sw s9, 440(sp)
; CHECK-NEXT: sw s11, 440(sp)
; CHECK-NEXT: call __addtf3@plt
; CHECK-NEXT: lw a3, 472(sp)
; CHECK-NEXT: lw a0, 476(sp)
@ -152,31 +152,31 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: sw a2, %lo(X+8)(a4)
; CHECK-NEXT: sw a3, %lo(X+4)(a4)
; CHECK-NEXT: sw a0, %lo(X)(a4)
; CHECK-NEXT: lw s8, 4(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s8, 212(sp)
; CHECK-NEXT: lw s7, 8(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s7, 208(sp)
; CHECK-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s11, 204(sp)
; CHECK-NEXT: lw s4, 4(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s4, 212(sp)
; CHECK-NEXT: lw s3, 8(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s3, 208(sp)
; CHECK-NEXT: lw s2, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s2, 204(sp)
; CHECK-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 200(sp)
; CHECK-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 228(sp)
; CHECK-NEXT: lw s3, 24(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s3, 224(sp)
; CHECK-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s2, 220(sp)
; CHECK-NEXT: lw s1, 24(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s1, 224(sp)
; CHECK-NEXT: lw s0, 32(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s0, 220(sp)
; CHECK-NEXT: addi a0, sp, 232
; CHECK-NEXT: addi a1, sp, 216
; CHECK-NEXT: addi a2, sp, 200
; CHECK-NEXT: lw s1, 40(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s1, 216(sp)
; CHECK-NEXT: lw s8, 40(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s8, 216(sp)
; CHECK-NEXT: call __multf3@plt
; CHECK-NEXT: lw s5, 232(sp)
; CHECK-NEXT: lw a0, 236(sp)
; CHECK-NEXT: sw a0, 0(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw s6, 240(sp)
; CHECK-NEXT: lw s0, 244(sp)
; CHECK-NEXT: lw s7, 244(sp)
; CHECK-NEXT: sw zero, 356(sp)
; CHECK-NEXT: sw zero, 352(sp)
; CHECK-NEXT: sw zero, 348(sp)
@ -189,7 +189,7 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: addi a0, sp, 376
; CHECK-NEXT: addi a1, sp, 360
; CHECK-NEXT: addi a2, sp, 344
; CHECK-NEXT: sw s9, 360(sp)
; CHECK-NEXT: sw s11, 360(sp)
; CHECK-NEXT: call __multf3@plt
; CHECK-NEXT: lw a0, 376(sp)
; CHECK-NEXT: lw a1, 388(sp)
@ -202,10 +202,10 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: sw a0, %lo(S)(a4)
; CHECK-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 260(sp)
; CHECK-NEXT: sw s3, 256(sp)
; CHECK-NEXT: sw s2, 252(sp)
; CHECK-NEXT: sw s1, 248(sp)
; CHECK-NEXT: sw s4, 276(sp)
; CHECK-NEXT: sw s1, 256(sp)
; CHECK-NEXT: sw s0, 252(sp)
; CHECK-NEXT: sw s8, 248(sp)
; CHECK-NEXT: sw s9, 276(sp)
; CHECK-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 272(sp)
; CHECK-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
@ -229,7 +229,7 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: sw zero, 160(sp)
; CHECK-NEXT: sw zero, 156(sp)
; CHECK-NEXT: sw zero, 152(sp)
; CHECK-NEXT: sw s0, 180(sp)
; CHECK-NEXT: sw s7, 180(sp)
; CHECK-NEXT: sw s6, 176(sp)
; CHECK-NEXT: lw a0, 0(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 172(sp)
@ -251,9 +251,9 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: sw zero, 112(sp)
; CHECK-NEXT: sw zero, 108(sp)
; CHECK-NEXT: sw zero, 104(sp)
; CHECK-NEXT: sw s8, 132(sp)
; CHECK-NEXT: sw s7, 128(sp)
; CHECK-NEXT: sw s11, 124(sp)
; CHECK-NEXT: sw s4, 132(sp)
; CHECK-NEXT: sw s3, 128(sp)
; CHECK-NEXT: sw s2, 124(sp)
; CHECK-NEXT: addi a0, sp, 136
; CHECK-NEXT: addi a1, sp, 120
; CHECK-NEXT: addi a2, sp, 104

8
llvm/test/CodeGen/RISCV/tail-calls.ll
View File

@ -45,12 +45,12 @@ define void @caller_indirect_tail(i32 %a) nounwind {
; CHECK-NOT: tail callee_indirect2
; CHECK: lui a0, %hi(callee_indirect2)
; CHECK-NEXT: addi a5, a0, %lo(callee_indirect2)
; CHECK-NEXT: jr a5
; CHECK-NEXT: addi t1, a0, %lo(callee_indirect2)
; CHECK-NEXT: jr t1
; CHECK: lui a0, %hi(callee_indirect1)
; CHECK-NEXT: addi a5, a0, %lo(callee_indirect1)
; CHECK-NEXT: jr a5
; CHECK-NEXT: addi t1, a0, %lo(callee_indirect1)
; CHECK-NEXT: jr t1
entry:
%tobool = icmp eq i32 %a, 0
%callee = select i1 %tobool, void ()* @callee_indirect1, void ()* @callee_indirect2

146
llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
View File

@ -10,103 +10,99 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 {
; RISCV32-NEXT: sw s2, 20(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s3, 16(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s4, 12(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s5, 8(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s6, 4(sp) # 4-byte Folded Spill
; RISCV32-NEXT: lw a6, 12(a1)
; RISCV32-NEXT: lw a3, 12(a1)
; RISCV32-NEXT: lw a7, 12(a2)
; RISCV32-NEXT: lw t3, 8(a1)
; RISCV32-NEXT: lw a6, 8(a1)
; RISCV32-NEXT: lw a4, 0(a2)
; RISCV32-NEXT: lw a5, 0(a1)
; RISCV32-NEXT: lw a3, 4(a1)
; RISCV32-NEXT: lw s2, 8(a2)
; RISCV32-NEXT: lw t3, 4(a1)
; RISCV32-NEXT: lw t0, 8(a2)
; RISCV32-NEXT: lw a2, 4(a2)
; RISCV32-NEXT: mulhu a1, a5, a4
; RISCV32-NEXT: mul s1, a3, a4
; RISCV32-NEXT: add a1, s1, a1
; RISCV32-NEXT: sltu s1, a1, s1
; RISCV32-NEXT: mulhu s0, a3, a4
; RISCV32-NEXT: add t4, s0, s1
; RISCV32-NEXT: mul s0, a5, a2
; RISCV32-NEXT: add t0, s0, a1
; RISCV32-NEXT: sltu a1, t0, s0
; RISCV32-NEXT: mulhu s0, a5, a2
; RISCV32-NEXT: add a1, s0, a1
; RISCV32-NEXT: add a1, t4, a1
; RISCV32-NEXT: mul s0, a3, a2
; RISCV32-NEXT: add s1, s0, a1
; RISCV32-NEXT: mul t1, s2, a5
; RISCV32-NEXT: mul s3, t3, a4
; RISCV32-NEXT: mul t1, t3, a4
; RISCV32-NEXT: add a1, t1, a1
; RISCV32-NEXT: sltu t1, a1, t1
; RISCV32-NEXT: mulhu t2, t3, a4
; RISCV32-NEXT: add t4, t2, t1
; RISCV32-NEXT: mul t1, a5, a2
; RISCV32-NEXT: add a1, t1, a1
; RISCV32-NEXT: sltu t1, a1, t1
; RISCV32-NEXT: mulhu t2, a5, a2
; RISCV32-NEXT: add t1, t2, t1
; RISCV32-NEXT: add t5, t4, t1
; RISCV32-NEXT: mul t6, t3, a2
; RISCV32-NEXT: add s0, t6, t5
; RISCV32-NEXT: mul t1, t0, a5
; RISCV32-NEXT: mul s3, a6, a4
; RISCV32-NEXT: add s4, s3, t1
; RISCV32-NEXT: add t1, s1, s4
; RISCV32-NEXT: sltu t2, t1, s1
; RISCV32-NEXT: sltu s1, s1, s0
; RISCV32-NEXT: sltu a1, a1, t4
; RISCV32-NEXT: mulhu s0, a3, a2
; RISCV32-NEXT: add a1, s0, a1
; RISCV32-NEXT: add s0, a1, s1
; RISCV32-NEXT: mul a1, a3, s2
; RISCV32-NEXT: mul s1, a7, a5
; RISCV32-NEXT: add a1, s1, a1
; RISCV32-NEXT: mulhu s5, s2, a5
; RISCV32-NEXT: add s6, s5, a1
; RISCV32-NEXT: mul s1, a2, t3
; RISCV32-NEXT: mul a1, a6, a4
; RISCV32-NEXT: add a1, a1, s1
; RISCV32-NEXT: mulhu t5, t3, a4
; RISCV32-NEXT: add t6, t5, a1
; RISCV32-NEXT: add a1, t6, s6
; RISCV32-NEXT: sltu s1, s4, s3
; RISCV32-NEXT: add a1, a1, s1
; RISCV32-NEXT: add a1, s0, a1
; RISCV32-NEXT: add t4, a1, t2
; RISCV32-NEXT: add t1, s0, s4
; RISCV32-NEXT: sltu t2, t1, s0
; RISCV32-NEXT: sltu t6, s0, t6
; RISCV32-NEXT: sltu t4, t5, t4
; RISCV32-NEXT: mulhu t5, t3, a2
; RISCV32-NEXT: add t4, t5, t4
; RISCV32-NEXT: add s0, t4, t6
; RISCV32-NEXT: mul t4, t3, t0
; RISCV32-NEXT: mul t5, a7, a5
; RISCV32-NEXT: add t4, t5, t4
; RISCV32-NEXT: mulhu s1, t0, a5
; RISCV32-NEXT: add s2, s1, t4
; RISCV32-NEXT: mul t4, a2, a6
; RISCV32-NEXT: mul t5, a3, a4
; RISCV32-NEXT: add t4, t5, t4
; RISCV32-NEXT: mulhu t5, a6, a4
; RISCV32-NEXT: add t6, t5, t4
; RISCV32-NEXT: add t4, t6, s2
; RISCV32-NEXT: sltu s3, s4, s3
; RISCV32-NEXT: add t4, t4, s3
; RISCV32-NEXT: add t4, s0, t4
; RISCV32-NEXT: add t4, t4, t2
; RISCV32-NEXT: beq t4, s0, .LBB0_2
; RISCV32-NEXT: # %bb.1: # %start
; RISCV32-NEXT: sltu t2, t4, s0
; RISCV32-NEXT: .LBB0_2: # %start
; RISCV32-NEXT: sltu a1, s6, s5
; RISCV32-NEXT: sltu s0, s2, s1
; RISCV32-NEXT: snez s1, t3
; RISCV32-NEXT: snez s2, a7
; RISCV32-NEXT: and s1, s2, s1
; RISCV32-NEXT: mulhu s2, a7, a5
; RISCV32-NEXT: snez s2, s2
; RISCV32-NEXT: or s1, s1, s2
; RISCV32-NEXT: mulhu t3, t3, t0
; RISCV32-NEXT: snez t3, t3
; RISCV32-NEXT: or t3, s1, t3
; RISCV32-NEXT: or t3, t3, s0
; RISCV32-NEXT: sltu t5, t6, t5
; RISCV32-NEXT: snez t6, a2
; RISCV32-NEXT: snez s0, a3
; RISCV32-NEXT: snez s1, a7
; RISCV32-NEXT: and s0, s1, s0
; RISCV32-NEXT: mulhu s1, a7, a5
; RISCV32-NEXT: snez s1, s1
; RISCV32-NEXT: or s0, s0, s1
; RISCV32-NEXT: mulhu a3, a3, s2
; RISCV32-NEXT: snez a3, a3
; RISCV32-NEXT: or a3, s0, a3
; RISCV32-NEXT: or a1, a3, a1
; RISCV32-NEXT: sltu a3, t6, t5
; RISCV32-NEXT: snez s1, a2
; RISCV32-NEXT: snez s0, a6
; RISCV32-NEXT: and s1, s0, s1
; RISCV32-NEXT: mulhu s0, a6, a4
; RISCV32-NEXT: and t6, s0, t6
; RISCV32-NEXT: mulhu s0, a3, a4
; RISCV32-NEXT: snez s0, s0
; RISCV32-NEXT: or s1, s1, s0
; RISCV32-NEXT: mulhu a2, a2, t3
; RISCV32-NEXT: or t6, t6, s0
; RISCV32-NEXT: mulhu a2, a2, a6
; RISCV32-NEXT: snez a2, a2
; RISCV32-NEXT: or a2, s1, a2
; RISCV32-NEXT: or a2, a2, a3
; RISCV32-NEXT: or a3, s2, a7
; RISCV32-NEXT: or a2, t6, a2
; RISCV32-NEXT: or a2, a2, t5
; RISCV32-NEXT: or a7, t0, a7
; RISCV32-NEXT: snez a7, a7
; RISCV32-NEXT: or a3, a6, a3
; RISCV32-NEXT: snez a3, a3
; RISCV32-NEXT: or s1, t3, a6
; RISCV32-NEXT: snez s1, s1
; RISCV32-NEXT: and a3, s1, a3
; RISCV32-NEXT: and a3, a3, a7
; RISCV32-NEXT: or a2, a3, a2
; RISCV32-NEXT: or a1, a2, a1
; RISCV32-NEXT: or a1, a1, t2
; RISCV32-NEXT: mul a2, a5, a4
; RISCV32-NEXT: andi a1, a1, 1
; RISCV32-NEXT: sw a2, 0(a0)
; RISCV32-NEXT: sw t0, 4(a0)
; RISCV32-NEXT: or a2, a2, t3
; RISCV32-NEXT: or a2, a2, t2
; RISCV32-NEXT: mul a3, a5, a4
; RISCV32-NEXT: andi a2, a2, 1
; RISCV32-NEXT: sw a3, 0(a0)
; RISCV32-NEXT: sw a1, 4(a0)
; RISCV32-NEXT: sw t1, 8(a0)
; RISCV32-NEXT: sw t4, 12(a0)
; RISCV32-NEXT: sb a1, 16(a0)
; RISCV32-NEXT: sb a2, 16(a0)
; RISCV32-NEXT: lw s0, 28(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s1, 24(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s2, 20(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s3, 16(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s4, 12(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s5, 8(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s6, 4(sp) # 4-byte Folded Reload
; RISCV32-NEXT: addi sp, sp, 32
; RISCV32-NEXT: ret
start:

12
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
View File

@ -394,8 +394,8 @@ define void @test_urem_vec(<3 x i11>* %X) nounwind {
; RV64-NEXT: lwu a1, 0(s0)
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: srli s2, a0, 11
; RV64-NEXT: srli s1, a0, 22
; RV64-NEXT: srli s1, a0, 11
; RV64-NEXT: srli s2, a0, 22
; RV64-NEXT: andi a0, a0, 2047
; RV64-NEXT: li a1, 683
; RV64-NEXT: call __muldi3@plt
@ -407,14 +407,14 @@ define void @test_urem_vec(<3 x i11>* %X) nounwind {
; RV64-NEXT: li a1, 341
; RV64-NEXT: sltu s3, a1, a0
; RV64-NEXT: li a1, 819
; RV64-NEXT: mv a0, s1
; RV64-NEXT: mv a0, s2
; RV64-NEXT: call __muldi3@plt
; RV64-NEXT: addiw a0, a0, -1638
; RV64-NEXT: andi a0, a0, 2047
; RV64-NEXT: li a1, 1
; RV64-NEXT: sltu s1, a1, a0
; RV64-NEXT: sltu s2, a1, a0
; RV64-NEXT: li a1, 1463
; RV64-NEXT: mv a0, s2
; RV64-NEXT: mv a0, s1
; RV64-NEXT: call __muldi3@plt
; RV64-NEXT: addiw a0, a0, -1463
; RV64-NEXT: andi a0, a0, 2047
@ -426,7 +426,7 @@ define void @test_urem_vec(<3 x i11>* %X) nounwind {
; RV64-NEXT: andi a0, a0, 2047
; RV64-NEXT: slli a0, a0, 11
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: slli a1, s1, 22
; RV64-NEXT: slli a1, s2, 22
; RV64-NEXT: sub a0, a0, a1
; RV64-NEXT: sw a0, 0(s0)
; RV64-NEXT: slli a0, a0, 31

978
llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
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File diff suppressed because it is too large Load Diff

16
llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
View File

@ -16,18 +16,18 @@ define void @vec3_setcc_crash(<3 x i8>* %in, <3 x i8>* %out) {
; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: and a2, a0, a2
; RV32-NEXT: slli a3, a2, 16
; RV32-NEXT: srai a6, a3, 24
; RV32-NEXT: srai a3, a3, 24
; RV32-NEXT: slli a4, a0, 24
; RV32-NEXT: srai a3, a4, 24
; RV32-NEXT: srai a6, a4, 24
; RV32-NEXT: slli a4, a0, 8
; RV32-NEXT: mv a5, a0
; RV32-NEXT: bgtz a3, .LBB0_2
; RV32-NEXT: bgtz a6, .LBB0_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a5, 0
; RV32-NEXT: .LBB0_2:
; RV32-NEXT: srai a4, a4, 24
; RV32-NEXT: andi a5, a5, 255
; RV32-NEXT: bgtz a6, .LBB0_4
; RV32-NEXT: bgtz a3, .LBB0_4
; RV32-NEXT: # %bb.3:
; RV32-NEXT: li a2, 0
; RV32-NEXT: j .LBB0_5
@ -54,18 +54,18 @@ define void @vec3_setcc_crash(<3 x i8>* %in, <3 x i8>* %out) {
; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: and a2, a0, a2
; RV64-NEXT: slli a3, a2, 48
; RV64-NEXT: srai a6, a3, 56
; RV64-NEXT: srai a3, a3, 56
; RV64-NEXT: slli a4, a0, 56
; RV64-NEXT: srai a3, a4, 56
; RV64-NEXT: srai a6, a4, 56
; RV64-NEXT: slli a4, a0, 40
; RV64-NEXT: mv a5, a0
; RV64-NEXT: bgtz a3, .LBB0_2
; RV64-NEXT: bgtz a6, .LBB0_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a5, 0
; RV64-NEXT: .LBB0_2:
; RV64-NEXT: srai a4, a4, 56
; RV64-NEXT: andi a5, a5, 255
; RV64-NEXT: bgtz a6, .LBB0_4
; RV64-NEXT: bgtz a3, .LBB0_4
; RV64-NEXT: # %bb.3:
; RV64-NEXT: li a2, 0
; RV64-NEXT: j .LBB0_5

840
llvm/test/CodeGen/RISCV/xaluo.ll
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File diff suppressed because it is too large Load Diff