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[Hexagon] Merge HexagonAlias.td into HexagonInstrAlias.td, NFC 

llvm-svn: 268641
This commit is contained in:
Krzysztof Parzyszek 2016-05-05 16:19:36 +00:00
parent 11dc82fa83
commit 8da817d1ca
3 changed files with 81 additions and 95 deletions
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1
llvm/lib/Target/Hexagon/Hexagon.td
View File

@ -251,7 +251,6 @@ include "HexagonCallingConv.td"
include "HexagonInstrInfo.td"
include "HexagonIntrinsics.td"
include "HexagonIntrinsicsDerived.td"
include "HexagonAlias.td"
def HexagonInstrInfo : InstrInfo;

94
llvm/lib/Target/Hexagon/HexagonAlias.td
View File

@ -1,94 +0,0 @@
//==- HexagonAlias.td - Hexagon Instruction Aliases ---------*- tablegen -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Hexagon Instruction Mappings
//===----------------------------------------------------------------------===//
// V6_vassignp: Vector assign mapping.
let hasNewValue = 1, opNewValue = 0, isAsmParserOnly = 1 in
def HEXAGON_V6_vassignpair: CVI_VA_DV_Resource <
(outs VecDblRegs:$Vdd),
(ins VecDblRegs:$Vss),
"$Vdd = $Vss">;
// maps Vd = #0 to Vd = vxor(Vd, Vd)
def : InstAlias<"$Vd = #0",
(V6_vxor VectorRegs:$Vd, VectorRegs:$Vd, VectorRegs:$Vd)>,
Requires<[HasV60T]>;
// maps Vdd = #0 to Vdd = vsub(Vdd, Vdd)
def : InstAlias<"$Vdd = #0",
(V6_vsubw_dv VecDblRegs:$Vdd, VecDblRegs:$Vdd, VecDblRegs:$Vdd)>,
Requires<[HasV60T]>;
// maps "$Qd = vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd = vcmp.eq($Vu.h, $Vv.h)"
def : InstAlias<"$Qd = vcmp.eq($Vu.uh, $Vv.uh)",
(V6_veqh VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd &= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd &= vcmp.eq($Vu.h, $Vv.h)"
def : InstAlias<"$Qd &= vcmp.eq($Vu.uh, $Vv.uh)",
(V6_veqh_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd |= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd |= vcmp.eq($Vu.h, $Vv.h)"
def : InstAlias<"$Qd |= vcmp.eq($Vu.uh, $Vv.uh)",
(V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd ^= vcmp.eq($Vu.h, $Vv.h)"
def : InstAlias<"$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)",
(V6_veqh_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd = vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd = vcmp.eq($Vu.w, $Vv.w)"
def : InstAlias<"$Qd = vcmp.eq($Vu.uw, $Vv.uw)",
(V6_veqw VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd &= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd &= vcmp.eq($Vu.w, $Vv.w)"
def : InstAlias<"$Qd &= vcmp.eq($Vu.uw, $Vv.uw)",
(V6_veqw_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd |= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd |= vcmp.eq($Vu.w, $Vv.w)"
def : InstAlias<"$Qd |= vcmp.eq($Vu.uw, $Vv.uw)",
(V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd ^= vcmp.eq($Vu.w, $Vv.w)"
def : InstAlias<"$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)",
(V6_veqw_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd = vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd = vcmp.eq($Vu.b, $Vv.b)"
def : InstAlias<"$Qd = vcmp.eq($Vu.ub, $Vv.ub)",
(V6_veqb VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd &= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd &= vcmp.eq($Vu.b, $Vv.b)"
def : InstAlias<"$Qd &= vcmp.eq($Vu.ub, $Vv.ub)",
(V6_veqb_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd |= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd |= vcmp.eq($Vu.b, $Vv.b)"
def : InstAlias<"$Qd |= vcmp.eq($Vu.ub, $Vv.ub)",
(V6_veqb_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd ^= vcmp.eq($Vu.b, $Vv.b)"
def : InstAlias<"$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)",
(V6_veqb_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Rd.w = vextract($Vu, $Rs)" -> "$Rd = vextract($Vu, $Rs)"
def : InstAlias<"$Rd.w = vextract($Vu, $Rs)",
(V6_extractw IntRegs:$Rd, VectorRegs:$Vu, IntRegs:$Rs)>,
Requires<[HasV60T]>;

81
llvm/lib/Target/Hexagon/HexagonInstrAlias.td
View File

@ -460,3 +460,84 @@ def : InstAlias<"$Pd=cmp.lt($Rs, $Rt)",
def : InstAlias<"$Pd=cmp.ltu($Rs, $Rt)",
(C2_cmpgtu PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>;
// V6_vassignp: Vector assign mapping.
let hasNewValue = 1, opNewValue = 0, isAsmParserOnly = 1 in
def HEXAGON_V6_vassignpair: CVI_VA_DV_Resource <
(outs VecDblRegs:$Vdd),
(ins VecDblRegs:$Vss),
"$Vdd = $Vss">;
// maps Vd = #0 to Vd = vxor(Vd, Vd)
def : InstAlias<"$Vd = #0",
(V6_vxor VectorRegs:$Vd, VectorRegs:$Vd, VectorRegs:$Vd)>,
Requires<[HasV60T]>;
// maps Vdd = #0 to Vdd = vsub(Vdd, Vdd)
def : InstAlias<"$Vdd = #0",
(V6_vsubw_dv VecDblRegs:$Vdd, VecDblRegs:$Vdd, VecDblRegs:$Vdd)>,
Requires<[HasV60T]>;
// maps "$Qd = vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd = vcmp.eq($Vu.h, $Vv.h)"
def : InstAlias<"$Qd = vcmp.eq($Vu.uh, $Vv.uh)",
(V6_veqh VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd &= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd &= vcmp.eq($Vu.h, $Vv.h)"
def : InstAlias<"$Qd &= vcmp.eq($Vu.uh, $Vv.uh)",
(V6_veqh_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd |= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd |= vcmp.eq($Vu.h, $Vv.h)"
def : InstAlias<"$Qd |= vcmp.eq($Vu.uh, $Vv.uh)",
(V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd ^= vcmp.eq($Vu.h, $Vv.h)"
def : InstAlias<"$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)",
(V6_veqh_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd = vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd = vcmp.eq($Vu.w, $Vv.w)"
def : InstAlias<"$Qd = vcmp.eq($Vu.uw, $Vv.uw)",
(V6_veqw VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd &= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd &= vcmp.eq($Vu.w, $Vv.w)"
def : InstAlias<"$Qd &= vcmp.eq($Vu.uw, $Vv.uw)",
(V6_veqw_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd |= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd |= vcmp.eq($Vu.w, $Vv.w)"
def : InstAlias<"$Qd |= vcmp.eq($Vu.uw, $Vv.uw)",
(V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd ^= vcmp.eq($Vu.w, $Vv.w)"
def : InstAlias<"$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)",
(V6_veqw_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd = vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd = vcmp.eq($Vu.b, $Vv.b)"
def : InstAlias<"$Qd = vcmp.eq($Vu.ub, $Vv.ub)",
(V6_veqb VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd &= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd &= vcmp.eq($Vu.b, $Vv.b)"
def : InstAlias<"$Qd &= vcmp.eq($Vu.ub, $Vv.ub)",
(V6_veqb_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd |= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd |= vcmp.eq($Vu.b, $Vv.b)"
def : InstAlias<"$Qd |= vcmp.eq($Vu.ub, $Vv.ub)",
(V6_veqb_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd ^= vcmp.eq($Vu.b, $Vv.b)"
def : InstAlias<"$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)",
(V6_veqb_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
Requires<[HasV60T]>;
// maps "$Rd.w = vextract($Vu, $Rs)" -> "$Rd = vextract($Vu, $Rs)"
def : InstAlias<"$Rd.w = vextract($Vu, $Rs)",
(V6_extractw IntRegs:$Rd, VectorRegs:$Vu, IntRegs:$Rs)>,
Requires<[HasV60T]>;