forked from OSchip/llvm-project
[DAGCombiner] Remove an unused argument from tryFoldToZero. NFC
llvm-svn: 346118
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@ -2540,8 +2540,7 @@ SDValue DAGCombiner::visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
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// Since it may not be valid to emit a fold to zero for vector initializers
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// check if we can before folding.
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static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT,
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SelectionDAG &DAG, bool LegalOperations,
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bool LegalTypes) {
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SelectionDAG &DAG, bool LegalOperations) {
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if (!VT.isVector())
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return DAG.getConstant(0, DL, VT);
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if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
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@ -2568,7 +2567,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
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// fold (sub x, x) -> 0
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// FIXME: Refactor this and xor and other similar operations together.
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if (N0 == N1)
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return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations, LegalTypes);
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return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
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if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
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DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
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// fold (sub c1, c2) -> c1-c2
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@ -6154,7 +6153,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
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// fold (xor x, x) -> 0
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if (N0 == N1)
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return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
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return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations);
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// fold (xor (shl 1, x), -1) -> (rotl ~1, x)
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// Here is a concrete example of this equivalence:
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