forked from OSchip/llvm-project
[AArch64] Disable LDP/STP for quads
Disable LDP/STP for quads on Exynos M1 as they are not as efficient as pairs of regular LDR/STR. Patch by Abderrazek Zaafrani <a.zaafrani@samsung.com>. llvm-svn: 266223
This commit is contained in:
Evandro Menezes
parent
5927257206
commit
8d53f88162
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@ -1409,6 +1409,20 @@ bool AArch64InstrInfo::isCandidateToMergeOrPair(MachineInstr *MI) const {
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if (isLdStPairSuppressed(MI))
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return false;
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// Do not pair quad ld/st for Exynos.
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if (Subtarget.isExynosM1()) {
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switch (MI->getOpcode()) {
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default:
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break;
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case AArch64::LDURQi:
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case AArch64::STURQi:
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case AArch64::LDRQui:
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case AArch64::STRQui:
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return false;
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}
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}
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return true;
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}
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@ -1,5 +1,6 @@
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; REQUIRES: asserts
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; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m1 -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck --check-prefix=EXYNOS %s
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; Test ldr clustering.
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; CHECK: ********** MI Scheduling **********
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@ -7,6 +8,11 @@
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; CHECK: Cluster loads SU(1) - SU(2)
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; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
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; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldr_int:BB#0
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; EXYNOS: Cluster loads SU(1) - SU(2)
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; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
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; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
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define i32 @ldr_int(i32* %a) nounwind {
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%p1 = getelementptr inbounds i32, i32* %a, i32 1
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%tmp1 = load i32, i32* %p1, align 2
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@ -22,6 +28,11 @@ define i32 @ldr_int(i32* %a) nounwind {
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; CHECK: Cluster loads SU(1) - SU(2)
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; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
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; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldp_sext_int:BB#0
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; EXYNOS: Cluster loads SU(1) - SU(2)
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; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
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; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
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define i64 @ldp_sext_int(i32* %p) nounwind {
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%tmp = load i32, i32* %p, align 4
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%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
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@ -38,6 +49,11 @@ define i64 @ldp_sext_int(i32* %p) nounwind {
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; CHECK: Cluster loads SU(2) - SU(1)
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; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDURWi
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; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDURWi
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldur_int:BB#0
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; EXYNOS: Cluster loads SU(2) - SU(1)
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; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDURWi
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; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDURWi
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define i32 @ldur_int(i32* %a) nounwind {
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%p1 = getelementptr inbounds i32, i32* %a, i32 -1
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%tmp1 = load i32, i32* %p1, align 2
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@ -53,6 +69,11 @@ define i32 @ldur_int(i32* %a) nounwind {
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; CHECK: Cluster loads SU(3) - SU(4)
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; CHECK: SU(3): %vreg{{[0-9]+}}<def> = LDRSWui
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; CHECK: SU(4): %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldp_half_sext_zext_int:BB#0
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; EXYNOS: Cluster loads SU(3) - SU(4)
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; EXYNOS: SU(3): %vreg{{[0-9]+}}<def> = LDRSWui
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; EXYNOS: SU(4): %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
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define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
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%tmp0 = load i64, i64* %q, align 4
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%tmp = load i32, i32* %p, align 4
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@ -71,6 +92,11 @@ define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
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; CHECK: Cluster loads SU(3) - SU(4)
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; CHECK: SU(3): %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
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; CHECK: SU(4): %vreg{{[0-9]+}}<def> = LDRSWui
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldp_half_zext_sext_int:BB#0
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; EXYNOS: Cluster loads SU(3) - SU(4)
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; EXYNOS: SU(3): %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
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; EXYNOS: SU(4): %vreg{{[0-9]+}}<def> = LDRSWui
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define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
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%tmp0 = load i64, i64* %q, align 4
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%tmp = load i32, i32* %p, align 4
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@ -89,6 +115,11 @@ define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
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; CHECK-NOT: Cluster loads
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; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
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; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldr_int_volatile:BB#0
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; EXYNOS-NOT: Cluster loads
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; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
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; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
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define i32 @ldr_int_volatile(i32* %a) nounwind {
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%p1 = getelementptr inbounds i32, i32* %a, i32 1
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%tmp1 = load volatile i32, i32* %p1, align 2
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@ -97,3 +128,23 @@ define i32 @ldr_int_volatile(i32* %a) nounwind {
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%tmp3 = add i32 %tmp1, %tmp2
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ret i32 %tmp3
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}
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; Test ldq clustering (no clustering for Exynos).
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: ldq_cluster:BB#0
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; CHECK: Cluster loads SU(1) - SU(3)
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; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRQui
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; CHECK: SU(3): %vreg{{[0-9]+}}<def> = LDRQui
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; EXYNOS: ********** MI Scheduling **********
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; EXYNOS-LABEL: ldq_cluster:BB#0
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; EXYNOS-NOT: Cluster loads
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define <2 x i64> @ldq_cluster(i64* %p) {
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%a1 = bitcast i64* %p to <2 x i64>*
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%tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8
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%add.ptr2 = getelementptr inbounds i64, i64* %p, i64 2
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%a2 = bitcast i64* %add.ptr2 to <2 x i64>*
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%tmp2 = add nsw <2 x i64> %tmp1, %tmp1
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%tmp3 = load <2 x i64>, <2 x i64>* %a2, align 8
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%res = mul nsw <2 x i64> %tmp2, %tmp3
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ret <2 x i64> %res
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}
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@ -0,0 +1,28 @@
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; RUN: llc < %s -march=aarch64 -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s
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; CHECK-LABEL: test_exynos_nopair_st
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; CHECK: str
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; CHECK: stur
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; CHECK-NOT: stp
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define void @test_exynos_nopair_st(double* %ptr, <2 x double> %v1, <2 x double> %v2) {
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%tmp1 = bitcast double* %ptr to <2 x double>*
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store <2 x double> %v2, <2 x double>* %tmp1, align 16
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%add.ptr = getelementptr inbounds double, double* %ptr, i64 -2
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%tmp = bitcast double* %add.ptr to <2 x double>*
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store <2 x double> %v1, <2 x double>* %tmp, align 16
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ret void
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}
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; CHECK-LABEL: test_exynos_nopair_ld
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; CHECK: ldr
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; CHECK: ldr
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; CHECK-NOT: ldp
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define <2 x i64> @test_exynos_nopair_ld(i64* %p) {
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%a1 = bitcast i64* %p to <2 x i64>*
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%tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8
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%add.ptr2 = getelementptr inbounds i64, i64* %p, i64 2
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%a2 = bitcast i64* %add.ptr2 to <2 x i64>*
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%tmp2 = load <2 x i64>, <2 x i64>* %a2, align 8
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%add = add nsw <2 x i64> %tmp1, %tmp2
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ret <2 x i64> %add
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}
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