forked from OSchip/llvm-project
Followup to r106770: actually generate SXTB and SXTH for sign-extensions.
llvm-svn: 106940
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@ -459,11 +459,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
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// If the subtarget does not have extract instructions, sign_extend_inreg
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// needs to be expanded. Extract is available in ARM mode on v6 and up,
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// and on most Thumb2 implementations.
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if (!Subtarget->hasV6Ops()
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|| (Subtarget->isThumb2() && !Subtarget->hasT2ExtractPack())) {
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// Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
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if (!Subtarget->hasV6Ops()) {
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
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}
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