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[Sparc] Add floating-point register names 

Reviewers: jyknight

Reviewed By: jyknight

Subscribers: eraman, fedor.sergeev, jrtc27, cfe-commits

Differential Revision: https://reviews.llvm.org/D47137

llvm-svn: 333510
This commit is contained in:
Daniel Cederman 2018-05-30 06:02:18 +00:00
parent f6e79c6d3f
commit 8cc53aecad
3 changed files with 73 additions and 2 deletions
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10
clang/lib/Basic/Targets/Sparc.cpp
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@ -20,9 +20,17 @@ using namespace clang;
using namespace clang::targets;
const char *const SparcTargetInfo::GCCRegNames[] = {
// Integer registers
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
"r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
// Floating-point registers
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10",
"f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21",
"f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "f32",
"f34", "f36", "f38", "f40", "f42", "f44", "f46", "f48", "f50", "f52", "f54",
"f56", "f58", "f60", "f62",
};
ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {

33
clang/test/CodeGen/sparcv8-inline-asm.c
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@ -1,7 +1,7 @@
// RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
// CHECK: define float @fabsf(float %a)
// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float %{{.*}}) #1
// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float %{{.*}})
float fabsf(float a) {
float res;
__asm __volatile__("fabss %1, %0;"
@ -9,3 +9,34 @@ float fabsf(float a) {
: /* reg in */ "f"(a));
return res;
}
void test_gcc_registers(void) {
register unsigned int regO6 asm("o6") = 0;
register unsigned int regSP asm("sp") = 1;
register unsigned int reg14 asm("r14") = 2;
register unsigned int regI6 asm("i6") = 3;
register unsigned int regFP asm("fp") = 4;
register unsigned int reg30 asm("r30") = 5;
register float fF20 asm("f20") = 8.0;
register double dF20 asm("f20") = 11.0;
register long double qF20 asm("f20") = 14.0;
// Test remapping register names in register ... asm("rN") statments.
// CHECK: call void asm sideeffect "add $0,$1,$2", "{r14},{r14},{r14}"
asm volatile("add %0,%1,%2" : : "r" (regO6), "r" (regSP), "r" (reg14));
// CHECK: call void asm sideeffect "add $0,$1,$2", "{r30},{r30},{r30}"
asm volatile("add %0,%1,%2" : : "r" (regI6), "r" (regFP), "r" (reg30));
// CHECK: call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"
asm volatile("fadds %0,%1,%2" : : "f" (fF20), "f" (fF20), "f"(fF20));
// CHECK: call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"
asm volatile("faddd %0,%1,%2" : : "f" (dF20), "f" (dF20), "f"(dF20));
// CHECK: call void asm sideeffect "faddq $0,$1,$2", "{f20},{f20},{f20}"
asm volatile("faddq %0,%1,%2" : : "f" (qF20), "f" (qF20), "f"(qF20));
}

32
clang/test/CodeGen/sparcv9-inline-asm.c Normal file
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@ -0,0 +1,32 @@
// RUN: %clang_cc1 -triple sparcv9-unknown-unknown -emit-llvm %s -o - | FileCheck %s
void test_gcc_registers(void) {
register unsigned int regO6 asm("o6") = 0;
register unsigned int regSP asm("sp") = 1;
register unsigned int reg14 asm("r14") = 2;
register unsigned int regI6 asm("i6") = 3;
register unsigned int regFP asm("fp") = 4;
register unsigned int reg30 asm("r30") = 5;
register float fF20 asm("f20") = 8.0;
register double dF40 asm("f40") = 11.0;
register long double qF40 asm("f40") = 14.0;
// Test remapping register names in register ... asm("rN") statments.
// CHECK: call void asm sideeffect "add $0,$1,$2", "{r14},{r14},{r14}"
asm volatile("add %0,%1,%2" : : "r" (regO6), "r" (regSP), "r" (reg14));
// CHECK: call void asm sideeffect "add $0,$1,$2", "{r30},{r30},{r30}"
asm volatile("add %0,%1,%2" : : "r" (regI6), "r" (regFP), "r" (reg30));
// CHECK: call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"
asm volatile("fadds %0,%1,%2" : : "f" (fF20), "f" (fF20), "f"(fF20));
// CHECK: call void asm sideeffect "faddd $0,$1,$2", "{f40},{f40},{f40}"
asm volatile("faddd %0,%1,%2" : : "f" (dF40), "f" (dF40), "f"(dF40));
// CHECK: call void asm sideeffect "faddq $0,$1,$2", "{f40},{f40},{f40}"
asm volatile("faddq %0,%1,%2" : : "f" (qF40), "f" (qF40), "f"(qF40));
}