forked from OSchip/llvm-project
Improvements to int->float cast code for PPC-64
llvm-svn: 16105
This commit is contained in:
Nate Begeman
parent
50d140ee3d
commit
8cb6bd5f3c
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@ -2315,68 +2315,60 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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// Handle casts from integer to floating point now...
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if (DestClass == cFP32 || DestClass == cFP64) {
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// Emit a library call for long to float conversion
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if (SrcClass == cLong) {
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std::vector<ValueRecord> Args;
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Args.push_back(ValueRecord(SrcReg, SrcTy));
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Function *floatFn = (DestClass == cFP32) ? __floatdisfFn : __floatdidfFn;
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MachineInstr *TheCall =
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BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
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doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
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return;
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}
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// Make sure we're dealing with a full 32 bits
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unsigned TmpReg = makeAnotherReg(Type::IntTy);
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promote32(TmpReg, ValueRecord(SrcReg, SrcTy));
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SrcReg = TmpReg;
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// Spill the integer to memory and reload it from there.
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// Also spill room for a special conversion constant
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int ConstantFrameIndex =
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F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
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unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
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int ValueFrameIdx =
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F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
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unsigned constantHi = makeAnotherReg(Type::IntTy);
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unsigned constantLo = makeAnotherReg(Type::IntTy);
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unsigned ConstF = makeAnotherReg(Type::DoubleTy);
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unsigned TempF = makeAnotherReg(Type::DoubleTy);
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if (!SrcTy->isSigned()) {
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BuildMI(*BB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
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BuildMI(*BB, IP, PPC::LI, 1, constantLo).addSImm(0);
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addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
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ConstantFrameIndex);
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addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantLo),
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ConstantFrameIndex, 4);
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addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
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ValueFrameIdx);
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addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(SrcReg),
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ValueFrameIdx, 4);
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addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, ConstF),
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ConstantFrameIndex);
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addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
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BuildMI(*BB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
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} else {
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unsigned TempLo = makeAnotherReg(Type::IntTy);
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BuildMI(*BB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
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BuildMI(*BB, IP, PPC::LIS, 1, constantLo).addSImm(0x8000);
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addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
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ConstantFrameIndex);
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addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantLo),
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ConstantFrameIndex, 4);
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addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
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ValueFrameIdx);
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BuildMI(*BB, IP, PPC::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
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addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(TempLo),
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ValueFrameIdx, 4);
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addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, ConstF),
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ConstantFrameIndex);
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addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
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BuildMI(*BB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
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if (SrcClass == cLong) {
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if (SrcTy->isSigned()) {
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addFrameReference(BuildMI(*MBB, IP, PPC::STD, 3).addReg(SrcReg),
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ValueFrameIdx);
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addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TmpReg),
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ValueFrameIdx);
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BuildMI(*MBB, IP, PPC::FCFID, 1, DestReg).addReg(TmpReg);
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} else {
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unsigned Scale = getReg(ConstantFP::get(Type::DoubleTy, 0x1p32));
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unsigned TmpHi = makeAnotherReg(Type::IntTy);
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unsigned TmpLo = makeAnotherReg(Type::IntTy);
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unsigned FPLow = makeAnotherReg(Type::DoubleTy);
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unsigned FPTmpHi = makeAnotherReg(Type::DoubleTy);
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unsigned FPTmpLo = makeAnotherReg(Type::DoubleTy);
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int OtherFrameIdx = F->getFrameInfo()->CreateStackObject(Type::DoubleTy,
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TM.getTargetData());
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BuildMI(*MBB, IP, PPC::RLDICL, 3, TmpHi).addReg(SrcReg).addImm(32)
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.addImm(32);
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BuildMI(*MBB, IP, PPC::RLDICL, 3, TmpLo).addReg(SrcReg).addImm(0)
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.addImm(32);
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addFrameReference(BuildMI(*MBB, IP, PPC::STD, 3).addReg(TmpHi),
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ValueFrameIdx);
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addFrameReference(BuildMI(*MBB, IP, PPC::STD, 3).addReg(TmpLo),
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OtherFrameIdx);
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addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TmpReg),
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ValueFrameIdx);
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addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, FPLow),
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OtherFrameIdx);
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BuildMI(*MBB, IP, PPC::FCFID, 1, FPTmpHi).addReg(TmpReg);
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BuildMI(*MBB, IP, PPC::FCFID, 1, FPTmpLo).addReg(FPLow);
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BuildMI(*MBB, IP, PPC::FMADD, 3, DestReg).addReg(Scale).addReg(FPTmpHi)
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.addReg(FPTmpLo);
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}
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return;
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}
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// FIXME: really want a promote64
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unsigned IntTmp = makeAnotherReg(Type::IntTy);
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if (SrcTy->isSigned())
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BuildMI(*MBB, IP, PPC::EXTSW, 1, IntTmp).addReg(SrcReg);
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else
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BuildMI(*MBB, IP, PPC::RLDICL, 3, IntTmp).addReg(SrcReg).addImm(0)
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.addImm(32);
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addFrameReference(BuildMI(*MBB, IP, PPC::STD, 3).addReg(IntTmp),
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ValueFrameIdx);
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addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TmpReg),
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ValueFrameIdx);
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BuildMI(*MBB, IP, PPC::FCFID, 1, DestReg).addReg(TmpReg);
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return;
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}
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@ -104,6 +104,7 @@ def FADD : AForm_2<"fadd", 63, 21, 0, 0, 0>;
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def FADDS : AForm_2<"fadds", 59, 21, 0, 0, 0>;
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def FSUB : AForm_2<"fsub", 63, 20, 0, 0, 0>;
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def FSUBS : AForm_2<"fsubs", 59, 20, 0, 0, 0>;
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def FMADD : AForm_2<"fmul", 63, 29, 0, 0, 0>;
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def FMUL : AForm_3<"fmul", 63, 25, 0, 0, 0>;
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def FMULS : AForm_3<"fmuls", 59, 25, 0, 0, 0>;
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def FDIV : AForm_2<"fdiv", 63, 18, 0, 0, 0>;
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@ -232,18 +233,24 @@ def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
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"extsb $rA, $rS">;
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def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
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"extsh $rA, $rS">;
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def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
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"extsw $rA, $rS">;
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def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
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"lfsx $dst, $base, $index">;
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def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
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"lfdx $dst, $base, $index">;
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def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
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"fcfid $frD, $frB">;
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def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
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"fctidz $frD, $frB">;
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def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
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"fctiwz $frD, $frB">;
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def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
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"fmr $frD, $frB">;
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def FNEG : XForm_26<63, 80, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
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"fneg $frD, $frB">;
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def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
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"frsp $frD, $frB">;
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def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
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"fctiwz $frD, $frB">;
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def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
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"stfsx $frS, $rA, $rB">;
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def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
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@ -1,10 +1,10 @@
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TODO:
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* switch to auto-generated asm writer
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* use stfiwx in float->int
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* fix rlwimi generation to be use-and-def
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* implement scheduling info
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* implement powerpc-64 for darwin
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* implement powerpc-64 for aix
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* fix rlwimi generation to be use-and-def
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* use stfiwx in float->int
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* should hint to the branch select pass that it doesn't need to print the
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second unconditional branch, so we don't end up with things like:
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b .LBBl42__2E_expand_function_8_674 ; loopentry.24
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